1 /* ----------------------------------------------------------------------------
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2 * SAM Software Package License
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2012, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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33 * Provides the low-level initialization function that called on chip startup.
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36 /*----------------------------------------------------------------------------
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38 *----------------------------------------------------------------------------*/
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43 /*----------------------------------------------------------------------------
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44 * Exported functions
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45 *----------------------------------------------------------------------------*/
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46 /* Default memory map
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47 Address range Memory region Memory type Shareability Cache policy
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48 0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT
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49 0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA
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50 0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable -
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51 0x60000000- 0x7FFFFFFF External RAM Normal Non-shareable WBWA
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52 0x80000000- 0x9FFFFFFF WTb
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53 0xA0000000- 0xBFFFFFFF External device Devicea Shareable
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54 0xC0000000- 0xDFFFFFFF Non-shareablea
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55 0xE0000000- 0xE00FFFFF Private Peripheral Bus Strongly ordered Shareablea -
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56 0xE0100000- 0xFFFFFFFF Vendor-specific device Device Non-shareablea -
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60 * \brief Setup a memory region.
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62 void _SetupMemoryRegion( void )
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67 #ifdef BELOW_CODE_REMOVED_FOR_REASON_STATED_IN_WARNING_MESSAGE_ABOVE
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68 uint32_t dwRegionBaseAddr;
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69 uint32_t dwRegionAttr;
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72 /* ITCM memory region --- Normal */
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73 /* #define ITCM_START_ADDRESS 0x00000000UL
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74 #define ITCM_END_ADDRESS 0x00400000UL
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77 ITCM_START_ADDRESS |
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79 MPU_DEFAULT_ITCM_REGION;
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82 MPU_AP_PRIVILEGED_READ_WRITE |
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83 MPU_TEX_WRITE_THROUGH |
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84 MPU_REGION_CACHEABLE |
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86 MPU_CalMPURegionSize(ITCM_END_ADDRESS - ITCM_START_ADDRESS) |
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89 MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
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91 /* Internal flash privilege memory region --- Normal */
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92 /* #define IFLASH_START_ADDRESS 0x00400000UL
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93 #define IFLASH_END_ADDRESS 0x00600000UL
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96 IFLASH_START_ADDRESS |
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98 MPU_DEFAULT_IFLASH_REGION; //2
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101 MPU_AP_FULL_ACCESS |
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102 MPU_REGION_CACHEABLE |
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103 MPU_TEX_WRITE_THROUGH |
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105 MPU_CalMPURegionSize(IFLASH_END_ADDRESS - IFLASH_START_ADDRESS) |
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108 MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
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111 /* DTCM memory region */
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113 DTCM_START_ADDRESS |
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115 MPU_DEFAULT_DTCM_REGION; //3
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118 MPU_AP_PRIVILEGED_READ_WRITE |
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119 MPU_REGION_CACHEABLE |
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120 MPU_REGION_BUFFERABLE |
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121 MPU_TEX_WRITE_BACK_ALLOCATE |
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123 MPU_CalMPURegionSize(DTCM_END_ADDRESS - DTCM_START_ADDRESS) |
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126 MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
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129 /* SRAM memory privilege region */
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131 SRAM_PRIVILEGE_START_ADDRESS |
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133 MPU_DEFAULT_PRAM_REGION; //4
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136 MPU_AP_FULL_ACCESS |
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137 MPU_REGION_CACHEABLE |
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138 MPU_REGION_BUFFERABLE |
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139 MPU_REGION_SHAREABLE |
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140 MPU_TEX_WRITE_BACK_ALLOCATE|
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142 MPU_CalMPURegionSize(SRAM_PRIVILEGE_END_ADDRESS - SRAM_PRIVILEGE_START_ADDRESS) |
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145 MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
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147 /* SRAM memory un-privilege region */
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149 SRAM_UNPRIVILEGE_START_ADDRESS |
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151 MPU_DEFAULT_UPRAM_REGION; //5
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154 MPU_AP_PRIVILEGED_READ_WRITE |
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155 MPU_REGION_CACHEABLE |
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156 MPU_REGION_BUFFERABLE |
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157 MPU_TEX_WRITE_BACK_ALLOCATE|
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159 MPU_CalMPURegionSize(SRAM_UNPRIVILEGE_END_ADDRESS - SRAM_UNPRIVILEGE_START_ADDRESS) |
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162 MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
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165 /* Peripheral memory region ---- Device */
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166 /* #define PERIPHERALS_START_ADDRESS 0x40000000UL
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167 #define PERIPHERALS_END_ADDRESS 0x400E2000UL
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170 PERIPHERALS_START_ADDRESS |
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172 MPU_PERIPHERALS_REGION; //6
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174 dwRegionAttr = MPU_AP_FULL_ACCESS |
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175 MPU_REGION_EXECUTE_NEVER |
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177 MPU_CalMPURegionSize(PERIPHERALS_END_ADDRESS - PERIPHERALS_START_ADDRESS) |
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180 MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
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182 /* USBHS_ram memory region -External device */
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183 /* #define USBHSRAM_START_ADDRESS 0xA0100000UL
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184 #define USBHSRAM_END_ADDRESS 0xA0200000UL
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187 USBHSRAM_START_ADDRESS |
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189 MPU_USBHSRAM_REGION; //7
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192 MPU_AP_FULL_ACCESS |
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193 MPU_REGION_EXECUTE_NEVER |
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194 MPU_REGION_SHAREABLE |
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196 MPU_CalMPURegionSize(USBHSRAM_END_ADDRESS - USBHSRAM_START_ADDRESS) |
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199 MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
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201 /* QSPI memory region -External RAM -- normal */
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202 /* #define QSPI_START_ADDRESS 0x80000000UL
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203 #define QSPI_END_ADDRESS 0x9FFFFFFFUL
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206 QSPI_START_ADDRESS |
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208 MPU_QSPIMEM_REGION;
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211 MPU_AP_FULL_ACCESS |
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212 MPU_REGION_EXECUTE_NEVER |
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213 MPU_REGION_CACHEABLE |
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214 MPU_REGION_BUFFERABLE |
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215 MPU_TEX_WRITE_BACK_ALLOCATE|
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217 MPU_CalMPURegionSize(QSPI_END_ADDRESS - QSPI_START_ADDRESS) |
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220 MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
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223 /* SDRAM memory region */
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225 SDRAM_START_ADDRESS |
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230 MPU_REGION_READ_WRITE |
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231 MPU_REGION_CACHEABLE |
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232 MPU_REGION_BUFFERABLE |
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234 MPU_CalMPURegionSize(SDRAM_END_ADDRESS - SDRAM_START_ADDRESS) |
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237 MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
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241 /* Enable the memory management fault , Bus Fault, Usage Fault exception */
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242 SCB->SHCSR |= (SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_USGFAULTENA_Msk);
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244 /* Enable the MPU region */
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245 MPU_Enable( MPU_ENABLE | MPU_BGENABLE );
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246 #endif /* BELOW_CODE_REMOVED_FOR_REASON_STATED_IN_WARNING_MESSAGE_ABOVE */
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252 * \brief Performs the low-level initialization of the chip.
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253 * This includes EFC and master clock configuration.
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254 * It also enable a low level on the pin NRST triggers a user reset.
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256 extern WEAK void LowLevelInit( void )
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258 /* Set 6 FWS for Embedded Flash Access */
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259 EFC->EEFC_FMR = EEFC_FMR_FWS(6);
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260 if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) ) /* Main Oscillator Selection */
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262 SUPC_SelectExtCrystal32K();
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263 PMC_DisableAllClocks();
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264 PMC_SetMckSelection(PMC_MCKR_CSS_SLOW_CLK, PMC_MCKR_PRES_CLK_1);
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265 /* Then, enable Main XTAL oscillator */
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266 PMC_EnableExtOsc();
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267 PMC_SelectExtOsc();
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268 PMC_SetMckSelection(PMC_MCKR_CSS_MAIN_CLK, PMC_MCKR_PRES_CLK_1);
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269 /* wait Main CLK Ready */
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270 while(!(PMC->CKGR_MCFR & CKGR_MCFR_MAINFRDY));
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271 /* Then, cofigure PLLA and switch clock */
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272 PMC_ConfigureMckWithPlla(0x16, 0x1, PMC_MCKR_PRES_CLK_1);
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273 PMC->PMC_MCKR |= 1 << 8;
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274 while( !(PMC->PMC_SR & PMC_SR_MCKRDY) );
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277 _SetupMemoryRegion();
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