1 /* ----------------------------------------------------------------------------
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2 * SAM Software Package License
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2012, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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33 /*----------------------------------------------------------------------------
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35 *----------------------------------------------------------------------------*/
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36 #define ARM_MODE_USR 0x10
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38 #define PRIVILEGE_MODE 0
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43 //#define FLASH_SIZE
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44 //#define ISRAM_SIZE
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46 #define MPU_UNPRIVILEGED_RAM_REGION ( 0 )
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47 #define MPU_PRIVILEGE_RAM_REGION ( 1 )
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48 #define MPU_UNPRIVILEGED_FLASH_REGION ( 2 )
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49 #define MPU_PRIVILEGED_FLASH_REGION ( 3 )
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50 #define MPU_PRIVILEGED_PERIPHERALS_REGION ( 4 )
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51 #define MPU_UART_REGION_REGION ( 5 )
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52 #define MPU_SDRAM_REGION ( 6 )
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55 #define MPU_DEFAULT_ITCM_REGION ( 1 )
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56 #define MPU_DEFAULT_IFLASH_REGION ( 2 )
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57 #define MPU_DEFAULT_DTCM_REGION ( 3 )
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58 #define MPU_DEFAULT_PRAM_REGION ( 4 )
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59 #define MPU_DEFAULT_UPRAM_REGION ( 5 )
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60 #define MPU_PERIPHERALS_REGION ( 6 )
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61 #define MPU_USBHSRAM_REGION ( 7 )
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62 #define MPU_QSPIMEM_REGION ( 8 )
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66 #define MPU_QSPIMEM_REGION ( 0 )
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67 #define MPU_USBHSRAM_REGION ( 1 )
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68 #define MPU_PERIPHERALS_REGION ( 2 )
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69 #define MPU_DEFAULT_DTCM_REGION ( 3 )
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70 #define MPU_DEFAULT_ITCM_REGION ( 4 )
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71 #define MPU_DEFAULT_UPRAM_REGION ( 5 )
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72 #define MPU_DEFAULT_IFLASH_REGION ( 6 )
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73 #define MPU_DEFAULT_PRAM_REGION ( 7 )
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81 #define MPU_REGION_VALID ( 0x10 )
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82 #define MPU_REGION_ENABLE ( 0x01 )
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83 #define MPU_REGION_DISABLE ( 0x0 )
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85 #define MPU_ENABLE ( 0x1 )
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86 #define MPU_BGENABLE ( 0x1 << 2 )
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88 #define PROTECT_PIO_SUBREGION ( 0x1 << 4 )
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90 #define MPU_REGION_BUFFERABLE ( 0x01 << MPU_RASR_B_Pos )
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91 #define MPU_REGION_CACHEABLE ( 0x01 << MPU_RASR_C_Pos )
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92 #define MPU_REGION_SHAREABLE ( 0x01 << MPU_RASR_S_Pos )
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94 #define MPU_REGION_EXECUTE_NEVER ( 0x01 << MPU_RASR_XN_Pos )
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96 #define MPU_AP_NO_ACCESS ( 0x00 << MPU_RASR_AP_Pos )
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97 #define MPU_AP_PRIVILEGED_READ_WRITE ( 0x01 << MPU_RASR_AP_Pos )
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98 #define MPU_AP_UNPRIVILEGED_READONLY ( 0x02 << MPU_RASR_AP_Pos )
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99 #define MPU_AP_FULL_ACCESS ( 0x03 << MPU_RASR_AP_Pos )
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100 #define MPU_AP_RES ( 0x04 << MPU_RASR_AP_Pos )
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101 #define MPU_AP_PRIVILEGED_READONLY ( 0x05 << MPU_RASR_AP_Pos )
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102 #define MPU_AP_READONLY ( 0x06 << MPU_RASR_AP_Pos )
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103 #define MPU_AP_READONLY2 ( 0x07 << MPU_RASR_AP_Pos )
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105 #define MPU_TEX_NON_CACHE ( 0x04 << MPU_RASR_TEX_Pos )
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106 #define MPU_TEX_WRITE_BACK_ALLOCATE ( 0x05 << MPU_RASR_TEX_Pos )
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107 #define MPU_TEX_WRITE_THROUGH ( 0x06 << MPU_RASR_TEX_Pos )
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108 #define MPU_TEX_WRITE_BACK_NOALLOCATE ( 0x07 << MPU_RASR_TEX_Pos )
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110 /* Default memory map
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111 Address range Memory region Memory type Shareability Cache policy
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112 0x00000000- 0x1FFFFFFF Code Normal Non-shareablea WTb
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113 0x20000000- 0x3FFFFFFF SRAM Normal Non-shareablea WBWAb
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114 0x40000000- 0x5FFFFFFF Peripheral Device Non-shareablea -
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115 0x60000000- 0x7FFFFFFF External RAM Normal Non-shareablea WBWAb
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116 0x80000000- 0x9FFFFFFF WTb
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117 0xA0000000- 0xBFFFFFFF External device Devicea Shareable
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118 0xC0000000- 0xDFFFFFFF Non-shareablea
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119 0xE0000000- 0xE00FFFFF Private Peripheral Bus Strongly ordered Shareablea -
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120 0xE0100000- 0xFFFFFFFF Vendor-specific device Device Non-shareablea -
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123 /********* IFLASH memory macros *********************/
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124 #define ITCM_START_ADDRESS 0x00000000UL
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125 #define ITCM_END_ADDRESS 0x00400000UL
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126 #define IFLASH_START_ADDRESS 0x00400000UL
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127 #define IFLASH_END_ADDRESS 0x00600000UL
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128 #define IFLASH_HALF ((IFLASH_END_ADDRESS - IFLASH_START_ADDRESS) >> 1)
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130 #define IFLASH_PRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS)
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131 #define IFLASH_PRIVILEGE_END_ADDRESS (IFLASH_START_ADDRESS + IFLASH_HALF)
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133 #define IFLASH_UNPRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS + IFLASH_HALF + 1)
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134 #define IFLASH_UNPRIVILEGE_END_ADDRESS (IFLASH_END_ADDRESS)
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136 /**************** DTCM *******************************/
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137 #define DTCM_START_ADDRESS 0x20000000UL
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138 #define DTCM_END_ADDRESS 0x20400000UL
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141 /******* SRAM memory macros ***************************/
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143 #define SRAM_START_ADDRESS 0x20400000UL
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144 #define SRAM_END_ADDRESS 0x2045FFFFUL
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145 #define SRAM_HALF ((SRAM_END_ADDRESS - SRAM_START_ADDRESS) >>1)
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148 #define SRAM_PRIVILEGE_START_ADDRESS (SRAM_START_ADDRESS)
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149 #define SRAM_PRIVILEGE_END_ADDRESS (SRAM_START_ADDRESS + 0x3FFFF)
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151 #define SRAM_UNPRIVILEGE_START_ADDRESS (SRAM_PRIVILEGE_END_ADDRESS + 1)
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152 #define SRAM_UNPRIVILEGE_END_ADDRESS (SRAM_END_ADDRESS)
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154 /************** Peripherials memory region macros ********/
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156 #define PERIPHERALS_START_ADDRESS 0x40000000UL
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157 #define PERIPHERALS_END_ADDRESS 0x400E2000UL
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159 #define UART_REGION_START_ADDRESS 0x400E1C00UL
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160 #define UART_REGION_END_ADDRESS 0x400E2000UL
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162 /************** Peripherials memory region macros ********/
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164 #define PERIPHERALS_START_ADDRESS 0x40000000UL
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165 #define PERIPHERALS_END_ADDRESS 0x400E2000UL
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167 /************** QSPI region macros ******************/
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169 #define QSPI_START_ADDRESS 0x80000000UL
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170 #define QSPI_END_ADDRESS 0x9FFFFFFFUL
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172 /************** USBHS_RAM region macros ******************/
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174 #define USBHSRAM_START_ADDRESS 0xA0100000UL
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175 #define USBHSRAM_END_ADDRESS 0xA0200000UL
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177 /******* Ext-SRAM memory macros ***************************/
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179 #define SDRAM_START_ADDRESS 0x70000000UL
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180 #define SDRAM_END_ADDRESS 0x7FFFFFFFUL
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182 /** Flag to indicate whether the svc is done */
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183 extern volatile uint32_t dwRaisePriDone;
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184 /*----------------------------------------------------------------------------
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186 *----------------------------------------------------------------------------*/
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187 void MPU_Enable( uint32_t dwMPUEnable );
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188 void MPU_SetRegion( uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr );
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189 void MPU_SetRegionNum( uint32_t dwRegionNum );
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190 void MPU_DisableRegion( void );
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191 uint32_t MPU_CalMPURegionSize( uint32_t dwActualSizeInBytes );
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192 void MPU_UpdateRegions( uint32_t dwRegionNum, uint32_t dwRegionBaseAddr,
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193 uint32_t dwRegionAttr);
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195 #endif /* #ifndef _MMU_ */
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