1 /* ---------------------------------------------------------------------------- */
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2 /* Atmel Microcontroller Software Support */
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3 /* SAM Software Package License */
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4 /* ---------------------------------------------------------------------------- */
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5 /* Copyright (c) 2014, Atmel Corporation */
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7 /* All rights reserved. */
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9 /* Redistribution and use in source and binary forms, with or without */
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10 /* modification, are permitted provided that the following condition is met: */
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12 /* - Redistributions of source code must retain the above copyright notice, */
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13 /* this list of conditions and the disclaimer below. */
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15 /* Atmel's name may not be used to endorse or promote products derived from */
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16 /* this software without specific prior written permission. */
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18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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28 /* ---------------------------------------------------------------------------- */
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30 #ifndef _SAM_SMC_COMPONENT_
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31 #define _SAM_SMC_COMPONENT_
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33 /* ============================================================================= */
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34 /** SOFTWARE API DEFINITION FOR Static Memory Controller */
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35 /* ============================================================================= */
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36 /** \addtogroup SAM_SMC Static Memory Controller */
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39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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40 /** \brief SmcCs_number hardware registers */
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42 __IO uint32_t SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
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43 __IO uint32_t SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
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44 __IO uint32_t SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
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45 __IO uint32_t SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */
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47 /** \brief Smc hardware registers */
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48 #define SMCCS_NUMBER_NUMBER 4
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50 SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 3 */
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51 __I uint32_t Reserved1[16];
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52 __IO uint32_t SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */
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53 __O uint32_t SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */
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54 __O uint32_t SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */
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55 __I uint32_t Reserved2[22];
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56 __IO uint32_t SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */
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57 __I uint32_t SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */
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58 __I uint32_t SMC_ADDRSIZE; /**< \brief (Smc Offset: 0xEC) SMC Address Size Register */
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59 __I uint32_t SMC_IPNAME[2]; /**< \brief (Smc Offset: 0xF0) SMC IP Name 1 Register */
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60 __I uint32_t SMC_FEATURES; /**< \brief (Smc Offset: 0xF8) SMC Features Register */
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61 __I uint32_t SMC_VERSION; /**< \brief (Smc Offset: 0xFC) SMC Version Register */
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63 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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64 /* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
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65 #define SMC_SETUP_NWE_SETUP_Pos 0
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66 #define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
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67 #define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
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68 #define SMC_SETUP_NCS_WR_SETUP_Pos 8
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69 #define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */
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70 #define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
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71 #define SMC_SETUP_NRD_SETUP_Pos 16
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72 #define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
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73 #define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
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74 #define SMC_SETUP_NCS_RD_SETUP_Pos 24
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75 #define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */
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76 #define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
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77 /* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
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78 #define SMC_PULSE_NWE_PULSE_Pos 0
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79 #define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
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80 #define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
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81 #define SMC_PULSE_NCS_WR_PULSE_Pos 8
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82 #define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
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83 #define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
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84 #define SMC_PULSE_NRD_PULSE_Pos 16
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85 #define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
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86 #define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
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87 #define SMC_PULSE_NCS_RD_PULSE_Pos 24
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88 #define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
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89 #define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
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90 /* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
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91 #define SMC_CYCLE_NWE_CYCLE_Pos 0
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92 #define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
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93 #define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
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94 #define SMC_CYCLE_NRD_CYCLE_Pos 16
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95 #define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
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96 #define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
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97 /* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */
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98 #define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) */
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99 #define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) */
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100 #define SMC_MODE_EXNW_MODE_Pos 4
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101 #define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
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102 #define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
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103 #define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
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104 #define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
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105 #define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */
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106 #define SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit Data Bus */
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107 #define SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit Data Bus */
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108 #define SMC_MODE_TDF_CYCLES_Pos 16
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109 #define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
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110 #define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
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111 #define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
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112 #define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */
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113 #define SMC_MODE_PS_Pos 28
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114 #define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */
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115 #define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */
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116 #define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */
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117 #define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */
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118 #define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */
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119 /* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */
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120 #define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
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121 /* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */
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122 #define SMC_KEY1_KEY1_Pos 0
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123 #define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
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124 #define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
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125 /* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */
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126 #define SMC_KEY2_KEY2_Pos 0
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127 #define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
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128 #define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
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129 /* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */
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130 #define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */
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131 #define SMC_WPMR_WPKEY_Pos 8
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132 #define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protect KEY */
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133 #define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)))
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134 /* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */
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135 #define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protect Enable */
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136 #define SMC_WPSR_WPVSRC_Pos 8
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137 #define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protect Violation Source */
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138 /* -------- SMC_ADDRSIZE : (SMC Offset: 0xEC) SMC Address Size Register -------- */
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139 #define SMC_ADDRSIZE_ADDRSIZE_Pos 0
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140 #define SMC_ADDRSIZE_ADDRSIZE_Msk (0xffffu << SMC_ADDRSIZE_ADDRSIZE_Pos) /**< \brief (SMC_ADDRSIZE) User Interface Address Size */
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141 /* -------- SMC_IPNAME[2] : (SMC Offset: 0xF0) SMC IP Name 1 Register -------- */
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142 #define SMC_IPNAME_IPNAME_Pos 0
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143 #define SMC_IPNAME_IPNAME_Msk (0xffffffffu << SMC_IPNAME_IPNAME_Pos) /**< \brief (SMC_IPNAME[2]) ASCII Report of the IP Name */
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144 /* -------- SMC_VERSION : (SMC Offset: 0xFC) SMC Version Register -------- */
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145 #define SMC_VERSION_VERSION_Pos 0
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146 #define SMC_VERSION_VERSION_Msk (0xfffu << SMC_VERSION_VERSION_Pos) /**< \brief (SMC_VERSION) Hardware Module Version */
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147 #define SMC_VERSION_MFN_Pos 16
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148 #define SMC_VERSION_MFN_Msk (0x7u << SMC_VERSION_MFN_Pos) /**< \brief (SMC_VERSION) Metal Fix Number */
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153 #endif /* _SAM_SMC_COMPONENT_ */
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