1 /* ---------------------------------------------------------------------------- */
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2 /* Atmel Microcontroller Software Support */
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3 /* SAM Software Package License */
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4 /* ---------------------------------------------------------------------------- */
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5 /* Copyright (c) 2014, Atmel Corporation */
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7 /* All rights reserved. */
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9 /* Redistribution and use in source and binary forms, with or without */
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10 /* modification, are permitted provided that the following condition is met: */
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12 /* - Redistributions of source code must retain the above copyright notice, */
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13 /* this list of conditions and the disclaimer below. */
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15 /* Atmel's name may not be used to endorse or promote products derived from */
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16 /* this software without specific prior written permission. */
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18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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28 /* ---------------------------------------------------------------------------- */
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30 #ifndef _SAM_AFEC0_INSTANCE_
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31 #define _SAM_AFEC0_INSTANCE_
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33 /* ========== Register definition for AFEC0 peripheral ========== */
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34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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35 #define REG_AFEC0_CR (0x4003C000U) /**< \brief (AFEC0) AFEC Control Register */
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36 #define REG_AFEC0_MR (0x4003C004U) /**< \brief (AFEC0) AFEC Mode Register */
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37 #define REG_AFEC0_EMR (0x4003C008U) /**< \brief (AFEC0) AFEC Extended Mode Register */
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38 #define REG_AFEC0_SEQ1R (0x4003C00CU) /**< \brief (AFEC0) AFEC Channel Sequence 1 Register */
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39 #define REG_AFEC0_SEQ2R (0x4003C010U) /**< \brief (AFEC0) AFEC Channel Sequence 2 Register */
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40 #define REG_AFEC0_CHER (0x4003C014U) /**< \brief (AFEC0) AFEC Channel Enable Register */
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41 #define REG_AFEC0_CHDR (0x4003C018U) /**< \brief (AFEC0) AFEC Channel Disable Register */
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42 #define REG_AFEC0_CHSR (0x4003C01CU) /**< \brief (AFEC0) AFEC Channel Status Register */
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43 #define REG_AFEC0_LCDR (0x4003C020U) /**< \brief (AFEC0) AFEC Last Converted Data Register */
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44 #define REG_AFEC0_IER (0x4003C024U) /**< \brief (AFEC0) AFEC Interrupt Enable Register */
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45 #define REG_AFEC0_IDR (0x4003C028U) /**< \brief (AFEC0) AFEC Interrupt Disable Register */
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46 #define REG_AFEC0_IMR (0x4003C02CU) /**< \brief (AFEC0) AFEC Interrupt Mask Register */
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47 #define REG_AFEC0_ISR (0x4003C030U) /**< \brief (AFEC0) AFEC Interrupt Status Register */
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48 #define REG_AFEC0_OVER (0x4003C04CU) /**< \brief (AFEC0) AFEC Overrun Status Register */
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49 #define REG_AFEC0_CWR (0x4003C050U) /**< \brief (AFEC0) AFEC Compare Window Register */
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50 #define REG_AFEC0_CG1R (0x4003C054U) /**< \brief (AFEC0) AFEC Channel Gain 1 Register */
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51 #define REG_AFEC0_CG2R (0x4003C058U) /**< \brief (AFEC0) AFEC Channel Gain 2 Register */
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52 #define REG_AFEC0_DIFFR (0x4003C060U) /**< \brief (AFEC0) AFEC Channel Differential Register */
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53 #define REG_AFEC0_CSELR (0x4003C064U) /**< \brief (AFEC0) AFEC Channel Register Selection */
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54 #define REG_AFEC0_CDR (0x4003C068U) /**< \brief (AFEC0) AFEC Channel Data Register */
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55 #define REG_AFEC0_COCR (0x4003C06CU) /**< \brief (AFEC0) AFEC Channel Offset Compensation Register */
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56 #define REG_AFEC0_TEMPMR (0x4003C070U) /**< \brief (AFEC0) AFEC Temperature Sensor Mode Register */
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57 #define REG_AFEC0_TEMPCWR (0x4003C074U) /**< \brief (AFEC0) AFEC Temperature Compare Window Register */
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58 #define REG_AFEC0_ACR (0x4003C094U) /**< \brief (AFEC0) AFEC Analog Control Register */
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59 #define REG_AFEC0_SHMR (0x4003C0A0U) /**< \brief (AFEC0) AFEC Sample & Hold Mode Register */
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60 #define REG_AFEC0_COSR (0x4003C0D0U) /**< \brief (AFEC0) AFEC Correction Select Register */
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61 #define REG_AFEC0_CVR (0x4003C0D4U) /**< \brief (AFEC0) AFEC Correction Values Register */
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62 #define REG_AFEC0_CECR (0x4003C0D8U) /**< \brief (AFEC0) AFEC Channel Error Correction Register */
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63 #define REG_AFEC0_WPMR (0x4003C0E4U) /**< \brief (AFEC0) AFEC Write Protection Mode Register */
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64 #define REG_AFEC0_WPSR (0x4003C0E8U) /**< \brief (AFEC0) AFEC Write Protection Status Register */
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65 #define REG_AFEC0_VERSION (0x4003C0FCU) /**< \brief (AFEC0) AFEC Version Register */
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67 #define REG_AFEC0_CR (*(__O uint32_t*)0x4003C000U) /**< \brief (AFEC0) AFEC Control Register */
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68 #define REG_AFEC0_MR (*(__IO uint32_t*)0x4003C004U) /**< \brief (AFEC0) AFEC Mode Register */
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69 #define REG_AFEC0_EMR (*(__IO uint32_t*)0x4003C008U) /**< \brief (AFEC0) AFEC Extended Mode Register */
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70 #define REG_AFEC0_SEQ1R (*(__IO uint32_t*)0x4003C00CU) /**< \brief (AFEC0) AFEC Channel Sequence 1 Register */
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71 #define REG_AFEC0_SEQ2R (*(__IO uint32_t*)0x4003C010U) /**< \brief (AFEC0) AFEC Channel Sequence 2 Register */
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72 #define REG_AFEC0_CHER (*(__O uint32_t*)0x4003C014U) /**< \brief (AFEC0) AFEC Channel Enable Register */
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73 #define REG_AFEC0_CHDR (*(__O uint32_t*)0x4003C018U) /**< \brief (AFEC0) AFEC Channel Disable Register */
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74 #define REG_AFEC0_CHSR (*(__I uint32_t*)0x4003C01CU) /**< \brief (AFEC0) AFEC Channel Status Register */
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75 #define REG_AFEC0_LCDR (*(__I uint32_t*)0x4003C020U) /**< \brief (AFEC0) AFEC Last Converted Data Register */
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76 #define REG_AFEC0_IER (*(__O uint32_t*)0x4003C024U) /**< \brief (AFEC0) AFEC Interrupt Enable Register */
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77 #define REG_AFEC0_IDR (*(__O uint32_t*)0x4003C028U) /**< \brief (AFEC0) AFEC Interrupt Disable Register */
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78 #define REG_AFEC0_IMR (*(__I uint32_t*)0x4003C02CU) /**< \brief (AFEC0) AFEC Interrupt Mask Register */
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79 #define REG_AFEC0_ISR (*(__I uint32_t*)0x4003C030U) /**< \brief (AFEC0) AFEC Interrupt Status Register */
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80 #define REG_AFEC0_OVER (*(__I uint32_t*)0x4003C04CU) /**< \brief (AFEC0) AFEC Overrun Status Register */
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81 #define REG_AFEC0_CWR (*(__IO uint32_t*)0x4003C050U) /**< \brief (AFEC0) AFEC Compare Window Register */
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82 #define REG_AFEC0_CG1R (*(__IO uint32_t*)0x4003C054U) /**< \brief (AFEC0) AFEC Channel Gain 1 Register */
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83 #define REG_AFEC0_CG2R (*(__IO uint32_t*)0x4003C058U) /**< \brief (AFEC0) AFEC Channel Gain 2 Register */
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84 #define REG_AFEC0_DIFFR (*(__IO uint32_t*)0x4003C060U) /**< \brief (AFEC0) AFEC Channel Differential Register */
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85 #define REG_AFEC0_CSELR (*(__IO uint32_t*)0x4003C064U) /**< \brief (AFEC0) AFEC Channel Register Selection */
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86 #define REG_AFEC0_CDR (*(__I uint32_t*)0x4003C068U) /**< \brief (AFEC0) AFEC Channel Data Register */
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87 #define REG_AFEC0_COCR (*(__IO uint32_t*)0x4003C06CU) /**< \brief (AFEC0) AFEC Channel Offset Compensation Register */
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88 #define REG_AFEC0_TEMPMR (*(__IO uint32_t*)0x4003C070U) /**< \brief (AFEC0) AFEC Temperature Sensor Mode Register */
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89 #define REG_AFEC0_TEMPCWR (*(__IO uint32_t*)0x4003C074U) /**< \brief (AFEC0) AFEC Temperature Compare Window Register */
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90 #define REG_AFEC0_ACR (*(__IO uint32_t*)0x4003C094U) /**< \brief (AFEC0) AFEC Analog Control Register */
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91 #define REG_AFEC0_SHMR (*(__IO uint32_t*)0x4003C0A0U) /**< \brief (AFEC0) AFEC Sample & Hold Mode Register */
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92 #define REG_AFEC0_COSR (*(__IO uint32_t*)0x4003C0D0U) /**< \brief (AFEC0) AFEC Correction Select Register */
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93 #define REG_AFEC0_CVR (*(__IO uint32_t*)0x4003C0D4U) /**< \brief (AFEC0) AFEC Correction Values Register */
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94 #define REG_AFEC0_CECR (*(__IO uint32_t*)0x4003C0D8U) /**< \brief (AFEC0) AFEC Channel Error Correction Register */
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95 #define REG_AFEC0_WPMR (*(__IO uint32_t*)0x4003C0E4U) /**< \brief (AFEC0) AFEC Write Protection Mode Register */
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96 #define REG_AFEC0_WPSR (*(__I uint32_t*)0x4003C0E8U) /**< \brief (AFEC0) AFEC Write Protection Status Register */
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97 #define REG_AFEC0_VERSION (*(__I uint32_t*)0x4003C0FCU) /**< \brief (AFEC0) AFEC Version Register */
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98 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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100 #endif /* _SAM_AFEC0_INSTANCE_ */
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