1 /* ---------------------------------------------------------------------------- */
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2 /* Atmel Microcontroller Software Support */
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3 /* SAM Software Package License */
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4 /* ---------------------------------------------------------------------------- */
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5 /* Copyright (c) 2014, Atmel Corporation */
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7 /* All rights reserved. */
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9 /* Redistribution and use in source and binary forms, with or without */
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10 /* modification, are permitted provided that the following condition is met: */
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12 /* - Redistributions of source code must retain the above copyright notice, */
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13 /* this list of conditions and the disclaimer below. */
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15 /* Atmel's name may not be used to endorse or promote products derived from */
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16 /* this software without specific prior written permission. */
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18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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28 /* ---------------------------------------------------------------------------- */
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30 #ifndef _SAM_MATRIX_INSTANCE_
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31 #define _SAM_MATRIX_INSTANCE_
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33 /* ========== Register definition for MATRIX peripheral ========== */
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34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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35 #define REG_MATRIX_MCFG (0x40088000U) /**< \brief (MATRIX) Master Configuration Register */
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36 #define REG_MATRIX_SCFG (0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */
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37 #define REG_MATRIX_PRAS0 (0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
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38 #define REG_MATRIX_PRBS0 (0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */
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39 #define REG_MATRIX_PRAS1 (0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
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40 #define REG_MATRIX_PRBS1 (0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */
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41 #define REG_MATRIX_PRAS2 (0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
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42 #define REG_MATRIX_PRBS2 (0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */
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43 #define REG_MATRIX_PRAS3 (0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
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44 #define REG_MATRIX_PRBS3 (0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */
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45 #define REG_MATRIX_PRAS4 (0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
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46 #define REG_MATRIX_PRBS4 (0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */
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47 #define REG_MATRIX_PRAS5 (0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
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48 #define REG_MATRIX_PRBS5 (0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */
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49 #define REG_MATRIX_PRAS6 (0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
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50 #define REG_MATRIX_PRBS6 (0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */
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51 #define REG_MATRIX_PRAS7 (0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
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52 #define REG_MATRIX_PRBS7 (0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */
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53 #define REG_MATRIX_PRAS8 (0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
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54 #define REG_MATRIX_PRBS8 (0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */
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55 #define REG_MATRIX_PRAS9 (0x400880C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */
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56 #define REG_MATRIX_PRBS9 (0x400880CCU) /**< \brief (MATRIX) Priority Register B for Slave 9 */
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57 #define REG_MATRIX_PRAS10 (0x400880D0U) /**< \brief (MATRIX) Priority Register A for Slave 10 */
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58 #define REG_MATRIX_PRBS10 (0x400880D4U) /**< \brief (MATRIX) Priority Register B for Slave 10 */
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59 #define REG_MATRIX_PRAS11 (0x400880D8U) /**< \brief (MATRIX) Priority Register A for Slave 11 */
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60 #define REG_MATRIX_PRBS11 (0x400880DCU) /**< \brief (MATRIX) Priority Register B for Slave 11 */
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61 #define REG_MATRIX_PRAS12 (0x400880E0U) /**< \brief (MATRIX) Priority Register A for Slave 12 */
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62 #define REG_MATRIX_PRBS12 (0x400880E4U) /**< \brief (MATRIX) Priority Register B for Slave 12 */
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63 #define REG_MATRIX_PRAS13 (0x400880E8U) /**< \brief (MATRIX) Priority Register A for Slave 13 */
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64 #define REG_MATRIX_PRBS13 (0x400880ECU) /**< \brief (MATRIX) Priority Register B for Slave 13 */
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65 #define REG_MATRIX_PRAS14 (0x400880F0U) /**< \brief (MATRIX) Priority Register A for Slave 14 */
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66 #define REG_MATRIX_PRBS14 (0x400880F4U) /**< \brief (MATRIX) Priority Register B for Slave 14 */
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67 #define REG_MATRIX_PRAS15 (0x400880F8U) /**< \brief (MATRIX) Priority Register A for Slave 15 */
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68 #define REG_MATRIX_PRBS15 (0x400880FCU) /**< \brief (MATRIX) Priority Register B for Slave 15 */
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69 #define REG_MATRIX_MRCR (0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */
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70 #define REG_MATRIX_SFR (0x40088110U) /**< \brief (MATRIX) Special Function Register */
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71 #define REG_MATRIX_MEIER (0x40088150U) /**< \brief (MATRIX) Master Error Interrupt Enable Register */
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72 #define REG_MATRIX_MEIDR (0x40088154U) /**< \brief (MATRIX) Master Error Interrupt Disable Register */
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73 #define REG_MATRIX_MEIMR (0x40088158U) /**< \brief (MATRIX) Master Error Interrupt Mask Register */
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74 #define REG_MATRIX_MESR (0x4008815CU) /**< \brief (MATRIX) Master Error Status Register */
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75 #define REG_MATRIX_MEAR (0x40088160U) /**< \brief (MATRIX) Master 0 Error Address Register */
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76 #define REG_MATRIX_WPMR (0x400881E4U) /**< \brief (MATRIX) Write Protect Mode Register */
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77 #define REG_MATRIX_WPSR (0x400881E8U) /**< \brief (MATRIX) Write Protect Status Register */
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78 #define REG_MATRIX_VERSION (0x400881FCU) /**< \brief (MATRIX) Version Register */
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79 #define REG_MATRIX_SSR (0x40088200U) /**< \brief (MATRIX) Security Slave 0 Register */
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80 #define REG_MATRIX_SASSR (0x40088240U) /**< \brief (MATRIX) Security Areas Split Slave 0 Register */
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81 #define REG_MATRIX_SRTSR (0x40088280U) /**< \brief (MATRIX) Security Region Top Slave 0 Register */
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82 #define REG_MATRIX_SPSELR (0x400882C0U) /**< \brief (MATRIX) Security Peripheral Select 1 Register */
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84 #define REG_MATRIX_MCFG (*(__IO uint32_t*)0x40088000U) /**< \brief (MATRIX) Master Configuration Register */
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85 #define REG_MATRIX_SCFG (*(__IO uint32_t*)0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */
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86 #define REG_MATRIX_PRAS0 (*(__IO uint32_t*)0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
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87 #define REG_MATRIX_PRBS0 (*(__IO uint32_t*)0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */
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88 #define REG_MATRIX_PRAS1 (*(__IO uint32_t*)0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
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89 #define REG_MATRIX_PRBS1 (*(__IO uint32_t*)0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */
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90 #define REG_MATRIX_PRAS2 (*(__IO uint32_t*)0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
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91 #define REG_MATRIX_PRBS2 (*(__IO uint32_t*)0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */
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92 #define REG_MATRIX_PRAS3 (*(__IO uint32_t*)0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
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93 #define REG_MATRIX_PRBS3 (*(__IO uint32_t*)0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */
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94 #define REG_MATRIX_PRAS4 (*(__IO uint32_t*)0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
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95 #define REG_MATRIX_PRBS4 (*(__IO uint32_t*)0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */
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96 #define REG_MATRIX_PRAS5 (*(__IO uint32_t*)0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
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97 #define REG_MATRIX_PRBS5 (*(__IO uint32_t*)0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */
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98 #define REG_MATRIX_PRAS6 (*(__IO uint32_t*)0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
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99 #define REG_MATRIX_PRBS6 (*(__IO uint32_t*)0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */
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100 #define REG_MATRIX_PRAS7 (*(__IO uint32_t*)0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
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101 #define REG_MATRIX_PRBS7 (*(__IO uint32_t*)0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */
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102 #define REG_MATRIX_PRAS8 (*(__IO uint32_t*)0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
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103 #define REG_MATRIX_PRBS8 (*(__IO uint32_t*)0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */
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104 #define REG_MATRIX_PRAS9 (*(__IO uint32_t*)0x400880C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */
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105 #define REG_MATRIX_PRBS9 (*(__IO uint32_t*)0x400880CCU) /**< \brief (MATRIX) Priority Register B for Slave 9 */
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106 #define REG_MATRIX_PRAS10 (*(__IO uint32_t*)0x400880D0U) /**< \brief (MATRIX) Priority Register A for Slave 10 */
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107 #define REG_MATRIX_PRBS10 (*(__IO uint32_t*)0x400880D4U) /**< \brief (MATRIX) Priority Register B for Slave 10 */
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108 #define REG_MATRIX_PRAS11 (*(__IO uint32_t*)0x400880D8U) /**< \brief (MATRIX) Priority Register A for Slave 11 */
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109 #define REG_MATRIX_PRBS11 (*(__IO uint32_t*)0x400880DCU) /**< \brief (MATRIX) Priority Register B for Slave 11 */
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110 #define REG_MATRIX_PRAS12 (*(__IO uint32_t*)0x400880E0U) /**< \brief (MATRIX) Priority Register A for Slave 12 */
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111 #define REG_MATRIX_PRBS12 (*(__IO uint32_t*)0x400880E4U) /**< \brief (MATRIX) Priority Register B for Slave 12 */
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112 #define REG_MATRIX_PRAS13 (*(__IO uint32_t*)0x400880E8U) /**< \brief (MATRIX) Priority Register A for Slave 13 */
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113 #define REG_MATRIX_PRBS13 (*(__IO uint32_t*)0x400880ECU) /**< \brief (MATRIX) Priority Register B for Slave 13 */
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114 #define REG_MATRIX_PRAS14 (*(__IO uint32_t*)0x400880F0U) /**< \brief (MATRIX) Priority Register A for Slave 14 */
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115 #define REG_MATRIX_PRBS14 (*(__IO uint32_t*)0x400880F4U) /**< \brief (MATRIX) Priority Register B for Slave 14 */
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116 #define REG_MATRIX_PRAS15 (*(__IO uint32_t*)0x400880F8U) /**< \brief (MATRIX) Priority Register A for Slave 15 */
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117 #define REG_MATRIX_PRBS15 (*(__IO uint32_t*)0x400880FCU) /**< \brief (MATRIX) Priority Register B for Slave 15 */
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118 #define REG_MATRIX_MRCR (*(__IO uint32_t*)0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */
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119 #define REG_MATRIX_SFR (*(__IO uint32_t*)0x40088110U) /**< \brief (MATRIX) Special Function Register */
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120 #define REG_MATRIX_MEIER (*(__O uint32_t*)0x40088150U) /**< \brief (MATRIX) Master Error Interrupt Enable Register */
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121 #define REG_MATRIX_MEIDR (*(__O uint32_t*)0x40088154U) /**< \brief (MATRIX) Master Error Interrupt Disable Register */
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122 #define REG_MATRIX_MEIMR (*(__I uint32_t*)0x40088158U) /**< \brief (MATRIX) Master Error Interrupt Mask Register */
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123 #define REG_MATRIX_MESR (*(__I uint32_t*)0x4008815CU) /**< \brief (MATRIX) Master Error Status Register */
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124 #define REG_MATRIX_MEAR (*(__I uint32_t*)0x40088160U) /**< \brief (MATRIX) Master 0 Error Address Register */
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125 #define REG_MATRIX_WPMR (*(__IO uint32_t*)0x400881E4U) /**< \brief (MATRIX) Write Protect Mode Register */
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126 #define REG_MATRIX_WPSR (*(__I uint32_t*)0x400881E8U) /**< \brief (MATRIX) Write Protect Status Register */
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127 #define REG_MATRIX_VERSION (*(__I uint32_t*)0x400881FCU) /**< \brief (MATRIX) Version Register */
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128 #define REG_MATRIX_SSR (*(__IO uint32_t*)0x40088200U) /**< \brief (MATRIX) Security Slave 0 Register */
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129 #define REG_MATRIX_SASSR (*(__IO uint32_t*)0x40088240U) /**< \brief (MATRIX) Security Areas Split Slave 0 Register */
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130 #define REG_MATRIX_SRTSR (*(__IO uint32_t*)0x40088280U) /**< \brief (MATRIX) Security Region Top Slave 0 Register */
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131 #define REG_MATRIX_SPSELR (*(__IO uint32_t*)0x400882C0U) /**< \brief (MATRIX) Security Peripheral Select 1 Register */
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132 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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134 #endif /* _SAM_MATRIX_INSTANCE_ */
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