1 /* ---------------------------------------------------------------------------- */
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2 /* Atmel Microcontroller Software Support */
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3 /* SAM Software Package License */
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4 /* ---------------------------------------------------------------------------- */
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5 /* Copyright (c) 2014, Atmel Corporation */
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7 /* All rights reserved. */
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9 /* Redistribution and use in source and binary forms, with or without */
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10 /* modification, are permitted provided that the following condition is met: */
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12 /* - Redistributions of source code must retain the above copyright notice, */
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13 /* this list of conditions and the disclaimer below. */
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15 /* Atmel's name may not be used to endorse or promote products derived from */
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16 /* this software without specific prior written permission. */
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18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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28 /* ---------------------------------------------------------------------------- */
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33 /** \addtogroup SAMV71N21_definitions SAMV71N21 definitions
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34 This file defines all structures and symbols for SAMV71N21:
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35 - registers and bitfields
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36 - peripheral base address
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46 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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50 /* ************************************************************************** */
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51 /* CMSIS DEFINITIONS FOR SAMV71N21 */
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52 /* ************************************************************************** */
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53 /** \addtogroup SAMV71N21_cmsis CMSIS Definitions */
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56 /**< Interrupt Number Definition */
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59 /****** Cortex-M4 Processor Exceptions Numbers ******************************/
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60 NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
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61 MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */
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62 BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */
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63 UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */
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64 SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */
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65 DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
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66 PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */
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67 SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */
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68 /****** SAMV71N21 specific Interrupt Numbers *********************************/
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70 SUPC_IRQn = 0, /**< 0 SAMV71N21 Supply Controller (SUPC) */
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71 RSTC_IRQn = 1, /**< 1 SAMV71N21 Reset Controller (RSTC) */
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72 RTC_IRQn = 2, /**< 2 SAMV71N21 Real Time Clock (RTC) */
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73 RTT_IRQn = 3, /**< 3 SAMV71N21 Real Time Timer (RTT) */
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74 WDT0_IRQn = 4, /**< 4 SAMV71N21 Watchdog Timer 0 (WDT0) */
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75 PMC_IRQn = 5, /**< 5 SAMV71N21 Power Management Controller (PMC) */
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76 EFC_IRQn = 6, /**< 6 SAMV71N21 Enhanced Embedded Flash Controller (EFC) */
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77 UART0_IRQn = 7, /**< 7 SAMV71N21 UART 0 (UART0) */
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78 UART1_IRQn = 8, /**< 8 SAMV71N21 UART 1 (UART1) */
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79 PIOA_IRQn = 10, /**< 10 SAMV71N21 Parallel I/O Controller A (PIOA) */
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80 PIOB_IRQn = 11, /**< 11 SAMV71N21 Parallel I/O Controller B (PIOB) */
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81 USART0_IRQn = 13, /**< 13 SAMV71N21 USART 0 (USART0) */
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82 USART1_IRQn = 14, /**< 14 SAMV71N21 USART 1 (USART1) */
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83 USART2_IRQn = 15, /**< 15 SAMV71N21 USART 2 (USART2) */
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84 PIOD_IRQn = 16, /**< 16 SAMV71N21 Parallel I/O Controller D (PIOD) */
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85 HSMCI_IRQn = 18, /**< 18 SAMV71N21 Multimedia Card Interface (HSMCI) */
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86 TWI0_IRQn = 19, /**< 19 SAMV71N21 Two Wire Interface 0 HS (TWI0) */
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87 TWI1_IRQn = 20, /**< 20 SAMV71N21 Two Wire Interface 1 HS (TWI1) */
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88 SPI0_IRQn = 21, /**< 21 SAMV71N21 Serial Peripheral Interface 0 (SPI0) */
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89 SSC_IRQn = 22, /**< 22 SAMV71N21 Synchronous Serial Controller (SSC) */
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90 TC0_IRQn = 23, /**< 23 SAMV71N21 Timer/Counter 0 (TC0) */
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91 TC1_IRQn = 24, /**< 24 SAMV71N21 Timer/Counter 1 (TC1) */
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92 TC2_IRQn = 25, /**< 25 SAMV71N21 Timer/Counter 2 (TC2) */
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93 AFEC0_IRQn = 29, /**< 29 SAMV71N21 Analog Front End 0 (AFEC0) */
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94 PWM0_IRQn = 31, /**< 31 SAMV71N21 Pulse Width Modulation 0 (PWM0) */
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95 ICM_IRQn = 32, /**< 32 SAMV71N21 Integrity Check Monitor (ICM) */
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96 ACC_IRQn = 33, /**< 33 SAMV71N21 Analog Comparator (ACC) */
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97 USBHS_IRQn = 34, /**< 34 SAMV71N21 USB Host / Device Controller (USBHS) */
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98 GMAC_IRQn = 39, /**< 39 SAMV71N21 Ethernet MAC (GMAC) */
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99 AFEC1_IRQn = 40, /**< 40 SAMV71N21 Analog Front End 1 (AFEC1) */
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100 TWI2_IRQn = 41, /**< 41 SAMV71N21 Two Wire Interface 2 HS (TWI2) */
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101 SPI1_IRQn = 42, /**< 42 SAMV71N21 Serial Peripheral Interface 1 (SPI1) */
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102 QSPI_IRQn = 43, /**< 43 SAMV71N21 Quad I/O Serial Peripheral Interface (QSPI) */
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103 UART2_IRQn = 44, /**< 44 SAMV71N21 UART 2 (UART2) */
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104 UART3_IRQn = 45, /**< 45 SAMV71N21 UART 3 (UART3) */
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105 UART4_IRQn = 46, /**< 46 SAMV71N21 UART 4 (UART4) */
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106 TC9_IRQn = 50, /**< 50 SAMV71N21 Timer/Counter 9 (TC9) */
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107 TC10_IRQn = 51, /**< 51 SAMV71N21 Timer/Counter 10 (TC10) */
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108 TC11_IRQn = 52, /**< 52 SAMV71N21 Timer/Counter 11 (TC11) */
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109 AES_IRQn = 56, /**< 56 SAMV71N21 AES (AES) */
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110 TRNG_IRQn = 57, /**< 57 SAMV71N21 True Random Generator (TRNG) */
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111 XDMAC_IRQn = 58, /**< 58 SAMV71N21 DMA (XDMAC) */
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112 ISI_IRQn = 59, /**< 59 SAMV71N21 Camera Interface (ISI) */
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113 PWM1_IRQn = 60, /**< 60 SAMV71N21 Pulse Width Modulation 1 (PWM1) */
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114 WDT1_IRQn = 63, /**< 63 SAMV71N21 Watchdog Timer 1 (WDT1) */
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116 PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
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119 typedef struct _DeviceVectors
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121 /* Stack pointer */
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124 /* Cortex-M handlers */
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125 void* pfnReset_Handler;
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126 void* pfnNMI_Handler;
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127 void* pfnHardFault_Handler;
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128 void* pfnMemManage_Handler;
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129 void* pfnBusFault_Handler;
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130 void* pfnUsageFault_Handler;
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131 void* pfnReserved1_Handler;
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132 void* pfnReserved2_Handler;
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133 void* pfnReserved3_Handler;
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134 void* pfnReserved4_Handler;
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135 void* pfnSVC_Handler;
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136 void* pfnDebugMon_Handler;
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137 void* pfnReserved5_Handler;
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138 void* pfnPendSV_Handler;
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139 void* pfnSysTick_Handler;
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141 /* Peripheral handlers */
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142 void* pfnSUPC_Handler; /* 0 Supply Controller */
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143 void* pfnRSTC_Handler; /* 1 Reset Controller */
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144 void* pfnRTC_Handler; /* 2 Real Time Clock */
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145 void* pfnRTT_Handler; /* 3 Real Time Timer */
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146 void* pfnWDT0_Handler; /* 4 Watchdog Timer 0 */
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147 void* pfnPMC_Handler; /* 5 Power Management Controller */
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148 void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
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149 void* pfnUART0_Handler; /* 7 UART 0 */
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150 void* pfnUART1_Handler; /* 8 UART 1 */
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152 void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
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153 void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
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154 void* pvReserved12;
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155 void* pfnUSART0_Handler; /* 13 USART 0 */
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156 void* pfnUSART1_Handler; /* 14 USART 1 */
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157 void* pfnUSART2_Handler; /* 15 USART 2 */
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158 void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
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159 void* pvReserved17;
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160 void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
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161 void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 HS */
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162 void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 HS */
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163 void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
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164 void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
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165 void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
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166 void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
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167 void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
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168 void* pvReserved26;
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169 void* pvReserved27;
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170 void* pvReserved28;
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171 void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
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172 void* pvReserved30;
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173 void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
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174 void* pfnICM_Handler; /* 32 Integrity Check Monitor */
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175 void* pfnACC_Handler; /* 33 Analog Comparator */
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176 void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
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177 void* pvReserved35;
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178 void* pvReserved36;
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179 void* pvReserved37;
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180 void* pvReserved38;
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181 void* pfnGMAC_Handler; /* 39 Ethernet MAC */
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182 void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
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183 void* pfnTWI2_Handler; /* 41 Two Wire Interface 2 HS */
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184 void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
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185 void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
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186 void* pfnUART2_Handler; /* 44 UART 2 */
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187 void* pfnUART3_Handler; /* 45 UART 3 */
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188 void* pfnUART4_Handler; /* 46 UART 4 */
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189 void* pvReserved47;
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190 void* pvReserved48;
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191 void* pvReserved49;
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192 void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
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193 void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
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194 void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
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195 void* pvReserved53;
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196 void* pvReserved54;
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197 void* pvReserved55;
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198 void* pfnAES_Handler; /* 56 AES */
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199 void* pfnTRNG_Handler; /* 57 True Random Generator */
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200 void* pfnXDMAC_Handler; /* 58 DMA */
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201 void* pfnISI_Handler; /* 59 Camera Interface */
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202 void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
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203 void* pvReserved61;
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204 void* pvReserved62;
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205 void* pfnWDT1_Handler; /* 63 Watchdog Timer 1 */
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208 /* Cortex-M4 core handlers */
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209 void Reset_Handler ( void );
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210 void NMI_Handler ( void );
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211 void HardFault_Handler ( void );
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212 void MemManage_Handler ( void );
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213 void BusFault_Handler ( void );
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214 void UsageFault_Handler ( void );
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215 void SVC_Handler ( void );
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216 void DebugMon_Handler ( void );
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217 void PendSV_Handler ( void );
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218 void SysTick_Handler ( void );
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220 /* Peripherals handlers */
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221 void ACC_Handler ( void );
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222 void AES_Handler ( void );
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223 void AFEC0_Handler ( void );
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224 void AFEC1_Handler ( void );
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225 void EFC_Handler ( void );
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226 void GMAC_Handler ( void );
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227 void HSMCI_Handler ( void );
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228 void ICM_Handler ( void );
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229 void ISI_Handler ( void );
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230 void PIOA_Handler ( void );
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231 void PIOB_Handler ( void );
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232 void PIOD_Handler ( void );
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233 void PMC_Handler ( void );
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234 void PWM0_Handler ( void );
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235 void PWM1_Handler ( void );
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236 void QSPI_Handler ( void );
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237 void RSTC_Handler ( void );
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238 void RTC_Handler ( void );
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239 void RTT_Handler ( void );
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240 void SPI0_Handler ( void );
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241 void SPI1_Handler ( void );
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242 void SSC_Handler ( void );
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243 void SUPC_Handler ( void );
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244 void TC0_Handler ( void );
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245 void TC1_Handler ( void );
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246 void TC2_Handler ( void );
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247 void TC9_Handler ( void );
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248 void TC10_Handler ( void );
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249 void TC11_Handler ( void );
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250 void TRNG_Handler ( void );
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251 void TWI0_Handler ( void );
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252 void TWI1_Handler ( void );
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253 void TWI2_Handler ( void );
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254 void UART0_Handler ( void );
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255 void UART1_Handler ( void );
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256 void UART2_Handler ( void );
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257 void UART3_Handler ( void );
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258 void UART4_Handler ( void );
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259 void USART0_Handler ( void );
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260 void USART1_Handler ( void );
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261 void USART2_Handler ( void );
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262 void USBHS_Handler ( void );
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263 void WDT0_Handler ( void );
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264 void WDT1_Handler ( void );
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265 void XDMAC_Handler ( void );
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268 * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
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271 #define __CM4_REV 0x0000 /**< SAMV71N21 core revision number ([15:8] revision number, [7:0] patch number) */
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272 #define __MPU_PRESENT 1 /**< SAMV71N21 does provide a MPU */
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273 #define __FPU_PRESENT 1 /**< SAMV71N21 does provide a FPU */
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274 #define __NVIC_PRIO_BITS 3 /**< SAMV71N21 uses 3 Bits for the Priority Levels */
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275 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
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278 * \brief CMSIS includes
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281 #include <core_cm4.h>
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282 #if !defined DONT_USE_CMSIS_INIT
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283 #include "system_sam.h"
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284 #endif /* DONT_USE_CMSIS_INIT */
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288 /* ************************************************************************** */
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289 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71N21 */
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290 /* ************************************************************************** */
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291 /** \addtogroup SAMV71N21_api Peripheral Software API */
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294 #include "component/component_acc.h"
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295 #include "component/component_aes.h"
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296 #include "component/component_afec.h"
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297 #include "component/component_chipid.h"
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298 #include "component/component_efc.h"
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299 #include "component/component_gmac.h"
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300 #include "component/component_gpbr.h"
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301 #include "component/component_hsmci.h"
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302 #include "component/component_icm.h"
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303 #include "component/component_isi.h"
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304 #include "component/component_matrix.h"
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305 #include "component/component_pio.h"
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306 #include "component/component_pmc.h"
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307 #include "component/component_pwm.h"
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308 #include "component/component_qspi.h"
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309 #include "component/component_rstc.h"
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310 #include "component/component_rtc.h"
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311 #include "component/component_rtt.h"
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312 #include "component/component_spi.h"
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313 #include "component/component_ssc.h"
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314 #include "component/component_supc.h"
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315 #include "component/component_tc.h"
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316 #include "component/component_trng.h"
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317 #include "component/component_twi.h"
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318 #include "component/component_twihs.h"
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319 #include "component/component_uart.h"
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320 #include "component/component_uotghs.h"
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321 #include "component/component_usart.h"
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322 #include "component/component_wdt.h"
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323 #include "component/component_xdmac.h"
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326 /* ************************************************************************** */
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327 /* REGISTER ACCESS DEFINITIONS FOR SAMV71N21 */
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328 /* ************************************************************************** */
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329 /** \addtogroup SAMV71N21_reg Registers Access Definitions */
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332 #include "instance/instance_hsmci.h"
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333 #include "instance/instance_ssc.h"
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334 #include "instance/instance_spi0.h"
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335 #include "instance/instance_tc0.h"
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336 #include "instance/instance_twi0.h"
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337 #include "instance/instance_twi1.h"
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338 #include "instance/instance_pwm0.h"
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339 #include "instance/instance_usart0.h"
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340 #include "instance/instance_usart1.h"
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341 #include "instance/instance_usart2.h"
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342 #include "instance/instance_usbhs.h"
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343 #include "instance/instance_afec0.h"
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344 #include "instance/instance_acc.h"
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345 #include "instance/instance_icm.h"
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346 #include "instance/instance_isi.h"
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347 #include "instance/instance_gmac.h"
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348 #include "instance/instance_tc3.h"
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349 #include "instance/instance_spi1.h"
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350 #include "instance/instance_pwm1.h"
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351 #include "instance/instance_twi2.h"
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352 #include "instance/instance_afec1.h"
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353 #include "instance/instance_aes.h"
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354 #include "instance/instance_trng.h"
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355 #include "instance/instance_xdmac.h"
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356 #include "instance/instance_qspi.h"
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357 #include "instance/instance_matrix.h"
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358 #include "instance/instance_pmc.h"
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359 #include "instance/instance_uart0.h"
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360 #include "instance/instance_chipid.h"
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361 #include "instance/instance_uart1.h"
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362 #include "instance/instance_efc.h"
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363 #include "instance/instance_pioa.h"
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364 #include "instance/instance_piob.h"
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365 #include "instance/instance_piod.h"
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366 #include "instance/instance_rstc.h"
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367 #include "instance/instance_supc.h"
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368 #include "instance/instance_rtt.h"
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369 #include "instance/instance_wdt0.h"
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370 #include "instance/instance_rtc.h"
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371 #include "instance/instance_gpbr.h"
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372 #include "instance/instance_wdt1.h"
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373 #include "instance/instance_uart2.h"
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374 #include "instance/instance_uart3.h"
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375 #include "instance/instance_uart4.h"
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378 /* ************************************************************************** */
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379 /* PERIPHERAL ID DEFINITIONS FOR SAMV71N21 */
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380 /* ************************************************************************** */
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381 /** \addtogroup SAMV71N21_id Peripheral Ids Definitions */
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384 #define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
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385 #define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
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386 #define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
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387 #define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
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388 #define ID_WDT0 ( 4) /**< \brief Watchdog Timer 0 (WDT0) */
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389 #define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
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390 #define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
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391 #define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
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392 #define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
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393 #define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
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394 #define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
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395 #define ID_USART0 (13) /**< \brief USART 0 (USART0) */
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396 #define ID_USART1 (14) /**< \brief USART 1 (USART1) */
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397 #define ID_USART2 (15) /**< \brief USART 2 (USART2) */
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398 #define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
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399 #define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
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400 #define ID_TWI0 (19) /**< \brief Two Wire Interface 0 HS (TWI0) */
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401 #define ID_TWI1 (20) /**< \brief Two Wire Interface 1 HS (TWI1) */
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402 #define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
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403 #define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
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404 #define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
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405 #define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
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406 #define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
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407 #define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
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408 #define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
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409 #define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
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410 #define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
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411 #define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
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412 #define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */
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413 #define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
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414 #define ID_TWI2 (41) /**< \brief Two Wire Interface 2 HS (TWI2) */
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415 #define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
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416 #define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
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417 #define ID_UART2 (44) /**< \brief UART 2 (UART2) */
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418 #define ID_UART3 (45) /**< \brief UART 3 (UART3) */
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419 #define ID_UART4 (46) /**< \brief UART 4 (UART4) */
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420 #define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
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421 #define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
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422 #define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
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423 #define ID_AES (56) /**< \brief AES (AES) */
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424 #define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
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425 #define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
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426 #define ID_ISI (59) /**< \brief Camera Interface (ISI) */
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427 #define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
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428 #define ID_WDT1 (63) /**< \brief Watchdog Timer 1 (WDT1) */
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430 #define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
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433 /* ************************************************************************** */
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434 /* BASE ADDRESS DEFINITIONS FOR SAMV71N21 */
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435 /* ************************************************************************** */
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436 /** \addtogroup SAMV71N21_base Peripheral Base Address Definitions */
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439 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
\r
440 #define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
\r
441 #define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
\r
442 #define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
\r
443 #define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
\r
444 #define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */
\r
445 #define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */
\r
446 #define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
\r
447 #define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
\r
448 #define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
\r
449 #define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
\r
450 #define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
\r
451 #define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
\r
452 #define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
\r
453 #define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
\r
454 #define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
\r
455 #define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */
\r
456 #define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
\r
457 #define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
\r
458 #define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
\r
459 #define TWI2 (0x40060000U) /**< \brief (TWI2 ) Base Address */
\r
460 #define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
\r
461 #define AES (0x4006C000U) /**< \brief (AES ) Base Address */
\r
462 #define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
\r
463 #define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
\r
464 #define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
\r
465 #define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
\r
466 #define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
\r
467 #define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
\r
468 #define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
\r
469 #define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
\r
470 #define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
\r
471 #define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
\r
472 #define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
\r
473 #define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
\r
474 #define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
\r
475 #define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
\r
476 #define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
\r
477 #define WDT0 (0x400E1850U) /**< \brief (WDT0 ) Base Address */
\r
478 #define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
\r
479 #define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
\r
480 #define WDT1 (0x400E1900U) /**< \brief (WDT1 ) Base Address */
\r
481 #define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
\r
482 #define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
\r
483 #define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
\r
485 #define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
\r
486 #define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
\r
487 #define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
\r
488 #define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
\r
489 #define TWI0 ((Twihs *)0x40018000U) /**< \brief (TWI0 ) Base Address */
\r
490 #define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */
\r
491 #define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
\r
492 #define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
\r
493 #define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
\r
494 #define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
\r
495 #define USBHS ((Uotghs *)0x40038000U) /**< \brief (USBHS ) Base Address */
\r
496 #define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
\r
497 #define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
\r
498 #define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
\r
499 #define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
\r
500 #define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */
\r
501 #define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
\r
502 #define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
\r
503 #define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
\r
504 #define TWI2 ((Twi *)0x40060000U) /**< \brief (TWI2 ) Base Address */
\r
505 #define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
\r
506 #define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
\r
507 #define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
\r
508 #define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
\r
509 #define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
\r
510 #define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
\r
511 #define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
\r
512 #define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
\r
513 #define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
\r
514 #define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
\r
515 #define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
\r
516 #define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
\r
517 #define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
\r
518 #define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
\r
519 #define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
\r
520 #define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
\r
521 #define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
\r
522 #define WDT0 ((Wdt *)0x400E1850U) /**< \brief (WDT0 ) Base Address */
\r
523 #define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
\r
524 #define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
\r
525 #define WDT1 ((Wdt *)0x400E1900U) /**< \brief (WDT1 ) Base Address */
\r
526 #define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
\r
527 #define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
\r
528 #define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
\r
529 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
532 /* ************************************************************************** */
\r
533 /* PIO DEFINITIONS FOR SAMV71N21 */
\r
534 /* ************************************************************************** */
\r
535 /** \addtogroup SAMV71N21_pio Peripheral Pio Definitions */
\r
538 #include "pio/pio_samv71n21.h"
\r
541 /* ************************************************************************** */
\r
542 /* MEMORY MAPPING DEFINITIONS FOR SAMV71N21 */
\r
543 /* ************************************************************************** */
\r
545 #define IFLASH_SIZE (0x80000u)
\r
546 #define IFLASH_PAGE_SIZE (512u)
\r
547 #define IFLASH_LOCK_REGION_SIZE (8192u)
\r
548 #define IFLASH_NB_OF_PAGES (4096u)
\r
549 #define IFLASH_NB_OF_LOCK_BITS (128u)
\r
550 #define IRAM_SIZE (0x40000u)
\r
552 #define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
\r
553 #define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
\r
554 #define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
\r
555 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
\r
556 #define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
\r
557 #define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
\r
558 #define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
\r
559 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
\r
560 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
\r
561 #define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
\r
562 #define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
\r
563 #define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
\r
565 /* ************************************************************************** */
\r
566 /* MISCELLANEOUS DEFINITIONS FOR SAMV71N21 */
\r
567 /* ************************************************************************** */
\r
569 #define CHIP_JTAGID (0x05B3D03FUL)
\r
570 #define CHIP_CIDR (0xA1220E00UL)
\r
571 #define CHIP_EXID (0x00000001UL)
\r
573 /* ************************************************************************** */
\r
574 /* ELECTRICAL DEFINITIONS FOR SAMV71N21 */
\r
575 /* ************************************************************************** */
\r
577 /* Device characteristics */
\r
578 #define CHIP_FREQ_SLCK_RC_MIN (20000UL)
\r
579 #define CHIP_FREQ_SLCK_RC (32000UL)
\r
580 #define CHIP_FREQ_SLCK_RC_MAX (44000UL)
\r
581 #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
\r
582 #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
\r
583 #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
\r
584 #define CHIP_FREQ_CPU_MAX (120000000UL)
\r
585 #define CHIP_FREQ_XTAL_32K (32768UL)
\r
586 #define CHIP_FREQ_XTAL_12M (12000000UL)
\r
588 /* Embedded Flash Write Wait State */
\r
589 #define CHIP_FLASH_WRITE_WAIT_STATE (6U)
\r
591 /* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
\r
592 #define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
\r
593 #define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
\r
594 #define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
\r
595 #define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
\r
596 #define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
\r
597 #define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
\r
605 #endif /* _SAMV71N21_ */
\r