1 /* ---------------------------------------------------------------------------- */
\r
2 /* Atmel Microcontroller Software Support */
\r
3 /* SAM Software Package License */
\r
4 /* ---------------------------------------------------------------------------- */
\r
5 /* Copyright (c) 2014, Atmel Corporation */
\r
7 /* All rights reserved. */
\r
9 /* Redistribution and use in source and binary forms, with or without */
\r
10 /* modification, are permitted provided that the following condition is met: */
\r
12 /* - Redistributions of source code must retain the above copyright notice, */
\r
13 /* this list of conditions and the disclaimer below. */
\r
15 /* Atmel's name may not be used to endorse or promote products derived from */
\r
16 /* this software without specific prior written permission. */
\r
18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
\r
19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
\r
20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
\r
21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
\r
22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
\r
23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
\r
24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
\r
25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
\r
26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
\r
27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
\r
28 /* ---------------------------------------------------------------------------- */
\r
33 /** \addtogroup SAMV71Q21_definitions SAMV71Q21 definitions
\r
34 This file defines all structures and symbols for SAMV71Q21:
\r
35 - registers and bitfields
\r
36 - peripheral base address
\r
46 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
\r
50 /* ************************************************************************** */
\r
51 /* CMSIS DEFINITIONS FOR SAMV71Q21 */
\r
52 /* ************************************************************************** */
\r
53 /** \addtogroup SAMV71Q21_cmsis CMSIS Definitions */
\r
56 /**< Interrupt Number Definition */
\r
59 /****** Cortex-M4 Processor Exceptions Numbers ******************************/
\r
60 NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
\r
61 MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */
\r
62 BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */
\r
63 UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */
\r
64 SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */
\r
65 DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
\r
66 PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */
\r
67 SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */
\r
68 /****** SAMV71Q21 specific Interrupt Numbers *********************************/
\r
70 SUPC_IRQn = 0, /**< 0 SAMV71Q21 Supply Controller (SUPC) */
\r
71 RSTC_IRQn = 1, /**< 1 SAMV71Q21 Reset Controller (RSTC) */
\r
72 RTC_IRQn = 2, /**< 2 SAMV71Q21 Real Time Clock (RTC) */
\r
73 RTT_IRQn = 3, /**< 3 SAMV71Q21 Real Time Timer (RTT) */
\r
74 WDT0_IRQn = 4, /**< 4 SAMV71Q21 Watchdog Timer 0 (WDT0) */
\r
75 PMC_IRQn = 5, /**< 5 SAMV71Q21 Power Management Controller (PMC) */
\r
76 EFC_IRQn = 6, /**< 6 SAMV71Q21 Enhanced Embedded Flash Controller (EFC) */
\r
77 UART0_IRQn = 7, /**< 7 SAMV71Q21 UART 0 (UART0) */
\r
78 UART1_IRQn = 8, /**< 8 SAMV71Q21 UART 1 (UART1) */
\r
79 PIOA_IRQn = 10, /**< 10 SAMV71Q21 Parallel I/O Controller A (PIOA) */
\r
80 PIOB_IRQn = 11, /**< 11 SAMV71Q21 Parallel I/O Controller B (PIOB) */
\r
81 PIOC_IRQn = 12, /**< 12 SAMV71Q21 Parallel I/O Controller C (PIOC) */
\r
82 USART0_IRQn = 13, /**< 13 SAMV71Q21 USART 0 (USART0) */
\r
83 USART1_IRQn = 14, /**< 14 SAMV71Q21 USART 1 (USART1) */
\r
84 USART2_IRQn = 15, /**< 15 SAMV71Q21 USART 2 (USART2) */
\r
85 PIOD_IRQn = 16, /**< 16 SAMV71Q21 Parallel I/O Controller D (PIOD) */
\r
86 PIOE_IRQn = 17, /**< 17 SAMV71Q21 Parallel I/O Controller E (PIOE) */
\r
87 HSMCI_IRQn = 18, /**< 18 SAMV71Q21 Multimedia Card Interface (HSMCI) */
\r
88 TWI0_IRQn = 19, /**< 19 SAMV71Q21 Two Wire Interface 0 HS (TWI0) */
\r
89 TWI1_IRQn = 20, /**< 20 SAMV71Q21 Two Wire Interface 1 HS (TWI1) */
\r
90 SPI0_IRQn = 21, /**< 21 SAMV71Q21 Serial Peripheral Interface 0 (SPI0) */
\r
91 SSC_IRQn = 22, /**< 22 SAMV71Q21 Synchronous Serial Controller (SSC) */
\r
92 TC0_IRQn = 23, /**< 23 SAMV71Q21 Timer/Counter 0 (TC0) */
\r
93 TC1_IRQn = 24, /**< 24 SAMV71Q21 Timer/Counter 1 (TC1) */
\r
94 TC2_IRQn = 25, /**< 25 SAMV71Q21 Timer/Counter 2 (TC2) */
\r
95 TC3_IRQn = 26, /**< 26 SAMV71Q21 Timer/Counter 3 (TC3) */
\r
96 TC4_IRQn = 27, /**< 27 SAMV71Q21 Timer/Counter 4 (TC4) */
\r
97 TC5_IRQn = 28, /**< 28 SAMV71Q21 Timer/Counter 5 (TC5) */
\r
98 AFEC0_IRQn = 29, /**< 29 SAMV71Q21 Analog Front End 0 (AFEC0) */
\r
99 DACC_IRQn = 30, /**< 30 SAMV71Q21 Digital To Analog Converter (DACC) */
\r
100 PWM0_IRQn = 31, /**< 31 SAMV71Q21 Pulse Width Modulation 0 (PWM0) */
\r
101 ICM_IRQn = 32, /**< 32 SAMV71Q21 Integrity Check Monitor (ICM) */
\r
102 ACC_IRQn = 33, /**< 33 SAMV71Q21 Analog Comparator (ACC) */
\r
103 USBHS_IRQn = 34, /**< 34 SAMV71Q21 USB Host / Device Controller (USBHS) */
\r
104 GMAC_IRQn = 39, /**< 39 SAMV71Q21 Ethernet MAC (GMAC) */
\r
105 AFEC1_IRQn = 40, /**< 40 SAMV71Q21 Analog Front End 1 (AFEC1) */
\r
106 TWI2_IRQn = 41, /**< 41 SAMV71Q21 Two Wire Interface 2 HS (TWI2) */
\r
107 SPI1_IRQn = 42, /**< 42 SAMV71Q21 Serial Peripheral Interface 1 (SPI1) */
\r
108 QSPI_IRQn = 43, /**< 43 SAMV71Q21 Quad I/O Serial Peripheral Interface (QSPI) */
\r
109 UART2_IRQn = 44, /**< 44 SAMV71Q21 UART 2 (UART2) */
\r
110 UART3_IRQn = 45, /**< 45 SAMV71Q21 UART 3 (UART3) */
\r
111 UART4_IRQn = 46, /**< 46 SAMV71Q21 UART 4 (UART4) */
\r
112 TC6_IRQn = 47, /**< 47 SAMV71Q21 Timer/Counter 6 (TC6) */
\r
113 TC7_IRQn = 48, /**< 48 SAMV71Q21 Timer/Counter 7 (TC7) */
\r
114 TC8_IRQn = 49, /**< 49 SAMV71Q21 Timer/Counter 8 (TC8) */
\r
115 TC9_IRQn = 50, /**< 50 SAMV71Q21 Timer/Counter 9 (TC9) */
\r
116 TC10_IRQn = 51, /**< 51 SAMV71Q21 Timer/Counter 10 (TC10) */
\r
117 TC11_IRQn = 52, /**< 52 SAMV71Q21 Timer/Counter 11 (TC11) */
\r
118 AES_IRQn = 56, /**< 56 SAMV71Q21 AES (AES) */
\r
119 TRNG_IRQn = 57, /**< 57 SAMV71Q21 True Random Generator (TRNG) */
\r
120 XDMAC_IRQn = 58, /**< 58 SAMV71Q21 DMA (XDMAC) */
\r
121 ISI_IRQn = 59, /**< 59 SAMV71Q21 Camera Interface (ISI) */
\r
122 PWM1_IRQn = 60, /**< 60 SAMV71Q21 Pulse Width Modulation 1 (PWM1) */
\r
123 SDRAMC_IRQn = 62, /**< 62 SAMV71Q21 SDRAM Controller (SDRAMC) */
\r
124 WDT1_IRQn = 63, /**< 63 SAMV71Q21 Watchdog Timer 1 (WDT1) */
\r
125 CCW_IRQn = 64, /**< 64 SAMV71Q21 ARM Cache ECC Warning */
\r
126 CCF_IRQn = 65, /**< 65 SAMV71Q21 ARM Cache ECC Fault */
\r
127 GMACQ1_IRQn = 66, /**< 66 SAMV71Q21 GMAC Queue 1 Handler */
\r
128 GMACQ2_IRQn = 67, /**< 67 SAMV71Q21 GMAC Queue 2 Handler */
\r
130 PERIPH_COUNT_IRQn = 68 /**< Number of peripheral IDs */
\r
133 typedef struct _DeviceVectors
\r
135 /* Stack pointer */
\r
138 /* Cortex-M handlers */
\r
139 void* pfnReset_Handler;
\r
140 void* pfnNMI_Handler;
\r
141 void* pfnHardFault_Handler;
\r
142 void* pfnMemManage_Handler;
\r
143 void* pfnBusFault_Handler;
\r
144 void* pfnUsageFault_Handler;
\r
145 void* pfnReserved1_Handler;
\r
146 void* pfnReserved2_Handler;
\r
147 void* pfnReserved3_Handler;
\r
148 void* pfnReserved4_Handler;
\r
149 void* pfnSVC_Handler;
\r
150 void* pfnDebugMon_Handler;
\r
151 void* pfnReserved5_Handler;
\r
152 void* pfnPendSV_Handler;
\r
153 void* pfnSysTick_Handler;
\r
155 /* Peripheral handlers */
\r
156 void* pfnSUPC_Handler; /* 0 Supply Controller */
\r
157 void* pfnRSTC_Handler; /* 1 Reset Controller */
\r
158 void* pfnRTC_Handler; /* 2 Real Time Clock */
\r
159 void* pfnRTT_Handler; /* 3 Real Time Timer */
\r
160 void* pfnWDT0_Handler; /* 4 Watchdog Timer 0 */
\r
161 void* pfnPMC_Handler; /* 5 Power Management Controller */
\r
162 void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
\r
163 void* pfnUART0_Handler; /* 7 UART 0 */
\r
164 void* pfnUART1_Handler; /* 8 UART 1 */
\r
166 void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
\r
167 void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
\r
168 void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */
\r
169 void* pfnUSART0_Handler; /* 13 USART 0 */
\r
170 void* pfnUSART1_Handler; /* 14 USART 1 */
\r
171 void* pfnUSART2_Handler; /* 15 USART 2 */
\r
172 void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
\r
173 void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */
\r
174 void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
\r
175 void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 HS */
\r
176 void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 HS */
\r
177 void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
\r
178 void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
\r
179 void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
\r
180 void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
\r
181 void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
\r
182 void* pfnTC3_Handler; /* 26 Timer/Counter 3 */
\r
183 void* pfnTC4_Handler; /* 27 Timer/Counter 4 */
\r
184 void* pfnTC5_Handler; /* 28 Timer/Counter 5 */
\r
185 void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
\r
186 void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
\r
187 void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
\r
188 void* pfnICM_Handler; /* 32 Integrity Check Monitor */
\r
189 void* pfnACC_Handler; /* 33 Analog Comparator */
\r
190 void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
\r
191 void* pfnCAN0_Handler;
\r
192 void* pvReserved36;
\r
193 void* pfnCAN1_Handler;
\r
194 void* pvReserved38;
\r
195 void* pfnGMAC_Handler; /* 39 Ethernet MAC */
\r
196 void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
\r
197 void* pfnTWI2_Handler; /* 41 Two Wire Interface 2 HS */
\r
198 void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
\r
199 void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
\r
200 void* pfnUART2_Handler; /* 44 UART 2 */
\r
201 void* pfnUART3_Handler; /* 45 UART 3 */
\r
202 void* pfnUART4_Handler; /* 46 UART 4 */
\r
203 void* pfnTC6_Handler; /* 47 Timer/Counter 6 */
\r
204 void* pfnTC7_Handler; /* 48 Timer/Counter 7 */
\r
205 void* pfnTC8_Handler; /* 49 Timer/Counter 8 */
\r
206 void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
\r
207 void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
\r
208 void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
\r
209 void* pfnMLB_Handler;
\r
210 void* pvReserved54;
\r
211 void* pvReserved55;
\r
212 void* pfnAES_Handler; /* 56 AES */
\r
213 void* pfnTRNG_Handler; /* 57 True Random Generator */
\r
214 void* pfnXDMAC_Handler; /* 58 DMA */
\r
215 void* pfnISI_Handler; /* 59 Camera Interface */
\r
216 void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
\r
217 void* pfnFPU_Handler;
\r
218 void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */
\r
219 void* pfnWDT1_Handler; /* 63 Watchdog Timer 1 */
\r
220 void* pfnCCW_Handler; /* 64 ARM Cache ECC Warning */
\r
221 void* pfnCCF_Handler; /* 65 ARM Cache ECC Fault */
\r
222 void* pfnGMACQ1_Handler; /* 66 GMAC Queue 1 Handler */
\r
223 void* pfnGMACQ2_Handler; /* 67 GMAC Queue 2 Handler */
\r
226 /* Cortex-M4 core handlers */
\r
227 void Reset_Handler ( void );
\r
228 void NMI_Handler ( void );
\r
229 void HardFault_Handler ( void );
\r
230 void MemManage_Handler ( void );
\r
231 void BusFault_Handler ( void );
\r
232 void UsageFault_Handler ( void );
\r
233 void SVC_Handler ( void );
\r
234 void DebugMon_Handler ( void );
\r
235 void PendSV_Handler ( void );
\r
236 void SysTick_Handler ( void );
\r
238 /* Peripherals handlers */
\r
239 void ACC_Handler ( void );
\r
240 void AES_Handler ( void );
\r
241 void AFEC0_Handler ( void );
\r
242 void AFEC1_Handler ( void );
\r
243 void CAN0_Handler ( void );
\r
244 void CAN1_Handler ( void );
\r
245 void CCF_Handler ( void );
\r
246 void CCW_Handler ( void );
\r
247 void DACC_Handler ( void );
\r
248 void EFC_Handler ( void );
\r
249 void FPU_Handler ( void );
\r
250 void GMAC_Handler ( void );
\r
251 void GMACQ1_Handler ( void );
\r
252 void GMACQ2_Handler ( void );
\r
253 void HSMCI_Handler ( void );
\r
254 void ICM_Handler ( void );
\r
255 void ISI_Handler ( void );
\r
256 void MLB_Handler ( void );
\r
257 void PIOA_Handler ( void );
\r
258 void PIOB_Handler ( void );
\r
259 void PIOC_Handler ( void );
\r
260 void PIOD_Handler ( void );
\r
261 void PIOE_Handler ( void );
\r
262 void PMC_Handler ( void );
\r
263 void PWM0_Handler ( void );
\r
264 void PWM1_Handler ( void );
\r
265 void QSPI_Handler ( void );
\r
266 void RSTC_Handler ( void );
\r
267 void RTC_Handler ( void );
\r
268 void RTT_Handler ( void );
\r
269 void SDRAMC_Handler ( void );
\r
270 void SPI0_Handler ( void );
\r
271 void SPI1_Handler ( void );
\r
272 void SSC_Handler ( void );
\r
273 void SUPC_Handler ( void );
\r
274 void TC0_Handler ( void );
\r
275 void TC1_Handler ( void );
\r
276 void TC2_Handler ( void );
\r
277 void TC3_Handler ( void );
\r
278 void TC4_Handler ( void );
\r
279 void TC5_Handler ( void );
\r
280 void TC6_Handler ( void );
\r
281 void TC7_Handler ( void );
\r
282 void TC8_Handler ( void );
\r
283 void TC9_Handler ( void );
\r
284 void TC10_Handler ( void );
\r
285 void TC11_Handler ( void );
\r
286 void TRNG_Handler ( void );
\r
287 void TWI0_Handler ( void );
\r
288 void TWI1_Handler ( void );
\r
289 void TWI2_Handler ( void );
\r
290 void UART0_Handler ( void );
\r
291 void UART1_Handler ( void );
\r
292 void UART2_Handler ( void );
\r
293 void UART3_Handler ( void );
\r
294 void UART4_Handler ( void );
\r
295 void USART0_Handler ( void );
\r
296 void USART1_Handler ( void );
\r
297 void USART2_Handler ( void );
\r
298 void USBHS_Handler ( void );
\r
299 void WDT0_Handler ( void );
\r
300 void WDT1_Handler ( void );
\r
301 void XDMAC_Handler ( void );
\r
304 * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
\r
307 #define __CM4_REV 0x0000 /**< SAMV71Q21 core revision number ([15:8] revision number, [7:0] patch number) */
\r
308 #define __MPU_PRESENT 1 /**< SAMV71Q21 does provide a MPU */
\r
309 #define __FPU_PRESENT 1 /**< SAMV71Q21 does provide a FPU */
\r
310 #define __NVIC_PRIO_BITS 3 /**< SAMV71Q21 uses 3 Bits for the Priority Levels */
\r
311 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
\r
314 * \brief CMSIS includes
\r
317 #include <core_cm7.h>
\r
318 #if !defined DONT_USE_CMSIS_INIT
\r
319 #include "system_sam.h"
\r
320 #endif /* DONT_USE_CMSIS_INIT */
\r
324 /* ************************************************************************** */
\r
325 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q21 */
\r
326 /* ************************************************************************** */
\r
327 /** \addtogroup SAMV71Q21_api Peripheral Software API */
\r
330 #include "component/component_acc.h"
\r
331 #include "component/component_aes.h"
\r
332 #include "component/component_afec.h"
\r
333 #include "component/component_chipid.h"
\r
334 #include "component/component_dacc.h"
\r
335 #include "component/component_efc.h"
\r
336 #include "component/component_gmac.h"
\r
337 #include "component/component_gpbr.h"
\r
338 #include "component/component_hsmci.h"
\r
339 #include "component/component_icm.h"
\r
340 #include "component/component_isi.h"
\r
341 #include "component/component_matrix.h"
\r
342 #include "component/component_pio.h"
\r
343 #include "component/component_pmc.h"
\r
344 #include "component/component_pwm.h"
\r
345 #include "component/component_qspi.h"
\r
346 #include "component/component_rstc.h"
\r
347 #include "component/component_rtc.h"
\r
348 #include "component/component_rtt.h"
\r
349 #include "component/component_sdramc.h"
\r
350 #include "component/component_smc.h"
\r
351 #include "component/component_spi.h"
\r
352 #include "component/component_ssc.h"
\r
353 #include "component/component_supc.h"
\r
354 #include "component/component_tc.h"
\r
355 #include "component/component_trng.h"
\r
356 #include "component/component_twi.h"
\r
357 #include "component/component_twihs.h"
\r
358 #include "component/component_uart.h"
\r
359 #include "component/component_uotghs.h"
\r
360 #include "component/component_usart.h"
\r
361 #include "component/component_wdt.h"
\r
362 #include "component/component_xdmac.h"
\r
365 /* ************************************************************************** */
\r
366 /* REGISTER ACCESS DEFINITIONS FOR SAMV71Q21 */
\r
367 /* ************************************************************************** */
\r
368 /** \addtogroup SAMV71Q21_reg Registers Access Definitions */
\r
371 #include "instance/instance_hsmci.h"
\r
372 #include "instance/instance_ssc.h"
\r
373 #include "instance/instance_spi0.h"
\r
374 #include "instance/instance_tc0.h"
\r
375 #include "instance/instance_tc1.h"
\r
376 #include "instance/instance_tc2.h"
\r
377 #include "instance/instance_twi0.h"
\r
378 #include "instance/instance_twi1.h"
\r
379 #include "instance/instance_pwm0.h"
\r
380 #include "instance/instance_usart0.h"
\r
381 #include "instance/instance_usart1.h"
\r
382 #include "instance/instance_usart2.h"
\r
383 #include "instance/instance_usbhs.h"
\r
384 #include "instance/instance_afec0.h"
\r
385 #include "instance/instance_dacc.h"
\r
386 #include "instance/instance_acc.h"
\r
387 #include "instance/instance_icm.h"
\r
388 #include "instance/instance_isi.h"
\r
389 #include "instance/instance_gmac.h"
\r
390 #include "instance/instance_tc3.h"
\r
391 #include "instance/instance_spi1.h"
\r
392 #include "instance/instance_pwm1.h"
\r
393 #include "instance/instance_twi2.h"
\r
394 #include "instance/instance_afec1.h"
\r
395 #include "instance/instance_aes.h"
\r
396 #include "instance/instance_trng.h"
\r
397 #include "instance/instance_xdmac.h"
\r
398 #include "instance/instance_qspi.h"
\r
399 #include "instance/instance_smc.h"
\r
400 #include "instance/instance_sdramc.h"
\r
401 #include "instance/instance_matrix.h"
\r
402 #include "instance/instance_pmc.h"
\r
403 #include "instance/instance_uart0.h"
\r
404 #include "instance/instance_chipid.h"
\r
405 #include "instance/instance_uart1.h"
\r
406 #include "instance/instance_efc.h"
\r
407 #include "instance/instance_pioa.h"
\r
408 #include "instance/instance_piob.h"
\r
409 #include "instance/instance_pioc.h"
\r
410 #include "instance/instance_piod.h"
\r
411 #include "instance/instance_pioe.h"
\r
412 #include "instance/instance_rstc.h"
\r
413 #include "instance/instance_supc.h"
\r
414 #include "instance/instance_rtt.h"
\r
415 #include "instance/instance_wdt0.h"
\r
416 #include "instance/instance_rtc.h"
\r
417 #include "instance/instance_gpbr.h"
\r
418 #include "instance/instance_wdt1.h"
\r
419 #include "instance/instance_uart2.h"
\r
420 #include "instance/instance_uart3.h"
\r
421 #include "instance/instance_uart4.h"
\r
424 /* ************************************************************************** */
\r
425 /* PERIPHERAL ID DEFINITIONS FOR SAMV71Q21 */
\r
426 /* ************************************************************************** */
\r
427 /** \addtogroup SAMV71Q21_id Peripheral Ids Definitions */
\r
430 #define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
\r
431 #define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
\r
432 #define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
\r
433 #define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
\r
434 #define ID_WDT0 ( 4) /**< \brief Watchdog Timer 0 (WDT0) */
\r
435 #define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
\r
436 #define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
\r
437 #define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
\r
438 #define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
\r
439 #define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
\r
440 #define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
\r
441 #define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
\r
442 #define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */
\r
443 #define ID_USART0 (13) /**< \brief USART 0 (USART0) */
\r
444 #define ID_USART1 (14) /**< \brief USART 1 (USART1) */
\r
445 #define ID_USART2 (15) /**< \brief USART 2 (USART2) */
\r
446 #define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
\r
447 #define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */
\r
448 #define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
\r
449 #define ID_TWI0 (19) /**< \brief Two Wire Interface 0 HS (TWI0) */
\r
450 #define ID_TWI1 (20) /**< \brief Two Wire Interface 1 HS (TWI1) */
\r
451 #define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
\r
452 #define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
\r
453 #define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
\r
454 #define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
\r
455 #define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
\r
456 #define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
\r
457 #define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
\r
458 #define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
\r
459 #define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
\r
460 #define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
\r
461 #define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
\r
462 #define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
\r
463 #define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
\r
464 #define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
\r
465 #define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */
\r
466 #define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
\r
467 #define ID_TWI2 (41) /**< \brief Two Wire Interface 2 HS (TWI2) */
\r
468 #define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
\r
469 #define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
\r
470 #define ID_UART2 (44) /**< \brief UART 2 (UART2) */
\r
471 #define ID_UART3 (45) /**< \brief UART 3 (UART3) */
\r
472 #define ID_UART4 (46) /**< \brief UART 4 (UART4) */
\r
473 #define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */
\r
474 #define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */
\r
475 #define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */
\r
476 #define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
\r
477 #define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
\r
478 #define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
\r
479 #define ID_AES (56) /**< \brief AES (AES) */
\r
480 #define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
\r
481 #define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
\r
482 #define ID_ISI (59) /**< \brief Camera Interface (ISI) */
\r
483 #define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
\r
484 #define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */
\r
485 #define ID_WDT1 (63) /**< \brief Watchdog Timer 1 (WDT1) */
\r
486 #define ID_CCW (64) /**< \brief ARM cache ECC Warning(CCW) */
\r
487 #define ID_CCF (65) /**< \brief ARM cache ECC Fault (CCF) */
\r
489 #define ID_PERIPH_COUNT (66) /**< \brief Number of peripheral IDs */
\r
492 /* ************************************************************************** */
\r
493 /* BASE ADDRESS DEFINITIONS FOR SAMV71Q21 */
\r
494 /* ************************************************************************** */
\r
495 /** \addtogroup SAMV71Q21_base Peripheral Base Address Definitions */
\r
498 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
\r
499 #define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
\r
500 #define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
\r
501 #define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
\r
502 #define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
\r
503 #define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */
\r
504 #define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */
\r
505 #define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */
\r
506 #define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */
\r
507 #define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
\r
508 #define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
\r
509 #define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
\r
510 #define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
\r
511 #define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
\r
512 #define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
\r
513 #define DACC (0x40040000U) /**< \brief (DACC ) Base Address */
\r
514 #define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
\r
515 #define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
\r
516 #define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
\r
517 #define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */
\r
518 #define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
\r
519 #define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
\r
520 #define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
\r
521 #define TWI2 (0x40060000U) /**< \brief (TWI2 ) Base Address */
\r
522 #define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
\r
523 #define AES (0x4006C000U) /**< \brief (AES ) Base Address */
\r
524 #define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
\r
525 #define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
\r
526 #define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
\r
527 #define SMC (0x40080000U) /**< \brief (SMC ) Base Address */
\r
528 #define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */
\r
529 #define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
\r
530 #define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
\r
531 #define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
\r
532 #define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
\r
533 #define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
\r
534 #define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
\r
535 #define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
\r
536 #define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
\r
537 #define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */
\r
538 #define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
\r
539 #define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */
\r
540 #define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
\r
541 #define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
\r
542 #define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
\r
543 #define WDT0 (0x400E1850U) /**< \brief (WDT0 ) Base Address */
\r
544 #define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
\r
545 #define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
\r
546 #define WDT1 (0x400E1900U) /**< \brief (WDT1 ) Base Address */
\r
547 #define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
\r
548 #define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
\r
549 #define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
\r
551 #define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
\r
552 #define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
\r
553 #define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
\r
554 #define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
\r
555 #define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */
\r
556 #define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */
\r
557 #define TWI0 ((Twihs *)0x40018000U) /**< \brief (TWI0 ) Base Address */
\r
558 #define TWI1 ((Twihs *)0x4001C000U) /**< \brief (TWI1 ) Base Address */
\r
559 #define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
\r
560 #define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
\r
561 #define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
\r
562 #define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
\r
563 #define USBHS ((Uotghs *)0x40038000U) /**< \brief (USBHS ) Base Address */
\r
564 #define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
\r
565 #define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */
\r
566 #define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
\r
567 #define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
\r
568 #define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
\r
569 #define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */
\r
570 #define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
\r
571 #define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
\r
572 #define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
\r
573 #define TWI2 ((Twihs *)0x40060000U) /**< \brief (TWI2 ) Base Address */
\r
574 #define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
\r
575 #define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
\r
576 #define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
\r
577 #define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
\r
578 #define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
\r
579 #define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */
\r
580 #define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */
\r
581 #define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
\r
582 #define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
\r
583 #define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
\r
584 #define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
\r
585 #define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
\r
586 #define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
\r
587 #define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
\r
588 #define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
\r
589 #define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */
\r
590 #define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
\r
591 #define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */
\r
592 #define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
\r
593 #define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
\r
594 #define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
\r
595 #define WDT0 ((Wdt *)0x400E1850U) /**< \brief (WDT0 ) Base Address */
\r
596 #define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
\r
597 #define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
\r
598 #define WDT1 ((Wdt *)0x400E1900U) /**< \brief (WDT1 ) Base Address */
\r
599 #define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
\r
600 #define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
\r
601 #define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
\r
602 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
605 /* ************************************************************************** */
\r
606 /* PIO DEFINITIONS FOR SAMV71Q21 */
\r
607 /* ************************************************************************** */
\r
608 /** \addtogroup SAMV71Q21_pio Peripheral Pio Definitions */
\r
611 #include "pio/pio_samv71q21.h"
\r
614 /* ************************************************************************** */
\r
615 /* MEMORY MAPPING DEFINITIONS FOR SAMV71Q21 */
\r
616 /* ************************************************************************** */
\r
618 #define IFLASH_SIZE (0x200000u)
\r
619 #define IFLASH_PAGE_SIZE (512u)
\r
620 #define IFLASH_LOCK_REGION_SIZE (8192u)
\r
621 #define IFLASH_NB_OF_PAGES (4096u)
\r
622 #define IFLASH_NB_OF_LOCK_BITS (128u)
\r
623 #define IRAM_SIZE (0x60000u)
\r
625 #define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
\r
626 #define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
\r
627 #define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
\r
628 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
\r
629 #define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
\r
630 #define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
\r
631 #define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
\r
632 #define USBHS_RAM_ADDR (0xA0100000u) /**< USB On-The-Go Interface RAM base address */
\r
633 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
\r
634 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
\r
635 #define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
\r
636 #define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
\r
637 #define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
\r
639 /* ************************************************************************** */
\r
640 /* MISCELLANEOUS DEFINITIONS FOR SAMV71Q21 */
\r
641 /* ************************************************************************** */
\r
643 #define CHIP_JTAGID (0x05B3D03FUL)
\r
644 #define CHIP_CIDR (0xA1220E00UL)
\r
645 #define CHIP_EXID (0x00000002UL)
\r
647 /* ************************************************************************** */
\r
648 /* ELECTRICAL DEFINITIONS FOR SAMV71Q21 */
\r
649 /* ************************************************************************** */
\r
651 /* Device characteristics */
\r
652 #define CHIP_FREQ_SLCK_RC_MIN (20000UL)
\r
653 #define CHIP_FREQ_SLCK_RC (32000UL)
\r
654 #define CHIP_FREQ_SLCK_RC_MAX (44000UL)
\r
655 #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
\r
656 #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
\r
657 #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
\r
658 #define CHIP_FREQ_CPU_MAX (120000000UL)
\r
659 #define CHIP_FREQ_XTAL_32K (32768UL)
\r
660 #define CHIP_FREQ_XTAL_12M (12000000UL)
\r
662 /* Embedded Flash Write Wait State */
\r
663 #define CHIP_FLASH_WRITE_WAIT_STATE (6U)
\r
665 /* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
\r
666 #define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
\r
667 #define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
\r
668 #define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
\r
669 #define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
\r
670 #define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
\r
671 #define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
\r
679 #endif /* _SAMV71Q21_ */
\r