1 /* ----------------------------------------------------------------------------
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2 * SAM Software Package License
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2013, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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31 * \addtogroup uart_dma_module UART xDMA driver
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32 * \ingroup lib_uartflash
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36 * <li> UARTD_Configure() initializes and configures the UART peripheral and xDMA for data transfer.</li>
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37 * <li> Configures the parameters for the device corresponding to the cs value by UARTD_ConfigureCS(). </li>
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38 * <li> Starts a UART master transfer. This is a non blocking function UARTD_SendCommand(). It will
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39 * return as soon as the transfer is started..</li>
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47 * Implementation for the UART Flash with xDMA driver.
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52 /*----------------------------------------------------------------------------
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54 *----------------------------------------------------------------------------*/
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58 /*----------------------------------------------------------------------------
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60 *----------------------------------------------------------------------------*/
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63 /** xDMA Link List size for uart transation*/
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64 #define DMA_UART_LLI 2
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66 /*----------------------------------------------------------------------------
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68 *----------------------------------------------------------------------------*/
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70 /*----------------------------------------------------------------------------
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72 *----------------------------------------------------------------------------*/
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75 /*----------------------------------------------------------------------------
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77 *----------------------------------------------------------------------------*/
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81 * \brief UART xDMA Rx callback
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82 * Invoked on UART DMA reception done.
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83 * \param channel DMA channel.
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84 * \param pArg Pointer to callback argument - Pointer to UARTDma instance.
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86 static void UARTD_Rx_Cb(uint32_t channel, UartDma* pArg)
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89 UartChannel *pUartdCh = pArg->pRxChannel;
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90 if (channel != pUartdCh->ChNum)
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93 // NVIC_ClearPendingIRQ(XDMAC_IRQn);
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95 /* Release the DMA channels */
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96 XDMAD_FreeChannel(pArg->pXdmad, pUartdCh->ChNum);
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98 /* Invoke the callback associated with the current command */
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99 if (pUartdCh && pUartdCh->callback) {
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100 pUartdCh->callback(0, pUartdCh->pArgument);
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102 pUartdCh->sempaphore = 1;
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106 * \brief USART xDMA Rx callback
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107 * Invoked on USART DMA reception done.
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108 * \param channel DMA channel.
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109 * \param pArg Pointer to callback argument - Pointer to USARTDma instance.
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111 static void UARTD_Tx_Cb(uint32_t channel, UartDma* pArg)
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113 UartChannel *pUartdCh = pArg->pTxChannel;
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114 if (channel != pUartdCh->ChNum)
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117 // NVIC_ClearPendingIRQ(XDMAC_IRQn);
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119 /* Release the DMA channels */
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120 XDMAD_FreeChannel(pArg->pXdmad, pUartdCh->ChNum);
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122 /* Invoke the callback associated with the current command */
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123 if (pUartdCh && pUartdCh->callback) {
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124 pUartdCh->callback(0, pUartdCh->pArgument);
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126 pUartdCh->sempaphore = 1;
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131 * \brief Configure the UART Rx DMA Destination with Linker List mode.
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133 * \param UartChannel Pointer to UART dma channel
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134 * \returns 0 if the dma multibuffer configuration successfully; otherwise returns
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135 * USARTD_ERROR_XXX.
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137 static uint8_t _configureRxLinkList(Uart *pUartHw, void *pXdmad, UartChannel *pUartRx)
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139 sXdmadCfg xdmadRxCfg;
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142 if ((unsigned int)pUartHw == (unsigned int)UART0 ) uartId = ID_UART0;
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143 if ((unsigned int)pUartHw == (unsigned int)UART1 ) uartId = ID_UART1;
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144 if ((unsigned int)pUartHw == (unsigned int)UART2 ) uartId = ID_UART2;
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145 if ((unsigned int)pUartHw == (unsigned int)UART3 ) uartId = ID_UART3;
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146 if ((unsigned int)pUartHw == (unsigned int)UART4 ) uartId = ID_UART4;
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148 /* Setup RX Link List */
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149 xdmadRxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 |
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150 XDMA_UBC_NDE_FETCH_DIS|
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151 XDMA_UBC_NDEN_UPDATED |
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153 xdmadRxCfg.mbr_da = (uint32_t)pUartRx->pBuff;
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155 xdmadRxCfg.mbr_sa = (uint32_t)&pUartHw->UART_RHR;
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156 xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
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157 XDMAC_CC_MBSIZE_SINGLE |
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158 XDMAC_CC_DSYNC_PER2MEM |
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159 XDMAC_CC_CSIZE_CHK_1 |
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160 XDMAC_CC_DWIDTH_BYTE |
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161 XDMAC_CC_SIF_AHB_IF1 |
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162 XDMAC_CC_DIF_AHB_IF0 |
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163 XDMAC_CC_SAM_FIXED_AM |
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164 XDMAC_CC_DAM_INCREMENTED_AM |
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165 XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( uartId, XDMAD_TRANSFER_RX ));
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167 xdmadRxCfg.mbr_bc = 0;
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168 xdmadRxCfg.mbr_sus = 0;
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169 xdmadRxCfg.mbr_dus =0;
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171 if (XDMAD_ConfigureTransfer( pXdmad, pUartRx->ChNum, &xdmadRxCfg, xdmaCndc, 0))
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172 return USARTD_ERROR;
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179 * \brief Configure the UART tx DMA source with Linker List mode.
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181 * \param UartChannel Pointer to UART dma channel
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182 * \returns 0 if the dma multibuffer configuration successfully; otherwise returns
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183 * USARTD_ERROR_XXX.
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185 static uint8_t _configureTxLinkList(Uart *pUartHw, void *pXdmad, UartChannel *pUartTx)
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187 sXdmadCfg xdmadTxCfg;
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190 if ((unsigned int)pUartHw == (unsigned int)UART0 ) uartId = ID_UART0;
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191 if ((unsigned int)pUartHw == (unsigned int)UART1 ) uartId = ID_UART1;
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192 if ((unsigned int)pUartHw == (unsigned int)UART2 ) uartId = ID_UART2;
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193 if ((unsigned int)pUartHw == (unsigned int)UART3 ) uartId = ID_UART3;
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194 if ((unsigned int)pUartHw == (unsigned int)UART4 ) uartId = ID_UART4;
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196 /* Setup TX Link List */
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197 xdmadTxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 |
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198 XDMA_UBC_NDE_FETCH_DIS|
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199 XDMA_UBC_NSEN_UPDATED | pUartTx->BuffSize;
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201 xdmadTxCfg.mbr_sa = (uint32_t)pUartTx->pBuff;
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202 xdmadTxCfg.mbr_da = (uint32_t)&pUartHw->UART_THR;
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203 xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
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204 XDMAC_CC_MBSIZE_SINGLE |
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205 XDMAC_CC_DSYNC_MEM2PER |
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206 XDMAC_CC_CSIZE_CHK_1 |
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207 XDMAC_CC_DWIDTH_BYTE|
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208 XDMAC_CC_SIF_AHB_IF0 |
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209 XDMAC_CC_DIF_AHB_IF1 |
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210 XDMAC_CC_SAM_INCREMENTED_AM |
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211 XDMAC_CC_DAM_FIXED_AM |
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212 XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( uartId, XDMAD_TRANSFER_TX ));
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214 xdmadTxCfg.mbr_bc = 0;
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215 xdmadTxCfg.mbr_sus = 0;
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216 xdmadTxCfg.mbr_dus =0;
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219 if (XDMAD_ConfigureTransfer( pXdmad, pUartTx->ChNum, &xdmadTxCfg, xdmaCndc, 0))
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220 return USARTD_ERROR;
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224 /*----------------------------------------------------------------------------
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225 * Exported functions
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226 *----------------------------------------------------------------------------*/
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228 * \brief Initializes the UartDma structure and the corresponding UART & DMA hardware.
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230 * The driver will uses DMA channel 0 for RX and DMA channel 1 for TX.
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231 * The DMA channels are freed automatically when no UART command processing.
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233 * \param pUartd Pointer to a UartDma instance.
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234 * \param pUartHw Associated UART peripheral.
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235 * \param uartId UART peripheral identifier.
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236 * \param pXdmad Pointer to a Dmad instance.
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238 uint32_t UARTD_Configure( UartDma *pUartd ,
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244 /* Initialize the UART structure */
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245 pUartd->pUartHw = pUartHw;
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246 pUartd->uartId = uartId;
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247 pUartd->pTxChannel = 0;
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248 pUartd->pRxChannel = 0;
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249 pUartd->pXdmad = pXdmad;
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251 /* Enable the UART Peripheral ,Execute a software reset of the UART, Configure UART in Master Mode*/
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252 UART_Configure ( pUartHw, UartMode, 115200, BOARD_MCK);
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254 /* Driver initialize */
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255 XDMAD_Initialize( pUartd->pXdmad, 0 );
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256 /* Configure and enable interrupt on RC compare */
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257 NVIC_ClearPendingIRQ(XDMAC_IRQn);
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258 NVIC_SetPriority( XDMAC_IRQn ,1);
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264 * \brief Enables USART Rx DMA channel
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266 * The driver will uses DMA channel 0 for RX and DMA channel 1 for TX.
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267 * The DMA channels are freed automatically when no USART command processing.
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269 * \param pUSARTd Pointer to a UartDma instance.
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270 * \param pUartHw Associated USART peripheral.
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271 * \param uartId USART peripheral identifier.
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272 * \param UartClk USART clock.
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273 * \param pDmad Pointer to a Dmad instance.
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276 uint32_t UARTD_EnableRxChannels( UartDma *pUartd, UartChannel *pRxCh)
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278 Uart *pUartHw = pUartd->pUartHw;
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281 // Initialize the callback
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282 pUartd->pRxChannel = pRxCh;
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284 /* Enables the USART to receive data. */
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285 UART_SetReceiverEnabled ( pUartHw , 1);
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287 XDMAD_FreeChannel( pUartd->pXdmad, pRxCh->ChNum);
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289 /* Allocate a DMA channel for UART0/1 RX. */
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290 Channel = XDMAD_AllocateChannel( pUartd->pXdmad, pUartd->uartId, XDMAD_TRANSFER_MEMORY);
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291 if ( Channel == XDMAD_ALLOC_FAILED )
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293 return USARTD_ERROR;
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296 pRxCh->ChNum = Channel ;
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298 /* Setup callbacks for UART0/1 RX */
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299 XDMAD_SetCallback(pUartd->pXdmad, pRxCh->ChNum, (XdmadTransferCallback)UARTD_Rx_Cb, pUartd);
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300 if (XDMAD_PrepareChannel( pUartd->pXdmad, pRxCh->ChNum ))
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301 return USARTD_ERROR;
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303 /* Enable interrupt */
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304 NVIC_EnableIRQ(XDMAC_IRQn);
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306 if (_configureRxLinkList(pUartHw, pUartd->pXdmad, pRxCh))
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307 return USARTD_ERROR_LOCK;
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314 uint32_t UARTD_EnableTxChannels( UartDma *pUartd, UartChannel *pTxCh)
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316 Uart *pUartHw = pUartd->pUartHw;
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319 // Initialize the callback
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320 pUartd->pTxChannel = pTxCh;
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322 /* Enables the USART to transfer data. */
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323 UART_SetTransmitterEnabled ( pUartHw , 1);
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325 XDMAD_FreeChannel( pUartd->pXdmad, pTxCh->ChNum);
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327 /* Allocate a DMA channel for USART0/1 TX. */
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328 Channel = XDMAD_AllocateChannel( pUartd->pXdmad, XDMAD_TRANSFER_MEMORY, pUartd->uartId);
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329 if ( pTxCh->ChNum == XDMAD_ALLOC_FAILED )
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331 return USARTD_ERROR;
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334 pTxCh->ChNum = Channel ;
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336 /* Setup callbacks for USART0/1 TX */
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337 XDMAD_SetCallback(pUartd->pXdmad, pTxCh->ChNum, (XdmadTransferCallback)UARTD_Tx_Cb, pUartd);
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338 if ( XDMAD_PrepareChannel( pUartd->pXdmad, pTxCh->ChNum ))
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339 return USARTD_ERROR;
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341 /* Enable interrupt */
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342 NVIC_EnableIRQ(XDMAC_IRQn);
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344 if (_configureTxLinkList(pUartHw, pUartd->pXdmad, pTxCh))
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345 return USARTD_ERROR_LOCK;
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351 * \brief Starts a USART master transfer. This is a non blocking function. It will
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352 * return as soon as the transfer is started.
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354 * \param pUSARTd Pointer to a USARTDma instance.
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355 * \param pCommand Pointer to the USART command to execute.
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356 * \returns 0 if the transfer has been started successfully; otherwise returns
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357 * USARTD_ERROR_LOCK is the driver is in use, or USARTD_ERROR if the command is not
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360 uint32_t UARTD_SendData( UartDma *pUartd)
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363 /* Start DMA 0(RX) && 1(TX) */
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364 while(!pUartd->pTxChannel->sempaphore);
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365 if (XDMAD_StartTransfer( pUartd->pXdmad, pUartd->pTxChannel->ChNum ))
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366 return USARTD_ERROR_LOCK;
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367 pUartd->pTxChannel->sempaphore=0;
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372 * \brief Starts a USART master transfer. This is a non blocking function. It will
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373 * return as soon as the transfer is started.
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375 * \param pUSARTd Pointer to a USARTDma instance.
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376 * \param pCommand Pointer to the USART command to execute.
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377 * \returns 0 if the transfer has been started successfully; otherwise returns
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378 * USARTD_ERROR_LOCK is the driver is in use, or USARTD_ERROR if the command is not
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381 uint32_t UARTD_RcvData( UartDma *pUartd)
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384 while(!pUartd->pRxChannel->sempaphore);
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385 /* Start DMA 0(RX) && 1(TX) */
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386 if (XDMAD_StartTransfer( pUartd->pXdmad, pUartd->pRxChannel->ChNum ))
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387 return USARTD_ERROR_LOCK;
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388 pUartd->pRxChannel->sempaphore=0;
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