1 /**************************************************************************//**
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2 * @file core_cm0plus.h
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3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
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5 * @date 18. March 2015
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9 ******************************************************************************/
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10 /* Copyright (c) 2009 - 2015 ARM LIMITED
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12 All rights reserved.
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13 Redistribution and use in source and binary forms, with or without
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14 modification, are permitted provided that the following conditions are met:
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15 - Redistributions of source code must retain the above copyright
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16 notice, this list of conditions and the following disclaimer.
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17 - Redistributions in binary form must reproduce the above copyright
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18 notice, this list of conditions and the following disclaimer in the
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19 documentation and/or other materials provided with the distribution.
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20 - Neither the name of ARM nor the names of its contributors may be used
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21 to endorse or promote products derived from this software without
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22 specific prior written permission.
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24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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34 POSSIBILITY OF SUCH DAMAGE.
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35 ---------------------------------------------------------------------------*/
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38 #if defined ( __ICCARM__ )
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39 #pragma system_include /* treat file as system include file for MISRA check */
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42 #ifndef __CORE_CM0PLUS_H_GENERIC
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43 #define __CORE_CM0PLUS_H_GENERIC
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49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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50 CMSIS violates the following MISRA-C:2004 rules:
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52 \li Required Rule 8.5, object/function definition in header file.<br>
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53 Function definitions in header files are used to allow 'inlining'.
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55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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56 Unions are used for effective representation of core registers.
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58 \li Advisory Rule 19.7, Function-like macro defined.<br>
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59 Function-like macros are used to allow more efficient code.
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63 /*******************************************************************************
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65 ******************************************************************************/
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66 /** \ingroup Cortex-M0+
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70 /* CMSIS CM0P definitions */
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71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
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72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
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73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
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74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
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76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
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79 #if defined ( __CC_ARM )
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80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
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81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
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82 #define __STATIC_INLINE static __inline
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84 #elif defined ( __GNUC__ )
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85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
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86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
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87 #define __STATIC_INLINE static inline
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89 #elif defined ( __ICCARM__ )
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90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
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91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
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92 #define __STATIC_INLINE static inline
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94 #elif defined ( __TMS470__ )
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95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
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96 #define __STATIC_INLINE static inline
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98 #elif defined ( __TASKING__ )
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99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
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100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
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101 #define __STATIC_INLINE static inline
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103 #elif defined ( __CSMC__ )
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105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
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106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
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107 #define __STATIC_INLINE static inline
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111 /** __FPU_USED indicates whether an FPU is used or not.
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112 This core does not support an FPU at all
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114 #define __FPU_USED 0
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116 #if defined ( __CC_ARM )
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117 #if defined __TARGET_FPU_VFP
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118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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121 #elif defined ( __GNUC__ )
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122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
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123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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126 #elif defined ( __ICCARM__ )
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127 #if defined __ARMVFP__
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128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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131 #elif defined ( __TMS470__ )
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132 #if defined __TI__VFP_SUPPORT____
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133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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136 #elif defined ( __TASKING__ )
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137 #if defined __FPU_VFP__
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138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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141 #elif defined ( __CSMC__ ) /* Cosmic */
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142 #if ( __CSMC__ & 0x400) // FPU present for parser
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143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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147 #include <stdint.h> /* standard types definitions */
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148 #include <core_cmInstr.h> /* Core Instruction Access */
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149 #include <core_cmFunc.h> /* Core Function Access */
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155 #endif /* __CORE_CM0PLUS_H_GENERIC */
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157 #ifndef __CMSIS_GENERIC
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159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
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160 #define __CORE_CM0PLUS_H_DEPENDANT
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166 /* check device defines and use defaults */
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167 #if defined __CHECK_DEVICE_DEFINES
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168 #ifndef __CM0PLUS_REV
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169 #define __CM0PLUS_REV 0x0000
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170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
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173 #ifndef __MPU_PRESENT
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174 #define __MPU_PRESENT 0
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175 #warning "__MPU_PRESENT not defined in device header file; using default!"
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178 #ifndef __VTOR_PRESENT
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179 #define __VTOR_PRESENT 0
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180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
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183 #ifndef __NVIC_PRIO_BITS
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184 #define __NVIC_PRIO_BITS 2
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185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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188 #ifndef __Vendor_SysTickConfig
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189 #define __Vendor_SysTickConfig 0
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190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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194 /* IO definitions (access restrictions to peripheral registers) */
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196 \defgroup CMSIS_glob_defs CMSIS Global Defines
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198 <strong>IO Type Qualifiers</strong> are used
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199 \li to specify the access to peripheral variables.
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200 \li for automatic generation of peripheral register debug information.
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203 #define __I volatile /*!< Defines 'read only' permissions */
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205 #define __I volatile const /*!< Defines 'read only' permissions */
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207 #define __O volatile /*!< Defines 'write only' permissions */
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208 #define __IO volatile /*!< Defines 'read / write' permissions */
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210 /*@} end of group Cortex-M0+ */
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214 /*******************************************************************************
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215 * Register Abstraction
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216 Core Register contain:
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218 - Core NVIC Register
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219 - Core SCB Register
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220 - Core SysTick Register
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221 - Core MPU Register
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222 ******************************************************************************/
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223 /** \defgroup CMSIS_core_register Defines and Type Definitions
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224 \brief Type definitions and defines for Cortex-M processor based devices.
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227 /** \ingroup CMSIS_core_register
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228 \defgroup CMSIS_CORE Status and Control Registers
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229 \brief Core Register type definitions.
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233 /** \brief Union type to access the Application Program Status Register (APSR).
\r
239 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
\r
240 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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241 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
\r
242 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
\r
243 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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244 } b; /*!< Structure used for bit access */
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245 uint32_t w; /*!< Type used for word access */
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248 /* APSR Register Definitions */
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249 #define APSR_N_Pos 31 /*!< APSR: N Position */
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250 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
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252 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
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253 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
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255 #define APSR_C_Pos 29 /*!< APSR: C Position */
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256 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
\r
258 #define APSR_V_Pos 28 /*!< APSR: V Position */
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259 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
\r
262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
\r
268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
\r
269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
\r
270 } b; /*!< Structure used for bit access */
\r
271 uint32_t w; /*!< Type used for word access */
\r
274 /* IPSR Register Definitions */
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275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
\r
276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
\r
279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
\r
285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
\r
286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
\r
287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
\r
288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
\r
289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
\r
290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
\r
291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
\r
292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
\r
293 } b; /*!< Structure used for bit access */
\r
294 uint32_t w; /*!< Type used for word access */
\r
297 /* xPSR Register Definitions */
\r
298 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
\r
299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
\r
301 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
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302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
\r
304 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
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305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
\r
307 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
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308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
\r
310 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
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311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
\r
313 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
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314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
\r
317 /** \brief Union type to access the Control Registers (CONTROL).
\r
323 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
\r
324 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
\r
325 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
\r
326 } b; /*!< Structure used for bit access */
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327 uint32_t w; /*!< Type used for word access */
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330 /* CONTROL Register Definitions */
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331 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
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332 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
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334 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
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335 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
\r
337 /*@} end of group CMSIS_CORE */
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340 /** \ingroup CMSIS_core_register
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341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
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342 \brief Type definitions for the NVIC Registers
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346 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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350 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
\r
351 uint32_t RESERVED0[31];
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352 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
\r
353 uint32_t RSERVED1[31];
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354 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
\r
355 uint32_t RESERVED2[31];
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356 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
\r
357 uint32_t RESERVED3[31];
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358 uint32_t RESERVED4[64];
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359 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
\r
362 /*@} end of group CMSIS_NVIC */
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365 /** \ingroup CMSIS_core_register
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366 \defgroup CMSIS_SCB System Control Block (SCB)
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367 \brief Type definitions for the System Control Block Registers
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371 /** \brief Structure type to access the System Control Block (SCB).
\r
375 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
\r
376 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
\r
377 #if (__VTOR_PRESENT == 1)
\r
378 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
\r
380 uint32_t RESERVED0;
\r
382 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
\r
383 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
\r
384 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
\r
385 uint32_t RESERVED1;
\r
386 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
\r
387 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
\r
390 /* SCB CPUID Register Definitions */
\r
391 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
\r
392 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
\r
394 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
\r
395 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
\r
397 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
\r
398 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
\r
400 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
\r
401 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
\r
403 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
\r
404 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
\r
406 /* SCB Interrupt Control State Register Definitions */
\r
407 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
\r
408 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
\r
410 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
\r
411 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
\r
413 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
\r
414 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
\r
416 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
\r
417 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
\r
419 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
\r
420 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
\r
422 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
\r
423 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
\r
425 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
\r
426 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
\r
428 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
\r
429 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
\r
431 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
\r
432 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
\r
434 #if (__VTOR_PRESENT == 1)
\r
435 /* SCB Interrupt Control State Register Definitions */
\r
436 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
\r
437 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
\r
440 /* SCB Application Interrupt and Reset Control Register Definitions */
\r
441 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
\r
442 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
\r
444 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
\r
445 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
\r
447 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
\r
448 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
\r
450 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
\r
451 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
\r
453 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
\r
454 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
\r
456 /* SCB System Control Register Definitions */
\r
457 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
\r
458 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
\r
460 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
\r
461 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
\r
463 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
\r
464 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
\r
466 /* SCB Configuration Control Register Definitions */
\r
467 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
\r
468 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
\r
470 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
\r
471 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
\r
473 /* SCB System Handler Control and State Register Definitions */
\r
474 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
\r
475 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
\r
477 /*@} end of group CMSIS_SCB */
\r
480 /** \ingroup CMSIS_core_register
\r
481 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
\r
482 \brief Type definitions for the System Timer Registers.
\r
486 /** \brief Structure type to access the System Timer (SysTick).
\r
490 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
\r
491 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
\r
492 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
\r
493 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
\r
496 /* SysTick Control / Status Register Definitions */
\r
497 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
\r
498 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
\r
500 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
\r
501 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
\r
503 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
\r
504 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
\r
506 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
\r
507 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
\r
509 /* SysTick Reload Register Definitions */
\r
510 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
\r
511 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
\r
513 /* SysTick Current Register Definitions */
\r
514 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
\r
515 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
\r
517 /* SysTick Calibration Register Definitions */
\r
518 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
\r
519 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
\r
521 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
\r
522 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
\r
524 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
\r
525 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
\r
527 /*@} end of group CMSIS_SysTick */
\r
529 #if (__MPU_PRESENT == 1)
\r
530 /** \ingroup CMSIS_core_register
\r
531 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
\r
532 \brief Type definitions for the Memory Protection Unit (MPU)
\r
536 /** \brief Structure type to access the Memory Protection Unit (MPU).
\r
540 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
\r
541 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
\r
542 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
\r
543 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
\r
544 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
\r
547 /* MPU Type Register */
\r
548 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
\r
549 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
\r
551 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
\r
552 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
\r
554 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
\r
555 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
\r
557 /* MPU Control Register */
\r
558 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
\r
559 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
\r
561 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
\r
562 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
\r
564 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
\r
565 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
\r
567 /* MPU Region Number Register */
\r
568 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
\r
569 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
\r
571 /* MPU Region Base Address Register */
\r
572 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
\r
573 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
\r
575 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
\r
576 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
\r
578 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
\r
579 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
\r
581 /* MPU Region Attribute and Size Register */
\r
582 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
\r
583 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
\r
585 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
\r
586 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
\r
588 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
\r
589 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
\r
591 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
\r
592 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
\r
594 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
\r
595 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
\r
597 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
\r
598 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
\r
600 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
\r
601 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
\r
603 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
\r
604 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
\r
606 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
\r
607 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
\r
609 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
\r
610 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
\r
612 /*@} end of group CMSIS_MPU */
\r
616 /** \ingroup CMSIS_core_register
\r
617 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\r
618 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
\r
619 are only accessible over DAP and not via processor. Therefore
\r
620 they are not covered by the Cortex-M0 header file.
\r
623 /*@} end of group CMSIS_CoreDebug */
\r
626 /** \ingroup CMSIS_core_register
\r
627 \defgroup CMSIS_core_base Core Definitions
\r
628 \brief Definitions for base addresses, unions, and structures.
\r
632 /* Memory mapping of Cortex-M0+ Hardware */
\r
633 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
\r
634 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
\r
635 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
\r
636 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
\r
638 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
\r
639 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
\r
640 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
\r
642 #if (__MPU_PRESENT == 1)
\r
643 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
\r
644 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
\r
651 /*******************************************************************************
\r
652 * Hardware Abstraction Layer
\r
653 Core Function Interface contains:
\r
654 - Core NVIC Functions
\r
655 - Core SysTick Functions
\r
656 - Core Register Access Functions
\r
657 ******************************************************************************/
\r
658 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
\r
663 /* ########################## NVIC functions #################################### */
\r
664 /** \ingroup CMSIS_Core_FunctionInterface
\r
665 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
\r
666 \brief Functions that manage interrupts and exceptions via the NVIC.
\r
670 /* Interrupt Priorities are WORD accessible only under ARMv6M */
\r
671 /* The following MACROS handle generation of the register offset and byte masks */
\r
672 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
\r
673 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
\r
674 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
\r
677 /** \brief Enable External Interrupt
\r
679 The function enables a device-specific interrupt in the NVIC interrupt controller.
\r
681 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
683 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
\r
685 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
689 /** \brief Disable External Interrupt
\r
691 The function disables a device-specific interrupt in the NVIC interrupt controller.
\r
693 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
695 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\r
697 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
701 /** \brief Get Pending Interrupt
\r
703 The function reads the pending register in the NVIC and returns the pending bit
\r
704 for the specified interrupt.
\r
706 \param [in] IRQn Interrupt number.
\r
708 \return 0 Interrupt status is not pending.
\r
709 \return 1 Interrupt status is pending.
\r
711 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
\r
713 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
717 /** \brief Set Pending Interrupt
\r
719 The function sets the pending bit of an external interrupt.
\r
721 \param [in] IRQn Interrupt number. Value cannot be negative.
\r
723 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
\r
725 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
729 /** \brief Clear Pending Interrupt
\r
731 The function clears the pending bit of an external interrupt.
\r
733 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
735 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\r
737 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
741 /** \brief Set Interrupt Priority
\r
743 The function sets the priority of an interrupt.
\r
745 \note The priority cannot be set for every core interrupt.
\r
747 \param [in] IRQn Interrupt number.
\r
748 \param [in] priority Priority to set.
\r
750 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\r
752 if((int32_t)(IRQn) < 0) {
\r
753 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
\r
754 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
\r
757 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
\r
758 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
\r
763 /** \brief Get Interrupt Priority
\r
765 The function reads the priority of an interrupt. The interrupt
\r
766 number can be positive to specify an external (device specific)
\r
767 interrupt, or negative to specify an internal (core) interrupt.
\r
770 \param [in] IRQn Interrupt number.
\r
771 \return Interrupt Priority. Value is aligned automatically to the implemented
\r
772 priority bits of the microcontroller.
\r
774 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
\r
777 if((int32_t)(IRQn) < 0) {
\r
778 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
\r
781 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
\r
786 /** \brief System Reset
\r
788 The function initiates a system reset request to reset the MCU.
\r
790 __STATIC_INLINE void NVIC_SystemReset(void)
\r
792 __DSB(); /* Ensure all outstanding memory accesses included
\r
793 buffered write are completed before reset */
\r
794 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
\r
795 SCB_AIRCR_SYSRESETREQ_Msk);
\r
796 __DSB(); /* Ensure completion of memory access */
\r
797 while(1) { __NOP(); } /* wait until reset */
\r
800 /*@} end of CMSIS_Core_NVICFunctions */
\r
804 /* ################################## SysTick function ############################################ */
\r
805 /** \ingroup CMSIS_Core_FunctionInterface
\r
806 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\r
807 \brief Functions that configure the System.
\r
811 #if (__Vendor_SysTickConfig == 0)
\r
813 /** \brief System Tick Configuration
\r
815 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
\r
816 Counter is in free running mode to generate periodic interrupts.
\r
818 \param [in] ticks Number of ticks between two interrupts.
\r
820 \return 0 Function succeeded.
\r
821 \return 1 Function failed.
\r
823 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
\r
824 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
\r
825 must contain a vendor-specific implementation of this function.
\r
828 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
\r
830 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
\r
832 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
\r
833 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
\r
834 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
\r
835 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\r
836 SysTick_CTRL_TICKINT_Msk |
\r
837 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
\r
838 return (0UL); /* Function successful */
\r
843 /*@} end of CMSIS_Core_SysTickFunctions */
\r
852 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
\r
854 #endif /* __CMSIS_GENERIC */
\r