1 /**************************************************************************//**
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3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
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5 * @date 18. March 2015
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9 ******************************************************************************/
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10 /* Copyright (c) 2009 - 2015 ARM LIMITED
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12 All rights reserved.
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13 Redistribution and use in source and binary forms, with or without
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14 modification, are permitted provided that the following conditions are met:
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15 - Redistributions of source code must retain the above copyright
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16 notice, this list of conditions and the following disclaimer.
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17 - Redistributions in binary form must reproduce the above copyright
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18 notice, this list of conditions and the following disclaimer in the
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19 documentation and/or other materials provided with the distribution.
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20 - Neither the name of ARM nor the names of its contributors may be used
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21 to endorse or promote products derived from this software without
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22 specific prior written permission.
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24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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34 POSSIBILITY OF SUCH DAMAGE.
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35 ---------------------------------------------------------------------------*/
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38 #if defined ( __ICCARM__ )
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39 #pragma system_include /* treat file as system include file for MISRA check */
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42 #ifndef __CORE_CM4_H_GENERIC
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43 #define __CORE_CM4_H_GENERIC
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49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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50 CMSIS violates the following MISRA-C:2004 rules:
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52 \li Required Rule 8.5, object/function definition in header file.<br>
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53 Function definitions in header files are used to allow 'inlining'.
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55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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56 Unions are used for effective representation of core registers.
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58 \li Advisory Rule 19.7, Function-like macro defined.<br>
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59 Function-like macros are used to allow more efficient code.
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63 /*******************************************************************************
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65 ******************************************************************************/
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66 /** \ingroup Cortex_M4
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70 /* CMSIS CM4 definitions */
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71 #define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
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72 #define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
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73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
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74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
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76 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
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79 #if defined ( __CC_ARM )
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80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
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81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
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82 #define __STATIC_INLINE static __inline
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84 #elif defined ( __GNUC__ )
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85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
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86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
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87 #define __STATIC_INLINE static inline
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89 #elif defined ( __ICCARM__ )
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90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
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91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
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92 #define __STATIC_INLINE static inline
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94 #elif defined ( __TMS470__ )
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95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
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96 #define __STATIC_INLINE static inline
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98 #elif defined ( __TASKING__ )
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99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
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100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
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101 #define __STATIC_INLINE static inline
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103 #elif defined ( __CSMC__ )
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105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
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106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
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107 #define __STATIC_INLINE static inline
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111 /** __FPU_USED indicates whether an FPU is used or not.
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112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
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114 #if defined ( __CC_ARM )
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115 #if defined __TARGET_FPU_VFP
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116 #if (__FPU_PRESENT == 1)
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117 #define __FPU_USED 1
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119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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120 #define __FPU_USED 0
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123 #define __FPU_USED 0
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126 #elif defined ( __GNUC__ )
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127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
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128 #if (__FPU_PRESENT == 1)
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129 #define __FPU_USED 1
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131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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132 #define __FPU_USED 0
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135 #define __FPU_USED 0
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138 #elif defined ( __ICCARM__ )
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139 #if defined __ARMVFP__
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140 #if (__FPU_PRESENT == 1)
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141 #define __FPU_USED 1
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143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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144 #define __FPU_USED 0
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147 #define __FPU_USED 0
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150 #elif defined ( __TMS470__ )
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151 #if defined __TI_VFP_SUPPORT__
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152 #if (__FPU_PRESENT == 1)
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153 #define __FPU_USED 1
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155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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156 #define __FPU_USED 0
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159 #define __FPU_USED 0
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162 #elif defined ( __TASKING__ )
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163 #if defined __FPU_VFP__
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164 #if (__FPU_PRESENT == 1)
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165 #define __FPU_USED 1
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167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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168 #define __FPU_USED 0
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171 #define __FPU_USED 0
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174 #elif defined ( __CSMC__ ) /* Cosmic */
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175 #if ( __CSMC__ & 0x400) // FPU present for parser
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176 #if (__FPU_PRESENT == 1)
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177 #define __FPU_USED 1
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179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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180 #define __FPU_USED 0
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183 #define __FPU_USED 0
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187 #include <stdint.h> /* standard types definitions */
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188 #include <core_cmInstr.h> /* Core Instruction Access */
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189 #include <core_cmFunc.h> /* Core Function Access */
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190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
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196 #endif /* __CORE_CM4_H_GENERIC */
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198 #ifndef __CMSIS_GENERIC
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200 #ifndef __CORE_CM4_H_DEPENDANT
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201 #define __CORE_CM4_H_DEPENDANT
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207 /* check device defines and use defaults */
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208 #if defined __CHECK_DEVICE_DEFINES
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210 #define __CM4_REV 0x0000
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211 #warning "__CM4_REV not defined in device header file; using default!"
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214 #ifndef __FPU_PRESENT
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215 #define __FPU_PRESENT 0
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216 #warning "__FPU_PRESENT not defined in device header file; using default!"
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219 #ifndef __MPU_PRESENT
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220 #define __MPU_PRESENT 0
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221 #warning "__MPU_PRESENT not defined in device header file; using default!"
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224 #ifndef __NVIC_PRIO_BITS
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225 #define __NVIC_PRIO_BITS 4
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226 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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229 #ifndef __Vendor_SysTickConfig
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230 #define __Vendor_SysTickConfig 0
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231 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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235 /* IO definitions (access restrictions to peripheral registers) */
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237 \defgroup CMSIS_glob_defs CMSIS Global Defines
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239 <strong>IO Type Qualifiers</strong> are used
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240 \li to specify the access to peripheral variables.
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241 \li for automatic generation of peripheral register debug information.
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244 #define __I volatile /*!< Defines 'read only' permissions */
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246 #define __I volatile const /*!< Defines 'read only' permissions */
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248 #define __O volatile /*!< Defines 'write only' permissions */
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249 #define __IO volatile /*!< Defines 'read / write' permissions */
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251 /*@} end of group Cortex_M4 */
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255 /*******************************************************************************
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256 * Register Abstraction
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257 Core Register contain:
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259 - Core NVIC Register
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260 - Core SCB Register
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261 - Core SysTick Register
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262 - Core Debug Register
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263 - Core MPU Register
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264 - Core FPU Register
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265 ******************************************************************************/
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266 /** \defgroup CMSIS_core_register Defines and Type Definitions
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267 \brief Type definitions and defines for Cortex-M processor based devices.
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270 /** \ingroup CMSIS_core_register
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271 \defgroup CMSIS_CORE Status and Control Registers
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272 \brief Core Register type definitions.
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276 /** \brief Union type to access the Application Program Status Register (APSR).
\r
282 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
\r
283 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
\r
284 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
\r
285 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
\r
286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
\r
287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
\r
288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
\r
289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
\r
290 } b; /*!< Structure used for bit access */
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291 uint32_t w; /*!< Type used for word access */
\r
294 /* APSR Register Definitions */
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295 #define APSR_N_Pos 31 /*!< APSR: N Position */
\r
296 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
\r
298 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
\r
299 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
\r
301 #define APSR_C_Pos 29 /*!< APSR: C Position */
\r
302 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
\r
304 #define APSR_V_Pos 28 /*!< APSR: V Position */
\r
305 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
\r
307 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
\r
308 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
\r
310 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
\r
311 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
\r
314 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
\r
320 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
\r
321 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
\r
322 } b; /*!< Structure used for bit access */
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323 uint32_t w; /*!< Type used for word access */
\r
326 /* IPSR Register Definitions */
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327 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
\r
328 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
\r
331 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
\r
337 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
\r
338 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
\r
339 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
\r
340 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
\r
341 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
\r
342 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
\r
343 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
\r
344 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
\r
345 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
\r
346 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
\r
347 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
\r
348 } b; /*!< Structure used for bit access */
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349 uint32_t w; /*!< Type used for word access */
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352 /* xPSR Register Definitions */
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353 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
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354 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
\r
356 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
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357 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
\r
359 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
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360 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
\r
362 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
\r
363 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
\r
365 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
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366 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
\r
368 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
\r
369 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
\r
371 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
\r
372 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
\r
374 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
\r
375 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
\r
377 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
\r
378 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
\r
381 /** \brief Union type to access the Control Registers (CONTROL).
\r
387 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
\r
388 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
\r
389 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
\r
390 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
\r
391 } b; /*!< Structure used for bit access */
\r
392 uint32_t w; /*!< Type used for word access */
\r
395 /* CONTROL Register Definitions */
\r
396 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
\r
397 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
\r
399 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
\r
400 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
\r
402 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
\r
403 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
\r
405 /*@} end of group CMSIS_CORE */
\r
408 /** \ingroup CMSIS_core_register
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409 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
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410 \brief Type definitions for the NVIC Registers
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414 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
\r
418 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
\r
419 uint32_t RESERVED0[24];
\r
420 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
\r
421 uint32_t RSERVED1[24];
\r
422 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
\r
423 uint32_t RESERVED2[24];
\r
424 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
\r
425 uint32_t RESERVED3[24];
\r
426 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
\r
427 uint32_t RESERVED4[56];
\r
428 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
\r
429 uint32_t RESERVED5[644];
\r
430 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
\r
433 /* Software Triggered Interrupt Register Definitions */
\r
434 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
\r
435 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
\r
437 /*@} end of group CMSIS_NVIC */
\r
440 /** \ingroup CMSIS_core_register
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441 \defgroup CMSIS_SCB System Control Block (SCB)
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442 \brief Type definitions for the System Control Block Registers
\r
446 /** \brief Structure type to access the System Control Block (SCB).
\r
450 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
\r
451 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
\r
452 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
\r
453 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
\r
454 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
\r
455 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
\r
456 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
\r
457 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
\r
458 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
\r
459 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
\r
460 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
\r
461 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
\r
462 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
\r
463 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
\r
464 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
\r
465 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
\r
466 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
\r
467 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
\r
468 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
\r
469 uint32_t RESERVED0[5];
\r
470 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
\r
473 /* SCB CPUID Register Definitions */
\r
474 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
\r
475 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
\r
477 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
\r
478 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
\r
480 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
\r
481 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
\r
483 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
\r
484 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
\r
486 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
\r
487 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
\r
489 /* SCB Interrupt Control State Register Definitions */
\r
490 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
\r
491 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
\r
493 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
\r
494 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
\r
496 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
\r
497 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
\r
499 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
\r
500 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
\r
502 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
\r
503 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
\r
505 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
\r
506 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
\r
508 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
\r
509 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
\r
511 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
\r
512 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
\r
514 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
\r
515 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
\r
517 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
\r
518 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
\r
520 /* SCB Vector Table Offset Register Definitions */
\r
521 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
\r
522 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
\r
524 /* SCB Application Interrupt and Reset Control Register Definitions */
\r
525 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
\r
526 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
\r
528 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
\r
529 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
\r
531 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
\r
532 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
\r
534 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
\r
535 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
\r
537 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
\r
538 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
\r
540 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
\r
541 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
\r
543 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
\r
544 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
\r
546 /* SCB System Control Register Definitions */
\r
547 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
\r
548 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
\r
550 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
\r
551 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
\r
553 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
\r
554 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
\r
556 /* SCB Configuration Control Register Definitions */
\r
557 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
\r
558 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
\r
560 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
\r
561 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
\r
563 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
\r
564 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
\r
566 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
\r
567 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
\r
569 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
\r
570 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
\r
572 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
\r
573 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
\r
575 /* SCB System Handler Control and State Register Definitions */
\r
576 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
\r
577 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
\r
579 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
\r
580 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
\r
582 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
\r
583 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
\r
585 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
\r
586 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
\r
588 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
\r
589 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
\r
591 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
\r
592 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
\r
594 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
\r
595 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
\r
597 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
\r
598 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
\r
600 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
\r
601 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
\r
603 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
\r
604 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
\r
606 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
\r
607 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
\r
609 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
\r
610 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
\r
612 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
\r
613 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
\r
615 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
\r
616 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
\r
618 /* SCB Configurable Fault Status Registers Definitions */
\r
619 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
\r
620 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
\r
622 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
\r
623 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
\r
625 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
\r
626 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
\r
628 /* SCB Hard Fault Status Registers Definitions */
\r
629 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
\r
630 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
\r
632 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
\r
633 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
\r
635 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
\r
636 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
\r
638 /* SCB Debug Fault Status Register Definitions */
\r
639 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
\r
640 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
\r
642 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
\r
643 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
\r
645 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
\r
646 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
\r
648 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
\r
649 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
\r
651 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
\r
652 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
\r
654 /*@} end of group CMSIS_SCB */
\r
657 /** \ingroup CMSIS_core_register
\r
658 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\r
659 \brief Type definitions for the System Control and ID Register not in the SCB
\r
663 /** \brief Structure type to access the System Control and ID Register not in the SCB.
\r
667 uint32_t RESERVED0[1];
\r
668 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
\r
669 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
\r
672 /* Interrupt Controller Type Register Definitions */
\r
673 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
\r
674 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
\r
676 /* Auxiliary Control Register Definitions */
\r
677 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
\r
678 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
\r
680 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
\r
681 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
\r
683 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
\r
684 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
\r
686 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
\r
687 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
\r
689 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
\r
690 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
\r
692 /*@} end of group CMSIS_SCnotSCB */
\r
695 /** \ingroup CMSIS_core_register
\r
696 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
\r
697 \brief Type definitions for the System Timer Registers.
\r
701 /** \brief Structure type to access the System Timer (SysTick).
\r
705 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
\r
706 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
\r
707 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
\r
708 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
\r
711 /* SysTick Control / Status Register Definitions */
\r
712 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
\r
713 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
\r
715 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
\r
716 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
\r
718 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
\r
719 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
\r
721 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
\r
722 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
\r
724 /* SysTick Reload Register Definitions */
\r
725 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
\r
726 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
\r
728 /* SysTick Current Register Definitions */
\r
729 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
\r
730 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
\r
732 /* SysTick Calibration Register Definitions */
\r
733 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
\r
734 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
\r
736 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
\r
737 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
\r
739 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
\r
740 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
\r
742 /*@} end of group CMSIS_SysTick */
\r
745 /** \ingroup CMSIS_core_register
\r
746 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
\r
747 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
\r
751 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
\r
757 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
\r
758 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
\r
759 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
\r
760 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
\r
761 uint32_t RESERVED0[864];
\r
762 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
\r
763 uint32_t RESERVED1[15];
\r
764 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
\r
765 uint32_t RESERVED2[15];
\r
766 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
\r
767 uint32_t RESERVED3[29];
\r
768 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
\r
769 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
\r
770 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
\r
771 uint32_t RESERVED4[43];
\r
772 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
\r
773 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
\r
774 uint32_t RESERVED5[6];
\r
775 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
\r
776 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
\r
777 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
\r
778 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
\r
779 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
\r
780 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
\r
781 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
\r
782 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
\r
783 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
\r
784 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
\r
785 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
\r
786 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
\r
789 /* ITM Trace Privilege Register Definitions */
\r
790 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
\r
791 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
\r
793 /* ITM Trace Control Register Definitions */
\r
794 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
\r
795 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
\r
797 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
\r
798 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
\r
800 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
\r
801 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
\r
803 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
\r
804 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
\r
806 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
\r
807 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
\r
809 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
\r
810 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
\r
812 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
\r
813 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
\r
815 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
\r
816 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
\r
818 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
\r
819 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
\r
821 /* ITM Integration Write Register Definitions */
\r
822 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
\r
823 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
\r
825 /* ITM Integration Read Register Definitions */
\r
826 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
\r
827 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
\r
829 /* ITM Integration Mode Control Register Definitions */
\r
830 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
\r
831 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
\r
833 /* ITM Lock Status Register Definitions */
\r
834 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
\r
835 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
\r
837 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
\r
838 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
\r
840 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
\r
841 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
\r
843 /*@}*/ /* end of group CMSIS_ITM */
\r
846 /** \ingroup CMSIS_core_register
\r
847 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\r
848 \brief Type definitions for the Data Watchpoint and Trace (DWT)
\r
852 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
\r
856 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
\r
857 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
\r
858 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
\r
859 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
\r
860 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
\r
861 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
\r
862 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
\r
863 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
\r
864 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
\r
865 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
\r
866 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
\r
867 uint32_t RESERVED0[1];
\r
868 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
\r
869 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
\r
870 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
\r
871 uint32_t RESERVED1[1];
\r
872 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
\r
873 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
\r
874 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
\r
875 uint32_t RESERVED2[1];
\r
876 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
\r
877 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
\r
878 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
\r
881 /* DWT Control Register Definitions */
\r
882 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
\r
883 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
\r
885 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
\r
886 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
\r
888 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
\r
889 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
\r
891 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
\r
892 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
\r
894 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
\r
895 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
\r
897 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
\r
898 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
\r
900 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
\r
901 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
\r
903 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
\r
904 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
\r
906 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
\r
907 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
\r
909 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
\r
910 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
\r
912 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
\r
913 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
\r
915 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
\r
916 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
\r
918 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
\r
919 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
\r
921 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
\r
922 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
\r
924 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
\r
925 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
\r
927 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
\r
928 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
\r
930 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
\r
931 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
\r
933 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
\r
934 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
\r
936 /* DWT CPI Count Register Definitions */
\r
937 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
\r
938 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
\r
940 /* DWT Exception Overhead Count Register Definitions */
\r
941 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
\r
942 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
\r
944 /* DWT Sleep Count Register Definitions */
\r
945 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
\r
946 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
\r
948 /* DWT LSU Count Register Definitions */
\r
949 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
\r
950 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
\r
952 /* DWT Folded-instruction Count Register Definitions */
\r
953 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
\r
954 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
\r
956 /* DWT Comparator Mask Register Definitions */
\r
957 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
\r
958 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
\r
960 /* DWT Comparator Function Register Definitions */
\r
961 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
\r
962 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
\r
964 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
\r
965 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
\r
967 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
\r
968 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
\r
970 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
\r
971 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
\r
973 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
\r
974 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
\r
976 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
\r
977 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
\r
979 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
\r
980 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
\r
982 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
\r
983 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
\r
985 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
\r
986 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
\r
988 /*@}*/ /* end of group CMSIS_DWT */
\r
991 /** \ingroup CMSIS_core_register
\r
992 \defgroup CMSIS_TPI Trace Port Interface (TPI)
\r
993 \brief Type definitions for the Trace Port Interface (TPI)
\r
997 /** \brief Structure type to access the Trace Port Interface Register (TPI).
\r
1001 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
\r
1002 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
\r
1003 uint32_t RESERVED0[2];
\r
1004 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
\r
1005 uint32_t RESERVED1[55];
\r
1006 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
\r
1007 uint32_t RESERVED2[131];
\r
1008 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
\r
1009 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
\r
1010 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
\r
1011 uint32_t RESERVED3[759];
\r
1012 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
\r
1013 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
\r
1014 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
\r
1015 uint32_t RESERVED4[1];
\r
1016 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
\r
1017 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
\r
1018 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
\r
1019 uint32_t RESERVED5[39];
\r
1020 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
\r
1021 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
\r
1022 uint32_t RESERVED7[8];
\r
1023 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
\r
1024 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
\r
1027 /* TPI Asynchronous Clock Prescaler Register Definitions */
\r
1028 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
\r
1029 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
\r
1031 /* TPI Selected Pin Protocol Register Definitions */
\r
1032 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
\r
1033 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
\r
1035 /* TPI Formatter and Flush Status Register Definitions */
\r
1036 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
\r
1037 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
\r
1039 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
\r
1040 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
\r
1042 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
\r
1043 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
\r
1045 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
\r
1046 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
\r
1048 /* TPI Formatter and Flush Control Register Definitions */
\r
1049 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
\r
1050 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
\r
1052 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
\r
1053 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
\r
1055 /* TPI TRIGGER Register Definitions */
\r
1056 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
\r
1057 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
\r
1059 /* TPI Integration ETM Data Register Definitions (FIFO0) */
\r
1060 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
\r
1061 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
\r
1063 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
\r
1064 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
\r
1066 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
\r
1067 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
\r
1069 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
\r
1070 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
\r
1072 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
\r
1073 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
\r
1075 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
\r
1076 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
\r
1078 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
\r
1079 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
\r
1081 /* TPI ITATBCTR2 Register Definitions */
\r
1082 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
\r
1083 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
\r
1085 /* TPI Integration ITM Data Register Definitions (FIFO1) */
\r
1086 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
\r
1087 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
\r
1089 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
\r
1090 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
\r
1092 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
\r
1093 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
\r
1095 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
\r
1096 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
\r
1098 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
\r
1099 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
\r
1101 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
\r
1102 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
\r
1104 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
\r
1105 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
\r
1107 /* TPI ITATBCTR0 Register Definitions */
\r
1108 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
\r
1109 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
\r
1111 /* TPI Integration Mode Control Register Definitions */
\r
1112 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
\r
1113 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
\r
1115 /* TPI DEVID Register Definitions */
\r
1116 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
\r
1117 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
\r
1119 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
\r
1120 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
\r
1122 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
\r
1123 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
\r
1125 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
\r
1126 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
\r
1128 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
\r
1129 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
\r
1131 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
\r
1132 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
\r
1134 /* TPI DEVTYPE Register Definitions */
\r
1135 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
\r
1136 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
\r
1138 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
\r
1139 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
\r
1141 /*@}*/ /* end of group CMSIS_TPI */
\r
1144 #if (__MPU_PRESENT == 1)
\r
1145 /** \ingroup CMSIS_core_register
\r
1146 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
\r
1147 \brief Type definitions for the Memory Protection Unit (MPU)
\r
1151 /** \brief Structure type to access the Memory Protection Unit (MPU).
\r
1155 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
\r
1156 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
\r
1157 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
\r
1158 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
\r
1159 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
\r
1160 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
\r
1161 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
\r
1162 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
\r
1163 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
\r
1164 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
\r
1165 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
\r
1168 /* MPU Type Register */
\r
1169 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
\r
1170 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
\r
1172 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
\r
1173 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
\r
1175 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
\r
1176 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
\r
1178 /* MPU Control Register */
\r
1179 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
\r
1180 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
\r
1182 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
\r
1183 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
\r
1185 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
\r
1186 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
\r
1188 /* MPU Region Number Register */
\r
1189 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
\r
1190 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
\r
1192 /* MPU Region Base Address Register */
\r
1193 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
\r
1194 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
\r
1196 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
\r
1197 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
\r
1199 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
\r
1200 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
\r
1202 /* MPU Region Attribute and Size Register */
\r
1203 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
\r
1204 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
\r
1206 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
\r
1207 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
\r
1209 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
\r
1210 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
\r
1212 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
\r
1213 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
\r
1215 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
\r
1216 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
\r
1218 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
\r
1219 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
\r
1221 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
\r
1222 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
\r
1224 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
\r
1225 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
\r
1227 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
\r
1228 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
\r
1230 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
\r
1231 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
\r
1233 /*@} end of group CMSIS_MPU */
\r
1237 #if (__FPU_PRESENT == 1)
\r
1238 /** \ingroup CMSIS_core_register
\r
1239 \defgroup CMSIS_FPU Floating Point Unit (FPU)
\r
1240 \brief Type definitions for the Floating Point Unit (FPU)
\r
1244 /** \brief Structure type to access the Floating Point Unit (FPU).
\r
1248 uint32_t RESERVED0[1];
\r
1249 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
\r
1250 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
\r
1251 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
\r
1252 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
\r
1253 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
\r
1256 /* Floating-Point Context Control Register */
\r
1257 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
\r
1258 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
\r
1260 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
\r
1261 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
\r
1263 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
\r
1264 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
\r
1266 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
\r
1267 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
\r
1269 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
\r
1270 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
\r
1272 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
\r
1273 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
\r
1275 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
\r
1276 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
\r
1278 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
\r
1279 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
\r
1281 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
\r
1282 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
\r
1284 /* Floating-Point Context Address Register */
\r
1285 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
\r
1286 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
\r
1288 /* Floating-Point Default Status Control Register */
\r
1289 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
\r
1290 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
\r
1292 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
\r
1293 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
\r
1295 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
\r
1296 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
\r
1298 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
\r
1299 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
\r
1301 /* Media and FP Feature Register 0 */
\r
1302 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
\r
1303 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
\r
1305 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
\r
1306 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
\r
1308 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
\r
1309 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
\r
1311 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
\r
1312 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
\r
1314 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
\r
1315 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
\r
1317 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
\r
1318 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
\r
1320 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
\r
1321 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
\r
1323 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
\r
1324 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
\r
1326 /* Media and FP Feature Register 1 */
\r
1327 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
\r
1328 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
\r
1330 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
\r
1331 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
\r
1333 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
\r
1334 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
\r
1336 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
\r
1337 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
\r
1339 /*@} end of group CMSIS_FPU */
\r
1343 /** \ingroup CMSIS_core_register
\r
1344 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\r
1345 \brief Type definitions for the Core Debug Registers
\r
1349 /** \brief Structure type to access the Core Debug Register (CoreDebug).
\r
1353 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
\r
1354 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
\r
1355 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
\r
1356 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
\r
1359 /* Debug Halting Control and Status Register */
\r
1360 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
\r
1361 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
\r
1363 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
\r
1364 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
\r
1366 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
\r
1367 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
\r
1369 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
\r
1370 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
\r
1372 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
\r
1373 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
\r
1375 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
\r
1376 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
\r
1378 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
\r
1379 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
\r
1381 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
\r
1382 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
\r
1384 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
\r
1385 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
\r
1387 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
\r
1388 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
\r
1390 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
\r
1391 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
\r
1393 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
\r
1394 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
\r
1396 /* Debug Core Register Selector Register */
\r
1397 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
\r
1398 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
\r
1400 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
\r
1401 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
\r
1403 /* Debug Exception and Monitor Control Register */
\r
1404 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
\r
1405 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
\r
1407 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
\r
1408 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
\r
1410 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
\r
1411 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
\r
1413 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
\r
1414 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
\r
1416 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
\r
1417 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
\r
1419 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
\r
1420 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
\r
1422 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
\r
1423 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
\r
1425 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
\r
1426 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
\r
1428 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
\r
1429 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
\r
1431 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
\r
1432 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
\r
1434 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
\r
1435 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
\r
1437 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
\r
1438 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
\r
1440 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
\r
1441 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
\r
1443 /*@} end of group CMSIS_CoreDebug */
\r
1446 /** \ingroup CMSIS_core_register
\r
1447 \defgroup CMSIS_core_base Core Definitions
\r
1448 \brief Definitions for base addresses, unions, and structures.
\r
1452 /* Memory mapping of Cortex-M4 Hardware */
\r
1453 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
\r
1454 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
\r
1455 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
\r
1456 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
\r
1457 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
\r
1458 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
\r
1459 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
\r
1460 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
\r
1462 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
\r
1463 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
\r
1464 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
\r
1465 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
\r
1466 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
\r
1467 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
\r
1468 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
\r
1469 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
\r
1471 #if (__MPU_PRESENT == 1)
\r
1472 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
\r
1473 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
\r
1476 #if (__FPU_PRESENT == 1)
\r
1477 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
\r
1478 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
\r
1485 /*******************************************************************************
\r
1486 * Hardware Abstraction Layer
\r
1487 Core Function Interface contains:
\r
1488 - Core NVIC Functions
\r
1489 - Core SysTick Functions
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1490 - Core Debug Functions
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1491 - Core Register Access Functions
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1492 ******************************************************************************/
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1493 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
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1498 /* ########################## NVIC functions #################################### */
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1499 /** \ingroup CMSIS_Core_FunctionInterface
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1500 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
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1501 \brief Functions that manage interrupts and exceptions via the NVIC.
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1505 /** \brief Set Priority Grouping
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1507 The function sets the priority grouping field using the required unlock sequence.
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1508 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
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1509 Only values from 0..7 are used.
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1510 In case of a conflict between priority grouping and available
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1511 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
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1513 \param [in] PriorityGroup Priority grouping field.
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1515 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
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1517 uint32_t reg_value;
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1518 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
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1520 reg_value = SCB->AIRCR; /* read old register configuration */
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1521 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
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1522 reg_value = (reg_value |
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1523 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
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1524 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
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1525 SCB->AIRCR = reg_value;
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1529 /** \brief Get Priority Grouping
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1531 The function reads the priority grouping field from the NVIC Interrupt Controller.
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1533 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
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1535 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
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1537 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
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1541 /** \brief Enable External Interrupt
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1543 The function enables a device-specific interrupt in the NVIC interrupt controller.
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1545 \param [in] IRQn External interrupt number. Value cannot be negative.
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1547 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
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1549 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
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1553 /** \brief Disable External Interrupt
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1555 The function disables a device-specific interrupt in the NVIC interrupt controller.
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1557 \param [in] IRQn External interrupt number. Value cannot be negative.
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1559 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
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1561 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
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1565 /** \brief Get Pending Interrupt
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1567 The function reads the pending register in the NVIC and returns the pending bit
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1568 for the specified interrupt.
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1570 \param [in] IRQn Interrupt number.
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1572 \return 0 Interrupt status is not pending.
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1573 \return 1 Interrupt status is pending.
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1575 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
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1577 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
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1581 /** \brief Set Pending Interrupt
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1583 The function sets the pending bit of an external interrupt.
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1585 \param [in] IRQn Interrupt number. Value cannot be negative.
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1587 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
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1589 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
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1593 /** \brief Clear Pending Interrupt
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1595 The function clears the pending bit of an external interrupt.
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1597 \param [in] IRQn External interrupt number. Value cannot be negative.
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1599 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
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1601 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
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1605 /** \brief Get Active Interrupt
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1607 The function reads the active register in NVIC and returns the active bit.
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1609 \param [in] IRQn Interrupt number.
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1611 \return 0 Interrupt status is not active.
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1612 \return 1 Interrupt status is active.
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1614 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
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1616 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
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1620 /** \brief Set Interrupt Priority
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1622 The function sets the priority of an interrupt.
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1624 \note The priority cannot be set for every core interrupt.
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1626 \param [in] IRQn Interrupt number.
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1627 \param [in] priority Priority to set.
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1629 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
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1631 if((int32_t)IRQn < 0) {
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1632 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
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1635 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
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1640 /** \brief Get Interrupt Priority
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1642 The function reads the priority of an interrupt. The interrupt
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1643 number can be positive to specify an external (device specific)
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1644 interrupt, or negative to specify an internal (core) interrupt.
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1647 \param [in] IRQn Interrupt number.
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1648 \return Interrupt Priority. Value is aligned automatically to the implemented
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1649 priority bits of the microcontroller.
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1651 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
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1654 if((int32_t)IRQn < 0) {
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1655 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
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1658 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
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1663 /** \brief Encode Priority
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1665 The function encodes the priority for an interrupt with the given priority group,
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1666 preemptive priority value, and subpriority value.
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1667 In case of a conflict between priority grouping and available
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1668 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
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1670 \param [in] PriorityGroup Used priority group.
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1671 \param [in] PreemptPriority Preemptive priority value (starting from 0).
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1672 \param [in] SubPriority Subpriority value (starting from 0).
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1673 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
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1675 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
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1677 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
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1678 uint32_t PreemptPriorityBits;
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1679 uint32_t SubPriorityBits;
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1681 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
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1682 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
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1685 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
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1686 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
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1691 /** \brief Decode Priority
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1693 The function decodes an interrupt priority value with a given priority group to
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1694 preemptive priority value and subpriority value.
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1695 In case of a conflict between priority grouping and available
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1696 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
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1698 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
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1699 \param [in] PriorityGroup Used priority group.
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1700 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
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1701 \param [out] pSubPriority Subpriority value (starting from 0).
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1703 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
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1705 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
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1706 uint32_t PreemptPriorityBits;
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1707 uint32_t SubPriorityBits;
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1709 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
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1710 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
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1712 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
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1713 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
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1717 /** \brief System Reset
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1719 The function initiates a system reset request to reset the MCU.
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1721 __STATIC_INLINE void NVIC_SystemReset(void)
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1723 __DSB(); /* Ensure all outstanding memory accesses included
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1724 buffered write are completed before reset */
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1725 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
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1726 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
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1727 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
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1728 __DSB(); /* Ensure completion of memory access */
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1729 while(1) { __NOP(); } /* wait until reset */
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1732 /*@} end of CMSIS_Core_NVICFunctions */
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1736 /* ################################## SysTick function ############################################ */
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1737 /** \ingroup CMSIS_Core_FunctionInterface
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1738 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
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1739 \brief Functions that configure the System.
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1743 #if (__Vendor_SysTickConfig == 0)
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1745 /** \brief System Tick Configuration
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1747 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
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1748 Counter is in free running mode to generate periodic interrupts.
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1750 \param [in] ticks Number of ticks between two interrupts.
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1752 \return 0 Function succeeded.
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1753 \return 1 Function failed.
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1755 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
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1756 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
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1757 must contain a vendor-specific implementation of this function.
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1760 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
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1762 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
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1764 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
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1765 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
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1766 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
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1767 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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1768 SysTick_CTRL_TICKINT_Msk |
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1769 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
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1770 return (0UL); /* Function successful */
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1775 /*@} end of CMSIS_Core_SysTickFunctions */
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1779 /* ##################################### Debug In/Output function ########################################### */
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1780 /** \ingroup CMSIS_Core_FunctionInterface
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1781 \defgroup CMSIS_core_DebugFunctions ITM Functions
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1782 \brief Functions that access the ITM debug interface.
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1786 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
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1787 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
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1790 /** \brief ITM Send Character
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1792 The function transmits a character via the ITM channel 0, and
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1793 \li Just returns when no debugger is connected that has booked the output.
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1794 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
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1796 \param [in] ch Character to transmit.
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1798 \returns Character to transmit.
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1800 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
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1802 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
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1803 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
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1805 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
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1806 ITM->PORT[0].u8 = (uint8_t)ch;
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1812 /** \brief ITM Receive Character
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1814 The function inputs a character via the external variable \ref ITM_RxBuffer.
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1816 \return Received character.
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1817 \return -1 No character pending.
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1819 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
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1820 int32_t ch = -1; /* no character available */
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1822 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
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1823 ch = ITM_RxBuffer;
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1824 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
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1831 /** \brief ITM Check Character
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1833 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
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1835 \return 0 No character available.
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1836 \return 1 Character available.
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1838 __STATIC_INLINE int32_t ITM_CheckChar (void) {
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1840 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
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1841 return (0); /* no character available */
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1843 return (1); /* character available */
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1847 /*@} end of CMSIS_core_DebugFunctions */
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1852 #ifdef __cplusplus
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1856 #endif /* __CORE_CM4_H_DEPENDANT */
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1858 #endif /* __CMSIS_GENERIC */
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