1 /**************************************************************************//**
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3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
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5 * @date 18. March 2015
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9 ******************************************************************************/
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10 /* Copyright (c) 2009 - 2015 ARM LIMITED
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12 All rights reserved.
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13 Redistribution and use in source and binary forms, with or without
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14 modification, are permitted provided that the following conditions are met:
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15 - Redistributions of source code must retain the above copyright
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16 notice, this list of conditions and the following disclaimer.
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17 - Redistributions in binary form must reproduce the above copyright
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18 notice, this list of conditions and the following disclaimer in the
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19 documentation and/or other materials provided with the distribution.
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20 - Neither the name of ARM nor the names of its contributors may be used
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21 to endorse or promote products derived from this software without
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22 specific prior written permission.
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24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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34 POSSIBILITY OF SUCH DAMAGE.
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35 ---------------------------------------------------------------------------*/
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38 #if defined ( __ICCARM__ )
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39 #pragma system_include /* treat file as system include file for MISRA check */
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42 #ifndef __CORE_CM7_H_GENERIC
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43 #define __CORE_CM7_H_GENERIC
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49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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50 CMSIS violates the following MISRA-C:2004 rules:
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52 \li Required Rule 8.5, object/function definition in header file.<br>
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53 Function definitions in header files are used to allow 'inlining'.
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55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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56 Unions are used for effective representation of core registers.
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58 \li Advisory Rule 19.7, Function-like macro defined.<br>
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59 Function-like macros are used to allow more efficient code.
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63 /*******************************************************************************
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65 ******************************************************************************/
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66 /** \ingroup Cortex_M7
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70 /* CMSIS CM7 definitions */
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71 #define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
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72 #define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
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73 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
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74 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
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76 #define __CORTEX_M (0x07) /*!< Cortex-M Core */
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79 #if defined ( __CC_ARM )
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80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
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81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
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82 #define __STATIC_INLINE static __inline
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84 #elif defined ( __GNUC__ )
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85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
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86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
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87 #define __STATIC_INLINE static inline
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89 #elif defined ( __ICCARM__ )
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90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
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91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
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92 #define __STATIC_INLINE static inline
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94 #elif defined ( __TMS470__ )
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95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
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96 #define __STATIC_INLINE static inline
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98 #elif defined ( __TASKING__ )
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99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
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100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
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101 #define __STATIC_INLINE static inline
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103 #elif defined ( __CSMC__ )
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105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
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106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
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107 #define __STATIC_INLINE static inline
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111 /** __FPU_USED indicates whether an FPU is used or not.
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112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
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114 #if defined ( __CC_ARM )
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115 #if defined __TARGET_FPU_VFP
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116 #if (__FPU_PRESENT == 1)
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117 #define __FPU_USED 1
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119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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120 #define __FPU_USED 0
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123 #define __FPU_USED 0
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126 #elif defined ( __GNUC__ )
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127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
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128 #if (__FPU_PRESENT == 1)
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129 #define __FPU_USED 1
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131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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132 #define __FPU_USED 0
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135 #define __FPU_USED 0
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138 #elif defined ( __ICCARM__ )
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139 #if defined __ARMVFP__
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140 #if (__FPU_PRESENT == 1)
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141 #define __FPU_USED 1
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143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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144 #define __FPU_USED 0
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147 #define __FPU_USED 0
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150 #elif defined ( __TMS470__ )
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151 #if defined __TI_VFP_SUPPORT__
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152 #if (__FPU_PRESENT == 1)
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153 #define __FPU_USED 1
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155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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156 #define __FPU_USED 0
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159 #define __FPU_USED 0
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162 #elif defined ( __TASKING__ )
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163 #if defined __FPU_VFP__
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164 #if (__FPU_PRESENT == 1)
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165 #define __FPU_USED 1
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167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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168 #define __FPU_USED 0
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171 #define __FPU_USED 0
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174 #elif defined ( __CSMC__ ) /* Cosmic */
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175 #if ( __CSMC__ & 0x400) // FPU present for parser
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176 #if (__FPU_PRESENT == 1)
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177 #define __FPU_USED 1
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179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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180 #define __FPU_USED 0
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183 #define __FPU_USED 0
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187 #include <stdint.h> /* standard types definitions */
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188 #include <core_cmInstr.h> /* Core Instruction Access */
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189 #include <core_cmFunc.h> /* Core Function Access */
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190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
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196 #endif /* __CORE_CM7_H_GENERIC */
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198 #ifndef __CMSIS_GENERIC
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200 #ifndef __CORE_CM7_H_DEPENDANT
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201 #define __CORE_CM7_H_DEPENDANT
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207 /* check device defines and use defaults */
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208 #if defined __CHECK_DEVICE_DEFINES
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210 #define __CM7_REV 0x0000
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211 #warning "__CM7_REV not defined in device header file; using default!"
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214 #ifndef __FPU_PRESENT
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215 #define __FPU_PRESENT 0
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216 #warning "__FPU_PRESENT not defined in device header file; using default!"
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219 #ifndef __MPU_PRESENT
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220 #define __MPU_PRESENT 0
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221 #warning "__MPU_PRESENT not defined in device header file; using default!"
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224 #ifndef __ICACHE_PRESENT
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225 #define __ICACHE_PRESENT 0
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226 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
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229 #ifndef __DCACHE_PRESENT
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230 #define __DCACHE_PRESENT 0
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231 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
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234 #ifndef __DTCM_PRESENT
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235 #define __DTCM_PRESENT 0
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236 #warning "__DTCM_PRESENT not defined in device header file; using default!"
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239 #ifndef __NVIC_PRIO_BITS
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240 #define __NVIC_PRIO_BITS 3
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241 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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244 #ifndef __Vendor_SysTickConfig
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245 #define __Vendor_SysTickConfig 0
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246 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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250 /* IO definitions (access restrictions to peripheral registers) */
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252 \defgroup CMSIS_glob_defs CMSIS Global Defines
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254 <strong>IO Type Qualifiers</strong> are used
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255 \li to specify the access to peripheral variables.
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256 \li for automatic generation of peripheral register debug information.
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259 #define __I volatile /*!< Defines 'read only' permissions */
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261 #define __I volatile const /*!< Defines 'read only' permissions */
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263 #define __O volatile /*!< Defines 'write only' permissions */
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264 #define __IO volatile /*!< Defines 'read / write' permissions */
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266 /*@} end of group Cortex_M7 */
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270 /*******************************************************************************
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271 * Register Abstraction
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272 Core Register contain:
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274 - Core NVIC Register
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275 - Core SCB Register
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276 - Core SysTick Register
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277 - Core Debug Register
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278 - Core MPU Register
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279 - Core FPU Register
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280 ******************************************************************************/
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281 /** \defgroup CMSIS_core_register Defines and Type Definitions
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282 \brief Type definitions and defines for Cortex-M processor based devices.
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285 /** \ingroup CMSIS_core_register
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286 \defgroup CMSIS_CORE Status and Control Registers
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287 \brief Core Register type definitions.
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291 /** \brief Union type to access the Application Program Status Register (APSR).
\r
297 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
\r
298 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
\r
299 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
\r
300 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
\r
301 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
\r
302 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
\r
303 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
\r
304 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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305 } b; /*!< Structure used for bit access */
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306 uint32_t w; /*!< Type used for word access */
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309 /* APSR Register Definitions */
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310 #define APSR_N_Pos 31 /*!< APSR: N Position */
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311 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
\r
313 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
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314 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
\r
316 #define APSR_C_Pos 29 /*!< APSR: C Position */
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317 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
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319 #define APSR_V_Pos 28 /*!< APSR: V Position */
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320 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
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322 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
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323 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
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325 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
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326 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
\r
329 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
\r
335 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
\r
336 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
\r
337 } b; /*!< Structure used for bit access */
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338 uint32_t w; /*!< Type used for word access */
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341 /* IPSR Register Definitions */
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342 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
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343 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
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346 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
\r
352 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
\r
353 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
\r
354 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
\r
355 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
\r
356 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
\r
357 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
\r
358 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
\r
359 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
\r
360 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
\r
361 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
\r
362 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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363 } b; /*!< Structure used for bit access */
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364 uint32_t w; /*!< Type used for word access */
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367 /* xPSR Register Definitions */
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368 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
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369 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
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371 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
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372 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
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374 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
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375 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
\r
377 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
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378 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
\r
380 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
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381 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
\r
383 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
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384 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
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386 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
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387 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
\r
389 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
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390 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
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392 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
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393 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
\r
396 /** \brief Union type to access the Control Registers (CONTROL).
\r
402 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
\r
403 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
\r
404 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
\r
405 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
\r
406 } b; /*!< Structure used for bit access */
\r
407 uint32_t w; /*!< Type used for word access */
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410 /* CONTROL Register Definitions */
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411 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
\r
412 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
\r
414 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
\r
415 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
\r
417 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
\r
418 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
\r
420 /*@} end of group CMSIS_CORE */
\r
423 /** \ingroup CMSIS_core_register
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424 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
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425 \brief Type definitions for the NVIC Registers
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429 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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433 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
\r
434 uint32_t RESERVED0[24];
\r
435 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
\r
436 uint32_t RSERVED1[24];
\r
437 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
\r
438 uint32_t RESERVED2[24];
\r
439 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
\r
440 uint32_t RESERVED3[24];
\r
441 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
\r
442 uint32_t RESERVED4[56];
\r
443 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
\r
444 uint32_t RESERVED5[644];
\r
445 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
\r
448 /* Software Triggered Interrupt Register Definitions */
\r
449 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
\r
450 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
\r
452 /*@} end of group CMSIS_NVIC */
\r
455 /** \ingroup CMSIS_core_register
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456 \defgroup CMSIS_SCB System Control Block (SCB)
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457 \brief Type definitions for the System Control Block Registers
\r
461 /** \brief Structure type to access the System Control Block (SCB).
\r
465 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
\r
466 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
\r
467 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
\r
468 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
\r
469 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
\r
470 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
\r
471 __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
\r
472 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
\r
473 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
\r
474 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
\r
475 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
\r
476 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
\r
477 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
\r
478 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
\r
479 __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
\r
480 __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
\r
481 __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
\r
482 __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
\r
483 __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
\r
484 uint32_t RESERVED0[1];
\r
485 __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
\r
486 __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
\r
487 __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
\r
488 __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
\r
489 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
\r
490 uint32_t RESERVED3[93];
\r
491 __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
\r
492 uint32_t RESERVED4[15];
\r
493 __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
\r
494 __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
\r
495 __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
\r
496 uint32_t RESERVED5[1];
\r
497 __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
\r
498 uint32_t RESERVED6[1];
\r
499 __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
\r
500 __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
\r
501 __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
\r
502 __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
\r
503 __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
\r
504 __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
\r
505 __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
\r
506 __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
\r
507 uint32_t RESERVED7[6];
\r
508 __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
\r
509 __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
\r
510 __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
\r
511 __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
\r
512 __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
\r
513 uint32_t RESERVED8[1];
\r
514 __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
\r
517 /* SCB CPUID Register Definitions */
\r
518 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
\r
519 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
\r
521 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
\r
522 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
\r
524 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
\r
525 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
\r
527 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
\r
528 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
\r
530 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
\r
531 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
\r
533 /* SCB Interrupt Control State Register Definitions */
\r
534 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
\r
535 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
\r
537 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
\r
538 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
\r
540 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
\r
541 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
\r
543 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
\r
544 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
\r
546 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
\r
547 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
\r
549 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
\r
550 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
\r
552 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
\r
553 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
\r
555 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
\r
556 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
\r
558 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
\r
559 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
\r
561 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
\r
562 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
\r
564 /* SCB Vector Table Offset Register Definitions */
\r
565 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
\r
566 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
\r
568 /* SCB Application Interrupt and Reset Control Register Definitions */
\r
569 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
\r
570 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
\r
572 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
\r
573 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
\r
575 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
\r
576 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
\r
578 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
\r
579 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
\r
581 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
\r
582 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
\r
584 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
\r
585 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
\r
587 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
\r
588 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
\r
590 /* SCB System Control Register Definitions */
\r
591 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
\r
592 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
\r
594 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
\r
595 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
\r
597 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
\r
598 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
\r
600 /* SCB Configuration Control Register Definitions */
\r
601 #define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */
\r
602 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
\r
604 #define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */
\r
605 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
\r
607 #define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */
\r
608 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
\r
610 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
\r
611 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
\r
613 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
\r
614 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
\r
616 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
\r
617 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
\r
619 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
\r
620 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
\r
622 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
\r
623 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
\r
625 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
\r
626 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
\r
628 /* SCB System Handler Control and State Register Definitions */
\r
629 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
\r
630 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
\r
632 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
\r
633 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
\r
635 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
\r
636 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
\r
638 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
\r
639 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
\r
641 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
\r
642 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
\r
644 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
\r
645 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
\r
647 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
\r
648 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
\r
650 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
\r
651 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
\r
653 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
\r
654 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
\r
656 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
\r
657 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
\r
659 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
\r
660 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
\r
662 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
\r
663 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
\r
665 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
\r
666 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
\r
668 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
\r
669 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
\r
671 /* SCB Configurable Fault Status Registers Definitions */
\r
672 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
\r
673 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
\r
675 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
\r
676 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
\r
678 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
\r
679 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
\r
681 /* SCB Hard Fault Status Registers Definitions */
\r
682 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
\r
683 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
\r
685 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
\r
686 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
\r
688 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
\r
689 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
\r
691 /* SCB Debug Fault Status Register Definitions */
\r
692 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
\r
693 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
\r
695 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
\r
696 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
\r
698 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
\r
699 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
\r
701 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
\r
702 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
\r
704 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
\r
705 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
\r
707 /* Cache Level ID register */
\r
708 #define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */
\r
709 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
\r
711 #define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */
\r
712 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */
\r
714 /* Cache Type register */
\r
715 #define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */
\r
716 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
\r
718 #define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */
\r
719 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
\r
721 #define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */
\r
722 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
\r
724 #define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */
\r
725 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
\r
727 #define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */
\r
728 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
\r
730 /* Cache Size ID Register */
\r
731 #define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */
\r
732 #define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
\r
734 #define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */
\r
735 #define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
\r
737 #define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */
\r
738 #define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
\r
740 #define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */
\r
741 #define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
\r
743 #define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */
\r
744 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
\r
746 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */
\r
747 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
\r
749 #define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */
\r
750 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
\r
752 /* Cache Size Selection Register */
\r
753 #define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */
\r
754 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
\r
756 #define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */
\r
757 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
\r
759 /* SCB Software Triggered Interrupt Register */
\r
760 #define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */
\r
761 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
\r
763 /* Instruction Tightly-Coupled Memory Control Register*/
\r
764 #define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */
\r
765 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
\r
767 #define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */
\r
768 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
\r
770 #define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */
\r
771 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
\r
773 #define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */
\r
774 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
\r
776 /* Data Tightly-Coupled Memory Control Registers */
\r
777 #define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */
\r
778 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
\r
780 #define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */
\r
781 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
\r
783 #define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */
\r
784 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
\r
786 #define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */
\r
787 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
\r
789 /* AHBP Control Register */
\r
790 #define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */
\r
791 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
\r
793 #define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */
\r
794 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
\r
796 /* L1 Cache Control Register */
\r
797 #define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */
\r
798 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
\r
800 #define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */
\r
801 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
\r
803 #define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */
\r
804 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
\r
806 /* AHBS control register */
\r
807 #define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */
\r
808 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
\r
810 #define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */
\r
811 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
\r
813 #define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/
\r
814 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
\r
816 /* Auxiliary Bus Fault Status Register */
\r
817 #define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/
\r
818 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
\r
820 #define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/
\r
821 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
\r
823 #define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/
\r
824 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
\r
826 #define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/
\r
827 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
\r
829 #define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/
\r
830 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
\r
832 #define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/
\r
833 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
\r
835 /*@} end of group CMSIS_SCB */
\r
838 /** \ingroup CMSIS_core_register
\r
839 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\r
840 \brief Type definitions for the System Control and ID Register not in the SCB
\r
844 /** \brief Structure type to access the System Control and ID Register not in the SCB.
\r
848 uint32_t RESERVED0[1];
\r
849 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
\r
850 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
\r
853 /* Interrupt Controller Type Register Definitions */
\r
854 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
\r
855 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
\r
857 /* Auxiliary Control Register Definitions */
\r
858 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */
\r
859 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
\r
861 #define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */
\r
862 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
\r
864 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */
\r
865 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
\r
867 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
\r
868 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
\r
870 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
\r
871 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
\r
873 /*@} end of group CMSIS_SCnotSCB */
\r
876 /** \ingroup CMSIS_core_register
\r
877 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
\r
878 \brief Type definitions for the System Timer Registers.
\r
882 /** \brief Structure type to access the System Timer (SysTick).
\r
886 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
\r
887 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
\r
888 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
\r
889 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
\r
892 /* SysTick Control / Status Register Definitions */
\r
893 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
\r
894 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
\r
896 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
\r
897 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
\r
899 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
\r
900 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
\r
902 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
\r
903 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
\r
905 /* SysTick Reload Register Definitions */
\r
906 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
\r
907 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
\r
909 /* SysTick Current Register Definitions */
\r
910 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
\r
911 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
\r
913 /* SysTick Calibration Register Definitions */
\r
914 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
\r
915 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
\r
917 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
\r
918 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
\r
920 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
\r
921 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
\r
923 /*@} end of group CMSIS_SysTick */
\r
926 /** \ingroup CMSIS_core_register
\r
927 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
\r
928 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
\r
932 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
\r
938 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
\r
939 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
\r
940 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
\r
941 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
\r
942 uint32_t RESERVED0[864];
\r
943 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
\r
944 uint32_t RESERVED1[15];
\r
945 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
\r
946 uint32_t RESERVED2[15];
\r
947 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
\r
948 uint32_t RESERVED3[29];
\r
949 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
\r
950 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
\r
951 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
\r
952 uint32_t RESERVED4[43];
\r
953 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
\r
954 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
\r
955 uint32_t RESERVED5[6];
\r
956 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
\r
957 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
\r
958 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
\r
959 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
\r
960 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
\r
961 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
\r
962 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
\r
963 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
\r
964 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
\r
965 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
\r
966 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
\r
967 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
\r
970 /* ITM Trace Privilege Register Definitions */
\r
971 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
\r
972 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
\r
974 /* ITM Trace Control Register Definitions */
\r
975 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
\r
976 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
\r
978 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
\r
979 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
\r
981 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
\r
982 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
\r
984 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
\r
985 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
\r
987 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
\r
988 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
\r
990 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
\r
991 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
\r
993 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
\r
994 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
\r
996 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
\r
997 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
\r
999 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
\r
1000 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
\r
1002 /* ITM Integration Write Register Definitions */
\r
1003 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
\r
1004 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
\r
1006 /* ITM Integration Read Register Definitions */
\r
1007 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
\r
1008 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
\r
1010 /* ITM Integration Mode Control Register Definitions */
\r
1011 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
\r
1012 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
\r
1014 /* ITM Lock Status Register Definitions */
\r
1015 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
\r
1016 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
\r
1018 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
\r
1019 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
\r
1021 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
\r
1022 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
\r
1024 /*@}*/ /* end of group CMSIS_ITM */
\r
1027 /** \ingroup CMSIS_core_register
\r
1028 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\r
1029 \brief Type definitions for the Data Watchpoint and Trace (DWT)
\r
1033 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
\r
1037 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
\r
1038 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
\r
1039 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
\r
1040 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
\r
1041 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
\r
1042 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
\r
1043 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
\r
1044 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
\r
1045 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
\r
1046 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
\r
1047 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
\r
1048 uint32_t RESERVED0[1];
\r
1049 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
\r
1050 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
\r
1051 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
\r
1052 uint32_t RESERVED1[1];
\r
1053 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
\r
1054 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
\r
1055 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
\r
1056 uint32_t RESERVED2[1];
\r
1057 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
\r
1058 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
\r
1059 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
\r
1060 uint32_t RESERVED3[981];
\r
1061 __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
\r
1062 __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
\r
1065 /* DWT Control Register Definitions */
\r
1066 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
\r
1067 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
\r
1069 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
\r
1070 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
\r
1072 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
\r
1073 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
\r
1075 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
\r
1076 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
\r
1078 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
\r
1079 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
\r
1081 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
\r
1082 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
\r
1084 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
\r
1085 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
\r
1087 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
\r
1088 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
\r
1090 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
\r
1091 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
\r
1093 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
\r
1094 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
\r
1096 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
\r
1097 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
\r
1099 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
\r
1100 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
\r
1102 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
\r
1103 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
\r
1105 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
\r
1106 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
\r
1108 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
\r
1109 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
\r
1111 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
\r
1112 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
\r
1114 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
\r
1115 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
\r
1117 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
\r
1118 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
\r
1120 /* DWT CPI Count Register Definitions */
\r
1121 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
\r
1122 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
\r
1124 /* DWT Exception Overhead Count Register Definitions */
\r
1125 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
\r
1126 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
\r
1128 /* DWT Sleep Count Register Definitions */
\r
1129 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
\r
1130 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
\r
1132 /* DWT LSU Count Register Definitions */
\r
1133 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
\r
1134 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
\r
1136 /* DWT Folded-instruction Count Register Definitions */
\r
1137 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
\r
1138 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
\r
1140 /* DWT Comparator Mask Register Definitions */
\r
1141 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
\r
1142 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
\r
1144 /* DWT Comparator Function Register Definitions */
\r
1145 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
\r
1146 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
\r
1148 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
\r
1149 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
\r
1151 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
\r
1152 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
\r
1154 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
\r
1155 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
\r
1157 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
\r
1158 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
\r
1160 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
\r
1161 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
\r
1163 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
\r
1164 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
\r
1166 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
\r
1167 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
\r
1169 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
\r
1170 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
\r
1172 /*@}*/ /* end of group CMSIS_DWT */
\r
1175 /** \ingroup CMSIS_core_register
\r
1176 \defgroup CMSIS_TPI Trace Port Interface (TPI)
\r
1177 \brief Type definitions for the Trace Port Interface (TPI)
\r
1181 /** \brief Structure type to access the Trace Port Interface Register (TPI).
\r
1185 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
\r
1186 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
\r
1187 uint32_t RESERVED0[2];
\r
1188 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
\r
1189 uint32_t RESERVED1[55];
\r
1190 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
\r
1191 uint32_t RESERVED2[131];
\r
1192 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
\r
1193 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
\r
1194 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
\r
1195 uint32_t RESERVED3[759];
\r
1196 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
\r
1197 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
\r
1198 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
\r
1199 uint32_t RESERVED4[1];
\r
1200 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
\r
1201 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
\r
1202 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
\r
1203 uint32_t RESERVED5[39];
\r
1204 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
\r
1205 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
\r
1206 uint32_t RESERVED7[8];
\r
1207 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
\r
1208 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
\r
1211 /* TPI Asynchronous Clock Prescaler Register Definitions */
\r
1212 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
\r
1213 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
\r
1215 /* TPI Selected Pin Protocol Register Definitions */
\r
1216 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
\r
1217 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
\r
1219 /* TPI Formatter and Flush Status Register Definitions */
\r
1220 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
\r
1221 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
\r
1223 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
\r
1224 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
\r
1226 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
\r
1227 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
\r
1229 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
\r
1230 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
\r
1232 /* TPI Formatter and Flush Control Register Definitions */
\r
1233 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
\r
1234 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
\r
1236 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
\r
1237 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
\r
1239 /* TPI TRIGGER Register Definitions */
\r
1240 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
\r
1241 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
\r
1243 /* TPI Integration ETM Data Register Definitions (FIFO0) */
\r
1244 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
\r
1245 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
\r
1247 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
\r
1248 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
\r
1250 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
\r
1251 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
\r
1253 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
\r
1254 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
\r
1256 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
\r
1257 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
\r
1259 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
\r
1260 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
\r
1262 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
\r
1263 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
\r
1265 /* TPI ITATBCTR2 Register Definitions */
\r
1266 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
\r
1267 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
\r
1269 /* TPI Integration ITM Data Register Definitions (FIFO1) */
\r
1270 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
\r
1271 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
\r
1273 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
\r
1274 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
\r
1276 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
\r
1277 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
\r
1279 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
\r
1280 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
\r
1282 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
\r
1283 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
\r
1285 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
\r
1286 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
\r
1288 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
\r
1289 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
\r
1291 /* TPI ITATBCTR0 Register Definitions */
\r
1292 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
\r
1293 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
\r
1295 /* TPI Integration Mode Control Register Definitions */
\r
1296 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
\r
1297 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
\r
1299 /* TPI DEVID Register Definitions */
\r
1300 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
\r
1301 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
\r
1303 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
\r
1304 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
\r
1306 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
\r
1307 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
\r
1309 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
\r
1310 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
\r
1312 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
\r
1313 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
\r
1315 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
\r
1316 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
\r
1318 /* TPI DEVTYPE Register Definitions */
\r
1319 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
\r
1320 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
\r
1322 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
\r
1323 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
\r
1325 /*@}*/ /* end of group CMSIS_TPI */
\r
1328 #if (__MPU_PRESENT == 1)
\r
1329 /** \ingroup CMSIS_core_register
\r
1330 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
\r
1331 \brief Type definitions for the Memory Protection Unit (MPU)
\r
1335 /** \brief Structure type to access the Memory Protection Unit (MPU).
\r
1339 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
\r
1340 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
\r
1341 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
\r
1342 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
\r
1343 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
\r
1344 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
\r
1345 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
\r
1346 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
\r
1347 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
\r
1348 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
\r
1349 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
\r
1352 /* MPU Type Register */
\r
1353 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
\r
1354 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
\r
1356 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
\r
1357 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
\r
1359 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
\r
1360 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
\r
1362 /* MPU Control Register */
\r
1363 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
\r
1364 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
\r
1366 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
\r
1367 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
\r
1369 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
\r
1370 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
\r
1372 /* MPU Region Number Register */
\r
1373 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
\r
1374 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
\r
1376 /* MPU Region Base Address Register */
\r
1377 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
\r
1378 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
\r
1380 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
\r
1381 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
\r
1383 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
\r
1384 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
\r
1386 /* MPU Region Attribute and Size Register */
\r
1387 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
\r
1388 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
\r
1390 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
\r
1391 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
\r
1393 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
\r
1394 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
\r
1396 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
\r
1397 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
\r
1399 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
\r
1400 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
\r
1402 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
\r
1403 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
\r
1405 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
\r
1406 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
\r
1408 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
\r
1409 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
\r
1411 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
\r
1412 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
\r
1414 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
\r
1415 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
\r
1417 /*@} end of group CMSIS_MPU */
\r
1421 #if (__FPU_PRESENT == 1)
\r
1422 /** \ingroup CMSIS_core_register
\r
1423 \defgroup CMSIS_FPU Floating Point Unit (FPU)
\r
1424 \brief Type definitions for the Floating Point Unit (FPU)
\r
1428 /** \brief Structure type to access the Floating Point Unit (FPU).
\r
1432 uint32_t RESERVED0[1];
\r
1433 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
\r
1434 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
\r
1435 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
\r
1436 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
\r
1437 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
\r
1438 __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
\r
1441 /* Floating-Point Context Control Register */
\r
1442 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
\r
1443 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
\r
1445 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
\r
1446 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
\r
1448 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
\r
1449 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
\r
1451 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
\r
1452 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
\r
1454 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
\r
1455 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
\r
1457 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
\r
1458 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
\r
1460 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
\r
1461 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
\r
1463 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
\r
1464 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
\r
1466 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
\r
1467 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
\r
1469 /* Floating-Point Context Address Register */
\r
1470 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
\r
1471 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
\r
1473 /* Floating-Point Default Status Control Register */
\r
1474 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
\r
1475 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
\r
1477 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
\r
1478 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
\r
1480 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
\r
1481 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
\r
1483 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
\r
1484 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
\r
1486 /* Media and FP Feature Register 0 */
\r
1487 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
\r
1488 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
\r
1490 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
\r
1491 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
\r
1493 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
\r
1494 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
\r
1496 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
\r
1497 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
\r
1499 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
\r
1500 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
\r
1502 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
\r
1503 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
\r
1505 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
\r
1506 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
\r
1508 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
\r
1509 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
\r
1511 /* Media and FP Feature Register 1 */
\r
1512 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
\r
1513 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
\r
1515 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
\r
1516 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
\r
1518 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
\r
1519 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
\r
1521 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
\r
1522 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
\r
1524 /* Media and FP Feature Register 2 */
\r
1526 /*@} end of group CMSIS_FPU */
\r
1530 /** \ingroup CMSIS_core_register
\r
1531 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\r
1532 \brief Type definitions for the Core Debug Registers
\r
1536 /** \brief Structure type to access the Core Debug Register (CoreDebug).
\r
1540 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
\r
1541 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
\r
1542 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
\r
1543 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
\r
1546 /* Debug Halting Control and Status Register */
\r
1547 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
\r
1548 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
\r
1550 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
\r
1551 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
\r
1553 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
\r
1554 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
\r
1556 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
\r
1557 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
\r
1559 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
\r
1560 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
\r
1562 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
\r
1563 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
\r
1565 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
\r
1566 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
\r
1568 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
\r
1569 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
\r
1571 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
\r
1572 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
\r
1574 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
\r
1575 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
\r
1577 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
\r
1578 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
\r
1580 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
\r
1581 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
\r
1583 /* Debug Core Register Selector Register */
\r
1584 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
\r
1585 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
\r
1587 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
\r
1588 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
\r
1590 /* Debug Exception and Monitor Control Register */
\r
1591 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
\r
1592 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
\r
1594 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
\r
1595 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
\r
1597 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
\r
1598 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
\r
1600 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
\r
1601 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
\r
1603 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
\r
1604 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
\r
1606 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
\r
1607 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
\r
1609 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
\r
1610 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
\r
1612 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
\r
1613 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
\r
1615 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
\r
1616 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
\r
1618 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
\r
1619 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
\r
1621 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
\r
1622 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
\r
1624 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
\r
1625 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
\r
1627 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
\r
1628 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
\r
1630 /*@} end of group CMSIS_CoreDebug */
\r
1633 /** \ingroup CMSIS_core_register
\r
1634 \defgroup CMSIS_core_base Core Definitions
\r
1635 \brief Definitions for base addresses, unions, and structures.
\r
1639 /* Memory mapping of Cortex-M4 Hardware */
\r
1640 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
\r
1641 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
\r
1642 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
\r
1643 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
\r
1644 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
\r
1645 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
\r
1646 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
\r
1647 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
\r
1649 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
\r
1650 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
\r
1651 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
\r
1652 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
\r
1653 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
\r
1654 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
\r
1655 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
\r
1656 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
\r
1658 #if (__MPU_PRESENT == 1)
\r
1659 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
\r
1660 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
\r
1663 #if (__FPU_PRESENT == 1)
\r
1664 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
\r
1665 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
\r
1672 /*******************************************************************************
\r
1673 * Hardware Abstraction Layer
\r
1674 Core Function Interface contains:
\r
1675 - Core NVIC Functions
\r
1676 - Core SysTick Functions
\r
1677 - Core Debug Functions
\r
1678 - Core Register Access Functions
\r
1679 ******************************************************************************/
\r
1680 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
\r
1685 /* ########################## NVIC functions #################################### */
\r
1686 /** \ingroup CMSIS_Core_FunctionInterface
\r
1687 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
\r
1688 \brief Functions that manage interrupts and exceptions via the NVIC.
\r
1692 /** \brief Set Priority Grouping
\r
1694 The function sets the priority grouping field using the required unlock sequence.
\r
1695 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
\r
1696 Only values from 0..7 are used.
\r
1697 In case of a conflict between priority grouping and available
\r
1698 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\r
1700 \param [in] PriorityGroup Priority grouping field.
\r
1702 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
\r
1704 uint32_t reg_value;
\r
1705 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
\r
1707 reg_value = SCB->AIRCR; /* read old register configuration */
\r
1708 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
\r
1709 reg_value = (reg_value |
\r
1710 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
\r
1711 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
\r
1712 SCB->AIRCR = reg_value;
\r
1716 /** \brief Get Priority Grouping
\r
1718 The function reads the priority grouping field from the NVIC Interrupt Controller.
\r
1720 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
\r
1722 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
\r
1724 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
\r
1728 /** \brief Enable External Interrupt
\r
1730 The function enables a device-specific interrupt in the NVIC interrupt controller.
\r
1732 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
1734 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
\r
1736 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
1740 /** \brief Disable External Interrupt
\r
1742 The function disables a device-specific interrupt in the NVIC interrupt controller.
\r
1744 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
1746 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\r
1748 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
1752 /** \brief Get Pending Interrupt
\r
1754 The function reads the pending register in the NVIC and returns the pending bit
\r
1755 for the specified interrupt.
\r
1757 \param [in] IRQn Interrupt number.
\r
1759 \return 0 Interrupt status is not pending.
\r
1760 \return 1 Interrupt status is pending.
\r
1762 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
\r
1764 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1768 /** \brief Set Pending Interrupt
\r
1770 The function sets the pending bit of an external interrupt.
\r
1772 \param [in] IRQn Interrupt number. Value cannot be negative.
\r
1774 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
\r
1776 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
1780 /** \brief Clear Pending Interrupt
\r
1782 The function clears the pending bit of an external interrupt.
\r
1784 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
1786 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\r
1788 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
1792 /** \brief Get Active Interrupt
\r
1794 The function reads the active register in NVIC and returns the active bit.
\r
1796 \param [in] IRQn Interrupt number.
\r
1798 \return 0 Interrupt status is not active.
\r
1799 \return 1 Interrupt status is active.
\r
1801 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
\r
1803 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1807 /** \brief Set Interrupt Priority
\r
1809 The function sets the priority of an interrupt.
\r
1811 \note The priority cannot be set for every core interrupt.
\r
1813 \param [in] IRQn Interrupt number.
\r
1814 \param [in] priority Priority to set.
\r
1816 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\r
1818 if((int32_t)IRQn < 0) {
\r
1819 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
\r
1822 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
\r
1827 /** \brief Get Interrupt Priority
\r
1829 The function reads the priority of an interrupt. The interrupt
\r
1830 number can be positive to specify an external (device specific)
\r
1831 interrupt, or negative to specify an internal (core) interrupt.
\r
1834 \param [in] IRQn Interrupt number.
\r
1835 \return Interrupt Priority. Value is aligned automatically to the implemented
\r
1836 priority bits of the microcontroller.
\r
1838 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
\r
1841 if((int32_t)IRQn < 0) {
\r
1842 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
\r
1845 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
\r
1850 /** \brief Encode Priority
\r
1852 The function encodes the priority for an interrupt with the given priority group,
\r
1853 preemptive priority value, and subpriority value.
\r
1854 In case of a conflict between priority grouping and available
\r
1855 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\r
1857 \param [in] PriorityGroup Used priority group.
\r
1858 \param [in] PreemptPriority Preemptive priority value (starting from 0).
\r
1859 \param [in] SubPriority Subpriority value (starting from 0).
\r
1860 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
\r
1862 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
\r
1864 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
\r
1865 uint32_t PreemptPriorityBits;
\r
1866 uint32_t SubPriorityBits;
\r
1868 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
\r
1869 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
\r
1872 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
\r
1873 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
\r
1878 /** \brief Decode Priority
\r
1880 The function decodes an interrupt priority value with a given priority group to
\r
1881 preemptive priority value and subpriority value.
\r
1882 In case of a conflict between priority grouping and available
\r
1883 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\r
1885 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\r
1886 \param [in] PriorityGroup Used priority group.
\r
1887 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
\r
1888 \param [out] pSubPriority Subpriority value (starting from 0).
\r
1890 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
\r
1892 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
\r
1893 uint32_t PreemptPriorityBits;
\r
1894 uint32_t SubPriorityBits;
\r
1896 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
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1897 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
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1899 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
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1900 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
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1904 /** \brief System Reset
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1906 The function initiates a system reset request to reset the MCU.
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1908 __STATIC_INLINE void NVIC_SystemReset(void)
\r
1910 __DSB(); /* Ensure all outstanding memory accesses included
\r
1911 buffered write are completed before reset */
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1912 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
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1913 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
\r
1914 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
\r
1915 __DSB(); /* Ensure completion of memory access */
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1916 while(1) { __NOP(); } /* wait until reset */
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1919 /*@} end of CMSIS_Core_NVICFunctions */
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1922 /* ########################## FPU functions #################################### */
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1923 /** \ingroup CMSIS_Core_FunctionInterface
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1924 \defgroup CMSIS_Core_FpuFunctions FPU Functions
\r
1925 \brief Function that provides FPU type.
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1930 \fn uint32_t SCB_GetFPUType(void)
\r
1931 \brief get FPU type
\r
1934 - \b 1: Single precision FPU
\r
1935 - \b 2: Double + Single precision FPU
\r
1937 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
\r
1941 mvfr0 = SCB->MVFR0;
\r
1942 if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
\r
1943 return 2UL; // Double + Single precision FPU
\r
1944 } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
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1945 return 1UL; // Single precision FPU
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1947 return 0UL; // No FPU
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1952 /*@} end of CMSIS_Core_FpuFunctions */
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1956 /* ########################## Cache functions #################################### */
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1957 /** \ingroup CMSIS_Core_FunctionInterface
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1958 \defgroup CMSIS_Core_CacheFunctions Cache Functions
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1959 \brief Functions that configure Instruction and Data cache.
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1963 /* Cache Size ID Register Macros */
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1964 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
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1965 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
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1966 #define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
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1969 /** \brief Enable I-Cache
\r
1971 The function turns on I-Cache
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1973 __STATIC_INLINE void SCB_EnableICache (void)
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1975 #if (__ICACHE_PRESENT == 1)
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1978 SCB->ICIALLU = 0UL; // invalidate I-Cache
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1979 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
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1986 /** \brief Disable I-Cache
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1988 The function turns off I-Cache
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1990 __STATIC_INLINE void SCB_DisableICache (void)
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1992 #if (__ICACHE_PRESENT == 1)
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1995 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
\r
1996 SCB->ICIALLU = 0UL; // invalidate I-Cache
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2003 /** \brief Invalidate I-Cache
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2005 The function invalidates I-Cache
\r
2007 __STATIC_INLINE void SCB_InvalidateICache (void)
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2009 #if (__ICACHE_PRESENT == 1)
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2012 SCB->ICIALLU = 0UL;
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2019 /** \brief Enable D-Cache
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2021 The function turns on D-Cache
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2023 __STATIC_INLINE void SCB_EnableDCache (void)
\r
2025 #if (__DCACHE_PRESENT == 1)
\r
2026 uint32_t ccsidr, sshift, wshift, sw;
\r
2027 uint32_t sets, ways;
\r
2029 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
\r
2030 ccsidr = SCB->CCSIDR;
\r
2031 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
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2032 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
\r
2033 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
\r
2034 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
\r
2038 do { // invalidate D-Cache
\r
2039 uint32_t tmpways = ways;
\r
2041 sw = ((tmpways << wshift) | (sets << sshift));
\r
2043 } while(tmpways--);
\r
2047 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
\r
2055 /** \brief Disable D-Cache
\r
2057 The function turns off D-Cache
\r
2059 __STATIC_INLINE void SCB_DisableDCache (void)
\r
2061 #if (__DCACHE_PRESENT == 1)
\r
2062 uint32_t ccsidr, sshift, wshift, sw;
\r
2063 uint32_t sets, ways;
\r
2065 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
\r
2066 ccsidr = SCB->CCSIDR;
\r
2067 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
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2068 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
\r
2069 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
\r
2070 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
\r
2074 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
\r
2076 do { // clean & invalidate D-Cache
\r
2077 uint32_t tmpways = ways;
\r
2079 sw = ((tmpways << wshift) | (sets << sshift));
\r
2081 } while(tmpways--);
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2091 /** \brief Invalidate D-Cache
\r
2093 The function invalidates D-Cache
\r
2095 __STATIC_INLINE void SCB_InvalidateDCache (void)
\r
2097 #if (__DCACHE_PRESENT == 1)
\r
2098 uint32_t ccsidr, sshift, wshift, sw;
\r
2099 uint32_t sets, ways;
\r
2101 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
\r
2102 ccsidr = SCB->CCSIDR;
\r
2103 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
\r
2104 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
\r
2105 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
\r
2106 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
\r
2110 do { // invalidate D-Cache
\r
2111 uint32_t tmpways = ways;
\r
2113 sw = ((tmpways << wshift) | (sets << sshift));
\r
2115 } while(tmpways--);
\r
2124 /** \brief Clean D-Cache
\r
2126 The function cleans D-Cache
\r
2128 __STATIC_INLINE void SCB_CleanDCache (void)
\r
2130 #if (__DCACHE_PRESENT == 1)
\r
2131 uint32_t ccsidr, sshift, wshift, sw;
\r
2132 uint32_t sets, ways;
\r
2134 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
\r
2135 ccsidr = SCB->CCSIDR;
\r
2136 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
\r
2137 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
\r
2138 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
\r
2139 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
\r
2143 do { // clean D-Cache
\r
2144 uint32_t tmpways = ways;
\r
2146 sw = ((tmpways << wshift) | (sets << sshift));
\r
2148 } while(tmpways--);
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2157 /** \brief Clean & Invalidate D-Cache
\r
2159 The function cleans and Invalidates D-Cache
\r
2161 __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
\r
2163 #if (__DCACHE_PRESENT == 1)
\r
2164 uint32_t ccsidr, sshift, wshift, sw;
\r
2165 uint32_t sets, ways;
\r
2167 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
\r
2168 ccsidr = SCB->CCSIDR;
\r
2169 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
\r
2170 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
\r
2171 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
\r
2172 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
\r
2176 do { // clean & invalidate D-Cache
\r
2177 uint32_t tmpways = ways;
\r
2179 sw = ((tmpways << wshift) | (sets << sshift));
\r
2181 } while(tmpways--);
\r
2191 \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
\r
2192 \brief D-Cache Invalidate by address
\r
2193 \param[in] addr address (aligned to 32-byte boundary)
\r
2194 \param[in] dsize size of memory block (in number of bytes)
\r
2196 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
\r
2198 #if (__DCACHE_PRESENT == 1)
\r
2199 int32_t op_size = dsize;
\r
2200 uint32_t op_addr = (uint32_t)addr;
\r
2201 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
\r
2205 while (op_size > 0) {
\r
2206 SCB->DCIMVAC = op_addr;
\r
2207 op_addr += linesize;
\r
2208 op_size -= (int32_t)linesize;
\r
2218 \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
\r
2219 \brief D-Cache Clean by address
\r
2220 \param[in] addr address (aligned to 32-byte boundary)
\r
2221 \param[in] dsize size of memory block (in number of bytes)
\r
2223 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
\r
2225 #if (__DCACHE_PRESENT == 1)
\r
2226 int32_t op_size = dsize;
\r
2227 uint32_t op_addr = (uint32_t) addr;
\r
2228 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
\r
2232 while (op_size > 0) {
\r
2233 SCB->DCCMVAC = op_addr;
\r
2234 op_addr += linesize;
\r
2235 op_size -= (int32_t)linesize;
\r
2245 \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
\r
2246 \brief D-Cache Clean and Invalidate by address
\r
2247 \param[in] addr address (aligned to 32-byte boundary)
\r
2248 \param[in] dsize size of memory block (in number of bytes)
\r
2250 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
\r
2252 #if (__DCACHE_PRESENT == 1)
\r
2253 int32_t op_size = dsize;
\r
2254 uint32_t op_addr = (uint32_t) addr;
\r
2255 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
\r
2259 while (op_size > 0) {
\r
2260 SCB->DCCIMVAC = op_addr;
\r
2261 op_addr += linesize;
\r
2262 op_size -= (int32_t)linesize;
\r
2271 /*@} end of CMSIS_Core_CacheFunctions */
\r
2275 /* ################################## SysTick function ############################################ */
\r
2276 /** \ingroup CMSIS_Core_FunctionInterface
\r
2277 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\r
2278 \brief Functions that configure the System.
\r
2282 #if (__Vendor_SysTickConfig == 0)
\r
2284 /** \brief System Tick Configuration
\r
2286 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
\r
2287 Counter is in free running mode to generate periodic interrupts.
\r
2289 \param [in] ticks Number of ticks between two interrupts.
\r
2291 \return 0 Function succeeded.
\r
2292 \return 1 Function failed.
\r
2294 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
\r
2295 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
\r
2296 must contain a vendor-specific implementation of this function.
\r
2299 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
\r
2301 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
\r
2303 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
\r
2304 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
\r
2305 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
\r
2306 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\r
2307 SysTick_CTRL_TICKINT_Msk |
\r
2308 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
\r
2309 return (0UL); /* Function successful */
\r
2314 /*@} end of CMSIS_Core_SysTickFunctions */
\r
2318 /* ##################################### Debug In/Output function ########################################### */
\r
2319 /** \ingroup CMSIS_Core_FunctionInterface
\r
2320 \defgroup CMSIS_core_DebugFunctions ITM Functions
\r
2321 \brief Functions that access the ITM debug interface.
\r
2325 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
\r
2326 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
\r
2329 /** \brief ITM Send Character
\r
2331 The function transmits a character via the ITM channel 0, and
\r
2332 \li Just returns when no debugger is connected that has booked the output.
\r
2333 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\r
2335 \param [in] ch Character to transmit.
\r
2337 \returns Character to transmit.
\r
2339 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
\r
2341 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
\r
2342 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
\r
2344 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
\r
2345 ITM->PORT[0].u8 = (uint8_t)ch;
\r
2351 /** \brief ITM Receive Character
\r
2353 The function inputs a character via the external variable \ref ITM_RxBuffer.
\r
2355 \return Received character.
\r
2356 \return -1 No character pending.
\r
2358 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
\r
2359 int32_t ch = -1; /* no character available */
\r
2361 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
\r
2362 ch = ITM_RxBuffer;
\r
2363 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
\r
2370 /** \brief ITM Check Character
\r
2372 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\r
2374 \return 0 No character available.
\r
2375 \return 1 Character available.
\r
2377 __STATIC_INLINE int32_t ITM_CheckChar (void) {
\r
2379 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
\r
2380 return (0); /* no character available */
\r
2382 return (1); /* character available */
\r
2386 /*@} end of CMSIS_core_DebugFunctions */
\r
2391 #ifdef __cplusplus
\r
2395 #endif /* __CORE_CM7_H_DEPENDANT */
\r
2397 #endif /* __CMSIS_GENERIC */
\r
projects / freertos / blob