2 ******************************************************************************
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3 * @file stm32f7xx_hal_cec.h
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4 * @author MCD Application Team
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6 * @date 24-March-2015
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7 * @brief Header file of CEC HAL module.
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8 ******************************************************************************
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11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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35 ******************************************************************************
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32F7xx_HAL_CEC_H
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40 #define __STM32F7xx_HAL_CEC_H
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32f7xx_hal_def.h"
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49 /** @addtogroup STM32F7xx_HAL_Driver
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57 /* Exported types ------------------------------------------------------------*/
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58 /** @defgroup CEC_Exported_Types CEC Exported Types
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63 * @brief CEC Init Structure definition
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67 uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
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68 It can be one of @ref CEC_Signal_Free_Time
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69 and belongs to the set {0,...,7} where
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70 0x0 is the default configuration
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71 else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
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73 uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
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74 it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
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75 or CEC_EXTENDED_TOLERANCE */
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77 uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
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78 CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
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79 CEC_RX_STOP_ON_BRE: reception is stopped. */
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81 uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
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82 CEC line upon Bit Rising Error detection.
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83 CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
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84 CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
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86 uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
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87 CEC line upon Long Bit Period Error detection.
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88 CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
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89 CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
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91 uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
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92 upon an error detected on a broadcast message.
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94 It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
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96 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
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97 a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
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98 and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
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99 b) LBPE detection: error-bit generation on the CEC line
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100 if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
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102 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
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103 no error-bit generation in case neither a) nor b) are satisfied. Additionally,
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104 there is no error-bit generation in case of Short Bit Period Error detection in
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105 a broadcast message while LSTN bit is set. */
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107 uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
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108 CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
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109 CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
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111 uint32_t OwnAddress; /*!< Set OAR field, specifies CEC device address within a 15-bit long field */
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113 uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
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115 CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
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116 own address (OAR). Messages addressed to different destination are ignored.
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117 Broadcast messages are always received.
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119 CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
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120 address (OAR) with positive acknowledge. Messages addressed to different destination
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121 are received, but without interfering with the CEC bus: no acknowledge sent. */
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123 uint8_t InitiatorAddress; /* Initiator address (source logical address, sent in each header) */
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128 * @brief HAL CEC State structures definition
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132 HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */
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133 HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
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134 HAL_CEC_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
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135 HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
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136 HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
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137 HAL_CEC_STATE_STANDBY_RX = 0x05, /*!< IP ready to receive, doesn't prevent IP to transmit */
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138 HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */
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139 HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */
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140 }HAL_CEC_StateTypeDef;
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143 * @brief CEC handle Structure definition
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147 CEC_TypeDef *Instance; /* CEC registers base address */
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149 CEC_InitTypeDef Init; /* CEC communication parameters */
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151 uint8_t *pTxBuffPtr; /* Pointer to CEC Tx transfer Buffer */
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153 uint16_t TxXferCount; /* CEC Tx Transfer Counter */
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155 uint8_t *pRxBuffPtr; /* Pointer to CEC Rx transfer Buffer */
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157 uint16_t RxXferSize; /* CEC Rx Transfer size, 0: header received only */
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159 uint32_t ErrorCode; /* For errors handling purposes, copy of ISR register
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160 in case error is reported */
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162 HAL_LockTypeDef Lock; /* Locking object */
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164 HAL_CEC_StateTypeDef State; /* CEC communication state */
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166 }CEC_HandleTypeDef;
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171 /* Exported constants --------------------------------------------------------*/
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172 /** @defgroup CEC_Exported_Constants CEC Exported Constants
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176 /** @defgroup CEC_Error_Code CEC Error Code
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179 #define HAL_CEC_ERROR_NONE (uint32_t) 0x0 /*!< no error */
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180 #define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
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181 #define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
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182 #define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
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183 #define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
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184 #define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
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185 #define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
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186 #define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
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187 #define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
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188 #define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
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193 /** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
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196 #define CEC_DEFAULT_SFT ((uint32_t)0x00000000)
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197 #define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001)
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198 #define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002)
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199 #define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003)
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200 #define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004)
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201 #define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005)
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202 #define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006)
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203 #define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007)
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208 /** @defgroup CEC_Tolerance CEC Receiver Tolerance
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211 #define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000)
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212 #define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
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217 /** @defgroup CEC_BRERxStop CEC Reception Stop on Error
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220 #define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000)
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221 #define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
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226 /** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
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229 #define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
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230 #define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
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235 /** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
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238 #define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
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239 #define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
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244 /** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
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247 #define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000)
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248 #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
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253 /** @defgroup CEC_SFT_Option CEC Signal Free Time start option
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256 #define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000)
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257 #define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
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262 /** @defgroup CEC_Listening_Mode CEC Listening mode option
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265 #define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000)
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266 #define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
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271 /** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
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274 #define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16)
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279 /** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
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282 #define CEC_INITIATOR_LSB_POS ((uint32_t) 4)
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287 /** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
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290 #define CEC_IT_TXACKE CEC_IER_TXACKEIE
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291 #define CEC_IT_TXERR CEC_IER_TXERRIE
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292 #define CEC_IT_TXUDR CEC_IER_TXUDRIE
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293 #define CEC_IT_TXEND CEC_IER_TXENDIE
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294 #define CEC_IT_TXBR CEC_IER_TXBRIE
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295 #define CEC_IT_ARBLST CEC_IER_ARBLSTIE
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296 #define CEC_IT_RXACKE CEC_IER_RXACKEIE
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297 #define CEC_IT_LBPE CEC_IER_LBPEIE
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298 #define CEC_IT_SBPE CEC_IER_SBPEIE
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299 #define CEC_IT_BRE CEC_IER_BREIE
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300 #define CEC_IT_RXOVR CEC_IER_RXOVRIE
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301 #define CEC_IT_RXEND CEC_IER_RXENDIE
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302 #define CEC_IT_RXBR CEC_IER_RXBRIE
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307 /** @defgroup CEC_Flags_Definitions CEC Flags definition
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310 #define CEC_FLAG_TXACKE CEC_ISR_TXACKE
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311 #define CEC_FLAG_TXERR CEC_ISR_TXERR
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312 #define CEC_FLAG_TXUDR CEC_ISR_TXUDR
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313 #define CEC_FLAG_TXEND CEC_ISR_TXEND
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314 #define CEC_FLAG_TXBR CEC_ISR_TXBR
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315 #define CEC_FLAG_ARBLST CEC_ISR_ARBLST
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316 #define CEC_FLAG_RXACKE CEC_ISR_RXACKE
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317 #define CEC_FLAG_LBPE CEC_ISR_LBPE
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318 #define CEC_FLAG_SBPE CEC_ISR_SBPE
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319 #define CEC_FLAG_BRE CEC_ISR_BRE
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320 #define CEC_FLAG_RXOVR CEC_ISR_RXOVR
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321 #define CEC_FLAG_RXEND CEC_ISR_RXEND
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322 #define CEC_FLAG_RXBR CEC_ISR_RXBR
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327 /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
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330 #define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
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331 CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
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336 /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
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339 #define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
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344 /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
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347 #define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
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356 /* Exported macros -----------------------------------------------------------*/
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357 /** @defgroup CEC_Exported_Macros CEC Exported Macros
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361 /** @brief Reset CEC handle state
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362 * @param __HANDLE__: CEC handle.
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365 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
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367 /** @brief Checks whether or not the specified CEC interrupt flag is set.
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368 * @param __HANDLE__: specifies the CEC Handle.
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369 * @param __FLAG__: specifies the flag to check.
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370 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
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371 * @arg CEC_FLAG_TXERR: Tx Error.
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372 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
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373 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
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374 * @arg CEC_FLAG_TXBR: Tx-Byte Request.
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375 * @arg CEC_FLAG_ARBLST: Arbitration Lost
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376 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
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377 * @arg CEC_FLAG_LBPE: Rx Long period Error
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378 * @arg CEC_FLAG_SBPE: Rx Short period Error
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379 * @arg CEC_FLAG_BRE: Rx Bit Rising Error
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380 * @arg CEC_FLAG_RXOVR: Rx Overrun.
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381 * @arg CEC_FLAG_RXEND: End Of Reception.
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382 * @arg CEC_FLAG_RXBR: Rx-Byte Received.
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385 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
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387 /** @brief Clears the interrupt or status flag when raised (write at 1)
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388 * @param __HANDLE__: specifies the CEC Handle.
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389 * @param __FLAG__: specifies the interrupt/status flag to clear.
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390 * This parameter can be one of the following values:
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391 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
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392 * @arg CEC_FLAG_TXERR: Tx Error.
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393 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
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394 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
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395 * @arg CEC_FLAG_TXBR: Tx-Byte Request.
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396 * @arg CEC_FLAG_ARBLST: Arbitration Lost
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397 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
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398 * @arg CEC_FLAG_LBPE: Rx Long period Error
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399 * @arg CEC_FLAG_SBPE: Rx Short period Error
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400 * @arg CEC_FLAG_BRE: Rx Bit Rising Error
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401 * @arg CEC_FLAG_RXOVR: Rx Overrun.
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402 * @arg CEC_FLAG_RXEND: End Of Reception.
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403 * @arg CEC_FLAG_RXBR: Rx-Byte Received.
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406 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
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408 /** @brief Enables the specified CEC interrupt.
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409 * @param __HANDLE__: specifies the CEC Handle.
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410 * @param __INTERRUPT__: specifies the CEC interrupt to enable.
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411 * This parameter can be one of the following values:
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412 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
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413 * @arg CEC_IT_TXERR: Tx Error IT Enable
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414 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
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415 * @arg CEC_IT_TXEND: End of transmission IT Enable
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416 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
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417 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
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418 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
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419 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
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420 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
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421 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
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422 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
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423 * @arg CEC_IT_RXEND: End Of Reception IT Enable
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424 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
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427 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
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429 /** @brief Disables the specified CEC interrupt.
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430 * @param __HANDLE__: specifies the CEC Handle.
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431 * @param __INTERRUPT__: specifies the CEC interrupt to disable.
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432 * This parameter can be one of the following values:
\r
433 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
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434 * @arg CEC_IT_TXERR: Tx Error IT Enable
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435 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
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436 * @arg CEC_IT_TXEND: End of transmission IT Enable
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437 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
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438 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
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439 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
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440 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
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441 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
\r
442 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
\r
443 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
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444 * @arg CEC_IT_RXEND: End Of Reception IT Enable
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445 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
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448 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
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450 /** @brief Checks whether or not the specified CEC interrupt is enabled.
\r
451 * @param __HANDLE__: specifies the CEC Handle.
\r
452 * @param __INTERRUPT__: specifies the CEC interrupt to check.
\r
453 * This parameter can be one of the following values:
\r
454 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
\r
455 * @arg CEC_IT_TXERR: Tx Error IT Enable
\r
456 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
\r
457 * @arg CEC_IT_TXEND: End of transmission IT Enable
\r
458 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
\r
459 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
\r
460 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
\r
461 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
\r
462 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
\r
463 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
\r
464 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
\r
465 * @arg CEC_IT_RXEND: End Of Reception IT Enable
\r
466 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
\r
467 * @retval FlagStatus
\r
469 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
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471 /** @brief Enables the CEC device
\r
472 * @param __HANDLE__: specifies the CEC Handle.
\r
475 #define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
\r
477 /** @brief Disables the CEC device
\r
478 * @param __HANDLE__: specifies the CEC Handle.
\r
481 #define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
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483 /** @brief Set Transmission Start flag
\r
484 * @param __HANDLE__: specifies the CEC Handle.
\r
487 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
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489 /** @brief Set Transmission End flag
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490 * @param __HANDLE__: specifies the CEC Handle.
\r
492 * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
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494 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
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496 /** @brief Get Transmission Start flag
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497 * @param __HANDLE__: specifies the CEC Handle.
\r
498 * @retval FlagStatus
\r
500 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
\r
502 /** @brief Get Transmission End flag
\r
503 * @param __HANDLE__: specifies the CEC Handle.
\r
504 * @retval FlagStatus
\r
506 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
\r
508 /** @brief Clear OAR register
\r
509 * @param __HANDLE__: specifies the CEC Handle.
\r
512 #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
\r
514 /** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
\r
515 * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
\r
516 * @param __HANDLE__: specifies the CEC Handle.
\r
517 * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
\r
520 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
\r
526 /* Exported functions --------------------------------------------------------*/
\r
527 /** @addtogroup CEC_Exported_Functions
\r
531 /** @addtogroup CEC_Exported_Functions_Group1
\r
534 /* Initialization and de-initialization functions ****************************/
\r
535 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
\r
536 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
\r
537 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
\r
538 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
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543 /** @addtogroup CEC_Exported_Functions_Group2
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546 /* I/O operation functions ***************************************************/
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547 HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
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548 HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
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549 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
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550 HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
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551 uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec);
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552 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
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553 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
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554 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
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555 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
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560 /** @addtogroup CEC_Exported_Functions_Group3
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563 /* Peripheral State functions ************************************************/
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564 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
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565 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
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574 /* Private types -------------------------------------------------------------*/
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575 /** @defgroup CEC_Private_Types CEC Private Types
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583 /* Private variables ---------------------------------------------------------*/
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584 /** @defgroup CEC_Private_Variables CEC Private Variables
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592 /* Private constants ---------------------------------------------------------*/
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593 /** @defgroup CEC_Private_Constants CEC Private Constants
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601 /* Private macros ------------------------------------------------------------*/
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602 /** @defgroup CEC_Private_Macros CEC Private Macros
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606 #define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
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608 #define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
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609 ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
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611 #define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
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612 ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
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614 #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
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615 ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
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617 #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
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618 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
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620 #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
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621 ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
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623 #define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
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624 ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
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626 #define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
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627 ((__MODE__) == CEC_FULL_LISTENING_MODE))
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629 /** @brief Check CEC device Own Address Register (OAR) setting.
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630 * OAR address is written in a 15-bit field within CEC_CFGR register.
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631 * @param __ADDRESS__: CEC own address.
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632 * @retval Test result (TRUE or FALSE).
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634 #define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF)
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636 /** @brief Check CEC initiator or destination logical address setting.
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637 * Initiator and destination addresses are coded over 4 bits.
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638 * @param __ADDRESS__: CEC initiator or logical address.
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639 * @retval Test result (TRUE or FALSE).
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641 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
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643 /** @brief Check CEC message size.
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644 * The message size is the payload size: without counting the header,
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645 * it varies from 0 byte (ping operation, one header only, no payload) to
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646 * 15 bytes (1 opcode and up to 14 operands following the header).
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647 * @param __SIZE__: CEC message size.
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648 * @retval Test result (TRUE or FALSE).
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650 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
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656 /* Private functions ---------------------------------------------------------*/
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657 /** @defgroup CEC_Private_Functions CEC Private Functions
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677 #endif /* __STM32F7xx_HAL_CEC_H */
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679 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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