2 ******************************************************************************
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3 * @file stm32f7xx_hal_qspi.h
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4 * @author MCD Application Team
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6 * @date 24-March-2015
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7 * @brief Header file of QSPI HAL module.
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8 ******************************************************************************
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11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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35 ******************************************************************************
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32F7xx_HAL_QSPI_H
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40 #define __STM32F7xx_HAL_QSPI_H
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32f7xx_hal_def.h"
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49 /** @addtogroup STM32F7xx_HAL_Driver
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53 /** @addtogroup QSPI
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57 /* Exported types ------------------------------------------------------------*/
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58 /** @defgroup QSPI_Exported_Types QSPI Exported Types
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63 * @brief QSPI Init structure definition
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68 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
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69 This parameter can be a number between 0 and 255 */
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71 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
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72 This parameter can be a value between 1 and 16 */
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74 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
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75 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
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76 This parameter can be a value of @ref QSPI_SampleShifting */
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78 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
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79 required to address the flash memory. The flash capacity can be up to 4GB
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80 (addressed using 32 bits) in indirect mode, but the addressable space in
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81 memory-mapped mode is limited to 256MB
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82 This parameter can be a number between 0 and 31 */
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84 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
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85 of clock cycles which the chip select must remain high between commands.
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86 This parameter can be a value of @ref QSPI_ChipSelectHighTime */
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88 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
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89 This parameter can be a value of @ref QSPI_ClockMode */
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91 uint32_t FlashID; /* Specifies the Flash which will be used,
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92 This parameter can be a value of @ref QSPI_Flash_Select */
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94 uint32_t DualFlash; /* Specifies the Dual Flash Mode State
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95 This parameter can be a value of @ref QSPI_DualFlash_Mode */
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99 * @brief HAL QSPI State structures definition
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103 HAL_QSPI_STATE_RESET = 0x00, /*!< Peripheral not initialized */
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104 HAL_QSPI_STATE_READY = 0x01, /*!< Peripheral initialized and ready for use */
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105 HAL_QSPI_STATE_BUSY = 0x02, /*!< Peripheral in indirect mode and busy */
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106 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /*!< Peripheral in indirect mode with transmission ongoing */
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107 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /*!< Peripheral in indirect mode with reception ongoing */
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108 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /*!< Peripheral in auto polling mode ongoing */
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109 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /*!< Peripheral in memory mapped mode ongoing */
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110 HAL_QSPI_STATE_ERROR = 0x04 /*!< Peripheral in error */
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111 }HAL_QSPI_StateTypeDef;
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114 * @brief QSPI Handle Structure definition
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118 QUADSPI_TypeDef *Instance; /* QSPI registers base address */
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119 QSPI_InitTypeDef Init; /* QSPI communication parameters */
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120 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
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121 __IO uint16_t TxXferSize; /* QSPI Tx Transfer size */
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122 __IO uint16_t TxXferCount; /* QSPI Tx Transfer Counter */
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123 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
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124 __IO uint16_t RxXferSize; /* QSPI Rx Transfer size */
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125 __IO uint16_t RxXferCount; /* QSPI Rx Transfer Counter */
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126 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
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127 __IO HAL_LockTypeDef Lock; /* Locking object */
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128 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
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129 __IO uint32_t ErrorCode; /* QSPI Error code */
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130 uint32_t Timeout; /* Timeout for the QSPI memory access */
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131 }QSPI_HandleTypeDef;
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134 * @brief QSPI Command structure definition
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138 uint32_t Instruction; /* Specifies the Instruction to be sent
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139 This parameter can be a value (8-bit) between 0x00 and 0xFF */
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140 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
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141 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
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142 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
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143 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
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144 uint32_t AddressSize; /* Specifies the Address Size
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145 This parameter can be a value of @ref QSPI_AddressSize */
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146 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
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147 This parameter can be a value of @ref QSPI_AlternateBytesSize */
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148 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
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149 This parameter can be a number between 0 and 31 */
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150 uint32_t InstructionMode; /* Specifies the Instruction Mode
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151 This parameter can be a value of @ref QSPI_InstructionMode */
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152 uint32_t AddressMode; /* Specifies the Address Mode
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153 This parameter can be a value of @ref QSPI_AddressMode */
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154 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
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155 This parameter can be a value of @ref QSPI_AlternateBytesMode */
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156 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
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157 This parameter can be a value of @ref QSPI_DataMode */
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158 uint32_t NbData; /* Specifies the number of data to transfer.
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159 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
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160 until end of memory)*/
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161 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
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162 This parameter can be a value of @ref QSPI_DdrMode */
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163 uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
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164 system clock in DDR mode.
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165 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
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166 uint32_t SIOOMode; /* Specifies the send instruction only once mode
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167 This parameter can be a value of @ref QSPI_SIOOMode */
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168 }QSPI_CommandTypeDef;
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171 * @brief QSPI Auto Polling mode configuration structure definition
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175 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
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176 This parameter can be any value between 0 and 0xFFFFFFFF */
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177 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
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178 This parameter can be any value between 0 and 0xFFFFFFFF */
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179 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
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180 This parameter can be any value between 0 and 0xFFFF */
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181 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
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182 This parameter can be any value between 1 and 4 */
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183 uint32_t MatchMode; /* Specifies the method used for determining a match.
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184 This parameter can be a value of @ref QSPI_MatchMode */
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185 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
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186 This parameter can be a value of @ref QSPI_AutomaticStop */
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187 }QSPI_AutoPollingTypeDef;
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190 * @brief QSPI Memory Mapped mode configuration structure definition
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194 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
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195 This parameter can be any value between 0 and 0xFFFF */
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196 uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
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197 This parameter can be a value of @ref QSPI_TimeOutActivation */
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198 }QSPI_MemoryMappedTypeDef;
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203 /* Exported constants --------------------------------------------------------*/
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204 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
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207 /** @defgroup QSPI_ErrorCode QSPI Error Code
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210 #define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
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211 #define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */
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212 #define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */
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213 #define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */
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218 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
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221 #define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /*!<No clock cycle shift to sample data*/
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222 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
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227 /** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
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230 #define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000) /*!<nCS stay high for at least 1 clock cycle between commands*/
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231 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
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232 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
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233 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
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234 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
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235 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
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236 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
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237 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
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242 /** @defgroup QSPI_ClockMode QSPI Clock Mode
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245 #define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/
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246 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
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251 /** @defgroup QSPI_Flash_Select QSPI Flash Select
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254 #define QSPI_FLASH_ID_1 ((uint32_t)0x00000000)
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255 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
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260 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
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263 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
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264 #define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000)
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269 /** @defgroup QSPI_AddressSize QSPI Address Size
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272 #define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/
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273 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
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274 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
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275 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
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280 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
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283 #define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/
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284 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
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285 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
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286 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
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291 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode
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294 #define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/
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295 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
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296 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
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297 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
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302 /** @defgroup QSPI_AddressMode QSPI Address Mode
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305 #define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/
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306 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
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307 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
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308 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
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313 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
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316 #define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/
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317 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
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318 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
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319 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
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324 /** @defgroup QSPI_DataMode QSPI Data Mode
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327 #define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/
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328 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
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329 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
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330 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
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335 /** @defgroup QSPI_DdrMode QSPI Ddr Mode
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338 #define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/
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339 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
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344 /** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
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347 #define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/
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348 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
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353 /** @defgroup QSPI_SIOOMode QSPI SIOO Mode
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356 #define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/
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357 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
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362 /** @defgroup QSPI_MatchMode QSPI Match Mode
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365 #define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/
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366 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
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371 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
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374 #define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/
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375 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
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380 /** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
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383 #define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/
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384 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
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389 /** @defgroup QSPI_Flags QSPI Flags
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392 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
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393 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
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394 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
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395 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
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396 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
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397 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
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402 /** @defgroup QSPI_Interrupts QSPI Interrupts
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405 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
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406 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
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407 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
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408 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
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409 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
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414 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition
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417 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
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426 /* Exported macros -----------------------------------------------------------*/
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427 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
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431 /** @brief Reset QSPI handle state
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432 * @param __HANDLE__: QSPI handle.
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435 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
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437 /** @brief Enable QSPI
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438 * @param __HANDLE__: specifies the QSPI Handle.
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441 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
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443 /** @brief Disable QSPI
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444 * @param __HANDLE__: specifies the QSPI Handle.
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447 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
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449 /** @brief Enables the specified QSPI interrupt.
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450 * @param __HANDLE__: specifies the QSPI Handle.
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451 * @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
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452 * This parameter can be one of the following values:
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453 * @arg QSPI_IT_TO: QSPI Time out interrupt
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454 * @arg QSPI_IT_SM: QSPI Status match interrupt
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455 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
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456 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
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457 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
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460 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
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463 /** @brief Disables the specified QSPI interrupt.
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464 * @param __HANDLE__: specifies the QSPI Handle.
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465 * @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
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466 * This parameter can be one of the following values:
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467 * @arg QSPI_IT_TO: QSPI Timeout interrupt
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468 * @arg QSPI_IT_SM: QSPI Status match interrupt
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469 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
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470 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
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471 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
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474 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
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476 /** @brief Checks whether the specified QSPI interrupt source is enabled.
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477 * @param __HANDLE__: specifies the QSPI Handle.
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478 * @param __INTERRUPT__: specifies the QSPI interrupt source to check.
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479 * This parameter can be one of the following values:
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480 * @arg QSPI_IT_TO: QSPI Time out interrupt
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481 * @arg QSPI_IT_SM: QSPI Status match interrupt
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482 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
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483 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
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484 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
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485 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
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487 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
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490 * @brief Get the selected QSPI's flag status.
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491 * @param __HANDLE__: specifies the QSPI Handle.
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492 * @param __FLAG__: specifies the QSPI flag to check.
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493 * This parameter can be one of the following values:
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494 * @arg QSPI_FLAG_BUSY: QSPI Busy flag
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495 * @arg QSPI_FLAG_TO: QSPI Time out flag
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496 * @arg QSPI_FLAG_SM: QSPI Status match flag
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497 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
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498 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
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499 * @arg QSPI_FLAG_TE: QSPI Transfer error flag
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502 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
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504 /** @brief Clears the specified QSPI's flag status.
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505 * @param __HANDLE__: specifies the QSPI Handle.
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506 * @param __FLAG__: specifies the QSPI clear register flag that needs to be set
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507 * This parameter can be one of the following values:
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508 * @arg QSPI_FLAG_TO: QSPI Time out flag
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509 * @arg QSPI_FLAG_SM: QSPI Status match flag
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510 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
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511 * @arg QSPI_FLAG_TE: QSPI Transfer error flag
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514 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
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519 /* Exported functions --------------------------------------------------------*/
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520 /** @addtogroup QSPI_Exported_Functions
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524 /** @addtogroup QSPI_Exported_Functions_Group1
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527 /* Initialization/de-initialization functions ********************************/
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528 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
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529 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
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530 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
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531 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
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536 /** @addtogroup QSPI_Exported_Functions_Group2
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539 /* IO operation functions *****************************************************/
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540 /* QSPI IRQ handler method */
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541 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
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543 /* QSPI indirect mode */
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544 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
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545 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
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546 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
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547 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
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548 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
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549 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
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550 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
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551 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
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553 /* QSPI status flag polling mode */
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554 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
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555 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
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557 /* QSPI memory-mapped mode */
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558 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
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563 /** @addtogroup QSPI_Exported_Functions_Group3
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566 /* Callback functions in non-blocking modes ***********************************/
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567 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
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568 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
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570 /* QSPI indirect mode */
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571 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
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572 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
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573 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
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574 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
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575 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
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577 /* QSPI status flag polling mode */
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578 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
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580 /* QSPI memory-mapped mode */
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581 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
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586 /** @addtogroup QSPI_Exported_Functions_Group4
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589 /* Peripheral Control and State functions ************************************/
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590 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi);
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591 uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi);
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592 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
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593 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
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602 /* Private types -------------------------------------------------------------*/
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603 /* Private variables ---------------------------------------------------------*/
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604 /* Private constants ---------------------------------------------------------*/
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605 /** @defgroup QSPI_Private_Constants QSPI Private Constants
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613 /* Private macros ------------------------------------------------------------*/
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614 /** @defgroup QSPI_Private_Macros QSPI Private Macros
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617 /** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
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620 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
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625 /** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold
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628 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 16))
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633 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
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634 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
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636 /** @defgroup QSPI_FlashSize QSPI Flash Size
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639 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
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644 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
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645 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
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646 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
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647 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
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648 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
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649 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
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650 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
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651 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
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653 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
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654 ((CLKMODE) == QSPI_CLOCK_MODE_3))
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656 #define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \
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657 ((FLA) == QSPI_FLASH_ID_2))
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659 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
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660 ((MODE) == QSPI_DUALFLASH_DISABLE))
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663 /** @defgroup QSPI_Instruction QSPI Instruction
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666 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
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671 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
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672 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
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673 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
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674 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
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676 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
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677 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
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678 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
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679 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
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682 /** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
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685 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
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690 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
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691 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
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692 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
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693 ((MODE) == QSPI_INSTRUCTION_4_LINES))
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695 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
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696 ((MODE) == QSPI_ADDRESS_1_LINE) || \
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697 ((MODE) == QSPI_ADDRESS_2_LINES) || \
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698 ((MODE) == QSPI_ADDRESS_4_LINES))
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700 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
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701 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
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702 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
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703 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
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705 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
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706 ((MODE) == QSPI_DATA_1_LINE) || \
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707 ((MODE) == QSPI_DATA_2_LINES) || \
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708 ((MODE) == QSPI_DATA_4_LINES))
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710 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
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711 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
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713 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
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714 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
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716 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
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717 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
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719 /** @defgroup QSPI_Interval QSPI Interval
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722 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
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727 /** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
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730 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
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734 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
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735 ((MODE) == QSPI_MATCH_MODE_OR))
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737 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
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738 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
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740 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
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741 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
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743 /** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period
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746 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)
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751 #define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \
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752 ((FLAG) == QSPI_FLAG_TO) || \
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753 ((FLAG) == QSPI_FLAG_SM) || \
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754 ((FLAG) == QSPI_FLAG_FT) || \
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755 ((FLAG) == QSPI_FLAG_TC) || \
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756 ((FLAG) == QSPI_FLAG_TE))
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758 #define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFF) == 0x00000000) && ((IT) != 0x00000000))
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763 /* Private functions ---------------------------------------------------------*/
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764 /** @defgroup QSPI_Private_Functions QSPI Private Functions
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784 #endif /* __STM32F7xx_HAL_QSPI_H */
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786 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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