2 ******************************************************************************
\r
3 * @file stm32f7xx_hal_rcc_ex.h
\r
4 * @author MCD Application Team
\r
7 * @brief Header file of RCC HAL Extension module.
\r
8 ******************************************************************************
\r
11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
\r
13 * Redistribution and use in source and binary forms, with or without modification,
\r
14 * are permitted provided that the following conditions are met:
\r
15 * 1. Redistributions of source code must retain the above copyright notice,
\r
16 * this list of conditions and the following disclaimer.
\r
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
\r
18 * this list of conditions and the following disclaimer in the documentation
\r
19 * and/or other materials provided with the distribution.
\r
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
\r
21 * may be used to endorse or promote products derived from this software
\r
22 * without specific prior written permission.
\r
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
\r
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
\r
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
\r
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
\r
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
\r
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
\r
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
\r
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
\r
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
\r
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\r
35 ******************************************************************************
\r
38 /* Define to prevent recursive inclusion -------------------------------------*/
\r
39 #ifndef __STM32F7xx_HAL_RCC_EX_H
\r
40 #define __STM32F7xx_HAL_RCC_EX_H
\r
46 /* Includes ------------------------------------------------------------------*/
\r
47 #include "stm32f7xx_hal_def.h"
\r
49 /** @addtogroup STM32F7xx_HAL_Driver
\r
53 /** @addtogroup RCCEx
\r
57 /* Exported types ------------------------------------------------------------*/
\r
58 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
\r
63 * @brief PLLI2S Clock structure definition
\r
67 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
\r
68 This parameter must be a number between Min_Data = 49 and Max_Data = 432.
\r
69 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
\r
71 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
\r
72 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
\r
73 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
\r
75 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
\r
76 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
\r
77 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
\r
79 uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock.
\r
80 This parameter must be a number between 0 and 3 for respective values 2, 4, 6 and 8.
\r
81 This parameter will be used only when PLLI2S is selected as Clock Source SPDDIF-RX */
\r
82 }RCC_PLLI2SInitTypeDef;
\r
85 * @brief PLLSAI Clock structure definition
\r
89 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
\r
90 This parameter must be a number between Min_Data = 49 and Max_Data = 432.
\r
91 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
\r
93 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
\r
94 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
\r
95 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
\r
97 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
\r
98 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
\r
99 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
\r
101 uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock.
\r
102 This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider
\r
103 This parameter will be used only when PLLSAI is disabled */
\r
104 }RCC_PLLSAIInitTypeDef;
\r
107 * @brief RCC extended clocks structure definition
\r
111 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
\r
112 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
\r
114 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
\r
115 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
\r
117 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
\r
118 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
\r
120 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
\r
121 This parameter must be a number between Min_Data = 1 and Max_Data = 32
\r
122 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
\r
124 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
\r
125 This parameter must be a number between Min_Data = 1 and Max_Data = 32
\r
126 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
\r
128 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
\r
129 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
\r
131 uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection.
\r
132 This parameter can be a value of @ref RCC_RTC_Clock_Source */
\r
134 uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection.
\r
135 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
\r
137 uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
\r
138 This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
\r
140 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection
\r
141 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
\r
143 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection
\r
144 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
\r
146 uint32_t Usart1ClockSelection; /*!< USART1 clock source
\r
147 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
\r
149 uint32_t Usart2ClockSelection; /*!< USART2 clock source
\r
150 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
\r
152 uint32_t Usart3ClockSelection; /*!< USART3 clock source
\r
153 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
\r
155 uint32_t Uart4ClockSelection; /*!< UART4 clock source
\r
156 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
\r
158 uint32_t Uart5ClockSelection; /*!< UART5 clock source
\r
159 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
\r
161 uint32_t Usart6ClockSelection; /*!< USART6 clock source
\r
162 This parameter can be a value of @ref RCCEx_USART6_Clock_Source */
\r
164 uint32_t Uart7ClockSelection; /*!< UART7 clock source
\r
165 This parameter can be a value of @ref RCCEx_UART7_Clock_Source */
\r
167 uint32_t Uart8ClockSelection; /*!< UART8 clock source
\r
168 This parameter can be a value of @ref RCCEx_UART8_Clock_Source */
\r
170 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
\r
171 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
\r
173 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
\r
174 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
\r
176 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
\r
177 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
\r
179 uint32_t I2c4ClockSelection; /*!< I2C4 clock source
\r
180 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
\r
182 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source
\r
183 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
\r
185 uint32_t CecClockSelection; /*!< CEC clock source
\r
186 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
\r
188 uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC
\r
189 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
\r
191 uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source
\r
192 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
\r
194 }RCC_PeriphCLKInitTypeDef;
\r
199 /* Exported constants --------------------------------------------------------*/
\r
200 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
\r
204 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
\r
207 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
\r
208 #if defined(STM32F756xx) || defined(STM32F746xx)
\r
209 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
\r
210 #endif /* STM32F756xx || STM32F746xx */
\r
211 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
\r
212 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
\r
213 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040)
\r
214 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080)
\r
215 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100)
\r
216 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200)
\r
217 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400)
\r
218 #define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800)
\r
219 #define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000)
\r
220 #define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000)
\r
221 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000)
\r
222 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000)
\r
223 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000)
\r
224 #define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000)
\r
225 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000)
\r
226 #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000)
\r
227 #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000)
\r
228 #define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000)
\r
229 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000)
\r
230 #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000)
\r
231 #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000)
\r
232 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000)
\r
239 /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider
\r
242 #define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000)
\r
243 #define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001)
\r
244 #define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002)
\r
245 #define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003)
\r
250 /** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR
\r
253 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
\r
254 #define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0
\r
255 #define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1
\r
256 #define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR
\r
261 /** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source
\r
264 #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
\r
265 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC
\r
272 /** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source
\r
275 #define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
\r
276 #define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0
\r
277 #define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1
\r
283 /** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source
\r
286 #define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
\r
287 #define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0
\r
288 #define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1
\r
293 /** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source
\r
296 #define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000)
\r
297 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL
\r
302 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
\r
305 #define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000)
\r
306 #define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/
\r
311 /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
\r
314 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
\r
315 #define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0
\r
316 #define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1
\r
317 #define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL
\r
322 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
\r
325 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
\r
326 #define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0
\r
327 #define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1
\r
328 #define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL
\r
333 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
\r
336 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
\r
337 #define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0
\r
338 #define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1
\r
339 #define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL
\r
344 /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source
\r
347 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
\r
348 #define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0
\r
349 #define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1
\r
350 #define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL
\r
355 /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source
\r
358 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
\r
359 #define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0
\r
360 #define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1
\r
361 #define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL
\r
366 /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source
\r
369 #define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
\r
370 #define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0
\r
371 #define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1
\r
372 #define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL
\r
377 /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source
\r
380 #define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
\r
381 #define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0
\r
382 #define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1
\r
383 #define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL
\r
388 /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source
\r
391 #define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
\r
392 #define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0
\r
393 #define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1
\r
394 #define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL
\r
399 /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
\r
402 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
\r
403 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0
\r
404 #define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1
\r
409 /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source
\r
412 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
\r
413 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0
\r
414 #define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1
\r
420 /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
\r
423 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
\r
424 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0
\r
425 #define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1
\r
430 /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source
\r
433 #define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
\r
434 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0
\r
435 #define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1
\r
441 /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
\r
444 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
\r
445 #define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0
\r
446 #define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1
\r
447 #define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL
\r
453 /** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source
\r
456 #define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000)
\r
457 #define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL
\r
462 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
\r
465 #define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000)
\r
466 #define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE
\r
477 /* Exported macro ------------------------------------------------------------*/
\r
478 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
\r
481 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
\r
482 * @brief Enables or disables the AHB/APB peripheral clock.
\r
483 * @note After reset, the peripheral clock (used for registers read/write access)
\r
484 * is disabled and the application software has to enable this clock before
\r
489 /** @brief Enables or disables the AHB1 peripheral clock.
\r
490 * @note After reset, the peripheral clock (used for registers read/write access)
\r
491 * is disabled and the application software has to enable this clock before
\r
494 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
\r
495 __IO uint32_t tmpreg; \
\r
496 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
\r
497 /* Delay after an RCC peripheral clock enabling */ \
\r
498 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
\r
502 #define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \
\r
503 __IO uint32_t tmpreg; \
\r
504 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
\r
505 /* Delay after an RCC peripheral clock enabling */ \
\r
506 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
\r
510 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
\r
511 __IO uint32_t tmpreg; \
\r
512 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
\r
513 /* Delay after an RCC peripheral clock enabling */ \
\r
514 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
\r
518 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
\r
519 __IO uint32_t tmpreg; \
\r
520 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
\r
521 /* Delay after an RCC peripheral clock enabling */ \
\r
522 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
\r
526 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
\r
527 __IO uint32_t tmpreg; \
\r
528 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
\r
529 /* Delay after an RCC peripheral clock enabling */ \
\r
530 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
\r
534 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
\r
535 __IO uint32_t tmpreg; \
\r
536 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
\r
537 /* Delay after an RCC peripheral clock enabling */ \
\r
538 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
\r
542 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
\r
543 __IO uint32_t tmpreg; \
\r
544 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
\r
545 /* Delay after an RCC peripheral clock enabling */ \
\r
546 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
\r
550 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
\r
551 __IO uint32_t tmpreg; \
\r
552 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
\r
553 /* Delay after an RCC peripheral clock enabling */ \
\r
554 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
\r
558 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
\r
559 __IO uint32_t tmpreg; \
\r
560 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
\r
561 /* Delay after an RCC peripheral clock enabling */ \
\r
562 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
\r
566 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
\r
567 __IO uint32_t tmpreg; \
\r
568 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
\r
569 /* Delay after an RCC peripheral clock enabling */ \
\r
570 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
\r
574 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
\r
575 __IO uint32_t tmpreg; \
\r
576 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
\r
577 /* Delay after an RCC peripheral clock enabling */ \
\r
578 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
\r
582 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
\r
583 __IO uint32_t tmpreg; \
\r
584 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
\r
585 /* Delay after an RCC peripheral clock enabling */ \
\r
586 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
\r
590 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
\r
591 __IO uint32_t tmpreg; \
\r
592 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
\r
593 /* Delay after an RCC peripheral clock enabling */ \
\r
594 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
\r
598 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
\r
599 __IO uint32_t tmpreg; \
\r
600 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
\r
601 /* Delay after an RCC peripheral clock enabling */ \
\r
602 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
\r
606 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
\r
607 __IO uint32_t tmpreg; \
\r
608 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
\r
609 /* Delay after an RCC peripheral clock enabling */ \
\r
610 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
\r
614 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
\r
615 __IO uint32_t tmpreg; \
\r
616 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
\r
617 /* Delay after an RCC peripheral clock enabling */ \
\r
618 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
\r
622 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
\r
623 __IO uint32_t tmpreg; \
\r
624 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
\r
625 /* Delay after an RCC peripheral clock enabling */ \
\r
626 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
\r
630 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
\r
631 #define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
\r
632 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
\r
633 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
\r
634 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
\r
635 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
\r
636 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
\r
637 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
\r
638 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
\r
639 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
\r
640 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
\r
641 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
\r
642 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
\r
643 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
\r
644 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
\r
645 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
\r
646 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
\r
648 * @brief Enable ETHERNET clock.
\r
650 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
\r
651 __IO uint32_t tmpreg; \
\r
652 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
\r
653 /* Delay after an RCC peripheral clock enabling */ \
\r
654 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
\r
658 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
\r
659 __IO uint32_t tmpreg; \
\r
660 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
\r
661 /* Delay after an RCC peripheral clock enabling */ \
\r
662 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
\r
666 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
\r
667 __IO uint32_t tmpreg; \
\r
668 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
\r
669 /* Delay after an RCC peripheral clock enabling */ \
\r
670 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
\r
674 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
\r
675 __IO uint32_t tmpreg; \
\r
676 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
\r
677 /* Delay after an RCC peripheral clock enabling */ \
\r
678 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
\r
682 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
\r
683 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
\r
684 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
\r
685 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
\r
688 * @brief Disable ETHERNET clock.
\r
690 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
\r
691 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
\r
692 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
\r
693 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
\r
694 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
\r
695 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
\r
696 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
\r
697 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
\r
700 /** @brief Enable or disable the AHB2 peripheral clock.
\r
701 * @note After reset, the peripheral clock (used for registers read/write access)
\r
702 * is disabled and the application software has to enable this clock before
\r
705 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
\r
706 __IO uint32_t tmpreg; \
\r
707 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
\r
708 /* Delay after an RCC peripheral clock enabling */ \
\r
709 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
\r
713 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
\r
714 __IO uint32_t tmpreg; \
\r
715 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
\r
716 /* Delay after an RCC peripheral clock enabling */ \
\r
717 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
\r
721 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
\r
722 __IO uint32_t tmpreg; \
\r
723 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
\r
724 /* Delay after an RCC peripheral clock enabling */ \
\r
725 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
\r
727 __HAL_RCC_SYSCFG_CLK_ENABLE();\
\r
730 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
\r
731 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
\r
733 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
\r
734 __HAL_RCC_SYSCFG_CLK_DISABLE();\
\r
736 #if defined(STM32F756xx)
\r
737 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
\r
738 __IO uint32_t tmpreg; \
\r
739 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
\r
740 /* Delay after an RCC peripheral clock enabling */ \
\r
741 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
\r
745 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
\r
746 __IO uint32_t tmpreg; \
\r
747 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
\r
748 /* Delay after an RCC peripheral clock enabling */ \
\r
749 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
\r
753 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
\r
754 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
\r
755 #endif /* STM32F756x */
\r
756 /** @brief Enables or disables the AHB3 peripheral clock.
\r
757 * @note After reset, the peripheral clock (used for registers read/write access)
\r
758 * is disabled and the application software has to enable this clock before
\r
761 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
\r
762 __IO uint32_t tmpreg; \
\r
763 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
\r
764 /* Delay after an RCC peripheral clock enabling */ \
\r
765 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
\r
769 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
\r
770 __IO uint32_t tmpreg; \
\r
771 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
\r
772 /* Delay after an RCC peripheral clock enabling */ \
\r
773 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
\r
777 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
\r
778 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
\r
780 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
\r
781 * @note After reset, the peripheral clock (used for registers read/write access)
\r
782 * is disabled and the application software has to enable this clock before
\r
785 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
\r
786 __IO uint32_t tmpreg; \
\r
787 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
\r
788 /* Delay after an RCC peripheral clock enabling */ \
\r
789 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
\r
793 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
\r
794 __IO uint32_t tmpreg; \
\r
795 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
\r
796 /* Delay after an RCC peripheral clock enabling */ \
\r
797 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
\r
801 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
\r
802 __IO uint32_t tmpreg; \
\r
803 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
\r
804 /* Delay after an RCC peripheral clock enabling */ \
\r
805 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
\r
809 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
\r
810 __IO uint32_t tmpreg; \
\r
811 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
\r
812 /* Delay after an RCC peripheral clock enabling */ \
\r
813 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
\r
817 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
\r
818 __IO uint32_t tmpreg; \
\r
819 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
\r
820 /* Delay after an RCC peripheral clock enabling */ \
\r
821 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
\r
825 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
\r
826 __IO uint32_t tmpreg; \
\r
827 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
\r
828 /* Delay after an RCC peripheral clock enabling */ \
\r
829 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
\r
833 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
\r
834 __IO uint32_t tmpreg; \
\r
835 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
\r
836 /* Delay after an RCC peripheral clock enabling */ \
\r
837 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
\r
841 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
\r
842 __IO uint32_t tmpreg; \
\r
843 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
\r
844 /* Delay after an RCC peripheral clock enabling */ \
\r
845 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
\r
849 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
\r
850 __IO uint32_t tmpreg; \
\r
851 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
\r
852 /* Delay after an RCC peripheral clock enabling */ \
\r
853 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
\r
857 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
\r
858 __IO uint32_t tmpreg; \
\r
859 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
\r
860 /* Delay after an RCC peripheral clock enabling */ \
\r
861 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
\r
865 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
\r
866 __IO uint32_t tmpreg; \
\r
867 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
\r
868 /* Delay after an RCC peripheral clock enabling */ \
\r
869 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
\r
873 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
\r
874 __IO uint32_t tmpreg; \
\r
875 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
\r
876 /* Delay after an RCC peripheral clock enabling */ \
\r
877 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
\r
881 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
\r
882 __IO uint32_t tmpreg; \
\r
883 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
\r
884 /* Delay after an RCC peripheral clock enabling */ \
\r
885 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
\r
889 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
\r
890 __IO uint32_t tmpreg; \
\r
891 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
\r
892 /* Delay after an RCC peripheral clock enabling */ \
\r
893 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
\r
897 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
\r
898 __IO uint32_t tmpreg; \
\r
899 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
\r
900 /* Delay after an RCC peripheral clock enabling */ \
\r
901 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
\r
905 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
\r
906 __IO uint32_t tmpreg; \
\r
907 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
\r
908 /* Delay after an RCC peripheral clock enabling */ \
\r
909 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
\r
913 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
\r
914 __IO uint32_t tmpreg; \
\r
915 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
\r
916 /* Delay after an RCC peripheral clock enabling */ \
\r
917 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
\r
921 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
\r
922 __IO uint32_t tmpreg; \
\r
923 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
\r
924 /* Delay after an RCC peripheral clock enabling */ \
\r
925 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
\r
929 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
\r
930 __IO uint32_t tmpreg; \
\r
931 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
\r
932 /* Delay after an RCC peripheral clock enabling */ \
\r
933 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
\r
937 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
\r
938 __IO uint32_t tmpreg; \
\r
939 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
\r
940 /* Delay after an RCC peripheral clock enabling */ \
\r
941 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
\r
945 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \
\r
946 __IO uint32_t tmpreg; \
\r
947 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
\r
948 /* Delay after an RCC peripheral clock enabling */ \
\r
949 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
\r
953 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
\r
954 __IO uint32_t tmpreg; \
\r
955 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
\r
956 /* Delay after an RCC peripheral clock enabling */ \
\r
957 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
\r
961 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
\r
962 __IO uint32_t tmpreg; \
\r
963 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
\r
964 /* Delay after an RCC peripheral clock enabling */ \
\r
965 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
\r
969 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
\r
970 __IO uint32_t tmpreg; \
\r
971 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
\r
972 /* Delay after an RCC peripheral clock enabling */ \
\r
973 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
\r
977 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
\r
978 __IO uint32_t tmpreg; \
\r
979 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
\r
980 /* Delay after an RCC peripheral clock enabling */ \
\r
981 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
\r
985 #define __HAL_RCC_UART7_CLK_ENABLE() do { \
\r
986 __IO uint32_t tmpreg; \
\r
987 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
\r
988 /* Delay after an RCC peripheral clock enabling */ \
\r
989 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
\r
993 #define __HAL_RCC_UART8_CLK_ENABLE() do { \
\r
994 __IO uint32_t tmpreg; \
\r
995 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
\r
996 /* Delay after an RCC peripheral clock enabling */ \
\r
997 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
\r
1001 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
\r
1002 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
\r
1003 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
\r
1004 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
\r
1005 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
\r
1006 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
\r
1007 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
\r
1008 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
\r
1009 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
\r
1010 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
\r
1011 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
\r
1012 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
\r
1013 #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
\r
1014 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
\r
1015 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
\r
1016 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
\r
1017 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
\r
1018 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
\r
1019 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
\r
1020 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
\r
1021 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
\r
1022 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
\r
1023 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
\r
1024 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
\r
1025 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
\r
1026 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
\r
1027 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
\r
1029 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
\r
1030 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1031 * is disabled and the application software has to enable this clock before
\r
1034 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
\r
1035 __IO uint32_t tmpreg; \
\r
1036 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
\r
1037 /* Delay after an RCC peripheral clock enabling */ \
\r
1038 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
\r
1042 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
\r
1043 __IO uint32_t tmpreg; \
\r
1044 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
\r
1045 /* Delay after an RCC peripheral clock enabling */ \
\r
1046 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
\r
1050 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
\r
1051 __IO uint32_t tmpreg; \
\r
1052 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
\r
1053 /* Delay after an RCC peripheral clock enabling */ \
\r
1054 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
\r
1058 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
\r
1059 __IO uint32_t tmpreg; \
\r
1060 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
\r
1061 /* Delay after an RCC peripheral clock enabling */ \
\r
1062 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
\r
1066 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
\r
1067 __IO uint32_t tmpreg; \
\r
1068 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
\r
1069 /* Delay after an RCC peripheral clock enabling */ \
\r
1070 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
\r
1074 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
\r
1075 __IO uint32_t tmpreg; \
\r
1076 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
\r
1077 /* Delay after an RCC peripheral clock enabling */ \
\r
1078 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
\r
1082 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
\r
1083 __IO uint32_t tmpreg; \
\r
1084 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
\r
1085 /* Delay after an RCC peripheral clock enabling */ \
\r
1086 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
\r
1090 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
\r
1091 __IO uint32_t tmpreg; \
\r
1092 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
\r
1093 /* Delay after an RCC peripheral clock enabling */ \
\r
1094 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
\r
1098 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
\r
1099 __IO uint32_t tmpreg; \
\r
1100 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
\r
1101 /* Delay after an RCC peripheral clock enabling */ \
\r
1102 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
\r
1106 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
\r
1107 __IO uint32_t tmpreg; \
\r
1108 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
\r
1109 /* Delay after an RCC peripheral clock enabling */ \
\r
1110 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
\r
1114 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
\r
1115 __IO uint32_t tmpreg; \
\r
1116 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
\r
1117 /* Delay after an RCC peripheral clock enabling */ \
\r
1118 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
\r
1122 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
\r
1123 __IO uint32_t tmpreg; \
\r
1124 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
\r
1125 /* Delay after an RCC peripheral clock enabling */ \
\r
1126 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
\r
1130 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
\r
1131 __IO uint32_t tmpreg; \
\r
1132 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
\r
1133 /* Delay after an RCC peripheral clock enabling */ \
\r
1134 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
\r
1138 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
\r
1139 __IO uint32_t tmpreg; \
\r
1140 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
\r
1141 /* Delay after an RCC peripheral clock enabling */ \
\r
1142 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
\r
1146 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \
\r
1147 __IO uint32_t tmpreg; \
\r
1148 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
\r
1149 /* Delay after an RCC peripheral clock enabling */ \
\r
1150 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
\r
1154 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
\r
1155 __IO uint32_t tmpreg; \
\r
1156 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
\r
1157 /* Delay after an RCC peripheral clock enabling */ \
\r
1158 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
\r
1162 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
\r
1163 __IO uint32_t tmpreg; \
\r
1164 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
\r
1165 /* Delay after an RCC peripheral clock enabling */ \
\r
1166 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
\r
1170 #if defined(STM32F756xx) || defined(STM32F746xx)
\r
1171 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \
\r
1172 __IO uint32_t tmpreg; \
\r
1173 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
\r
1174 /* Delay after an RCC peripheral clock enabling */ \
\r
1175 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
\r
1178 #endif /* STM32F756xx || STM32F746xx */
\r
1180 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
\r
1181 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
\r
1182 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
\r
1183 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
\r
1184 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
\r
1185 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
\r
1186 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
\r
1187 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
\r
1188 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
\r
1189 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
\r
1190 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
\r
1191 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
\r
1192 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
\r
1193 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
\r
1194 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
\r
1195 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
\r
1196 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
\r
1197 #if defined(STM32F756xx) || defined(STM32F746xx)
\r
1198 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
\r
1199 #endif /* STM32F756xx || STM32F746xx */
\r
1205 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
\r
1206 * @brief Get the enable or disable status of the AHB/APB peripheral clock.
\r
1207 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1208 * is disabled and the application software has to enable this clock before
\r
1213 /** @brief Get the enable or disable status of the AHB1 peripheral clock.
\r
1214 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1215 * is disabled and the application software has to enable this clock before
\r
1218 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
\r
1219 #define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
\r
1220 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
\r
1221 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
\r
1222 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
\r
1223 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
\r
1224 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
\r
1225 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
\r
1226 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
\r
1227 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
\r
1228 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
\r
1229 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
\r
1230 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
\r
1231 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
\r
1232 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
\r
1233 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
\r
1234 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
\r
1236 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
\r
1237 #define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
\r
1238 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
\r
1239 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
\r
1240 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
\r
1241 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
\r
1242 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
\r
1243 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
\r
1244 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
\r
1245 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
\r
1246 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
\r
1247 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
\r
1248 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
\r
1249 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
\r
1250 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
\r
1251 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
\r
1252 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
\r
1254 * @brief Enable ETHERNET clock.
\r
1256 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
\r
1257 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
\r
1258 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
\r
1259 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
\r
1260 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
\r
1261 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
\r
1262 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
\r
1265 * @brief Disable ETHERNET clock.
\r
1267 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
\r
1268 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
\r
1269 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
\r
1270 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
\r
1271 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
\r
1272 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
\r
1273 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
\r
1275 /** @brief Get the enable or disable status of the AHB2 peripheral clock.
\r
1276 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1277 * is disabled and the application software has to enable this clock before
\r
1280 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
\r
1281 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
\r
1282 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
\r
1285 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
\r
1286 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
\r
1287 #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
\r
1289 #if defined(STM32F756xx)
\r
1290 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
\r
1291 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
\r
1292 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
\r
1293 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
\r
1294 #endif /* STM32F756x */
\r
1296 /** @brief Get the enable or disable status of the AHB3 peripheral clock.
\r
1297 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1298 * is disabled and the application software has to enable this clock before
\r
1301 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
\r
1302 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
\r
1304 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
\r
1305 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
\r
1307 /** @brief Get the enable or disable status of the APB1 peripheral clock.
\r
1308 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1309 * is disabled and the application software has to enable this clock before
\r
1312 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
\r
1313 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
\r
1314 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
\r
1315 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
\r
1316 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
\r
1317 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
\r
1318 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
\r
1319 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
\r
1320 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
\r
1321 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
\r
1322 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
\r
1323 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
\r
1324 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
\r
1325 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
\r
1326 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
\r
1327 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
\r
1328 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
\r
1329 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
\r
1330 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
\r
1331 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
\r
1332 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
\r
1333 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
\r
1334 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
\r
1335 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
\r
1336 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
\r
1337 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
\r
1338 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
\r
1340 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
\r
1341 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
\r
1342 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
\r
1343 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
\r
1344 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
\r
1345 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
\r
1346 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
\r
1347 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
\r
1348 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
\r
1349 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
\r
1350 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
\r
1351 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
\r
1352 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
\r
1353 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
\r
1354 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
\r
1355 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
\r
1356 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
\r
1357 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
\r
1358 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
\r
1359 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
\r
1360 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
\r
1361 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
\r
1362 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
\r
1363 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
\r
1364 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
\r
1365 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
\r
1366 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
\r
1368 /** @brief Get the enable or disable status of the APB2 peripheral clock.
\r
1369 * @note After reset, the peripheral clock (used for registers read/write access)
\r
1370 * is disabled and the application software has to enable this clock before
\r
1373 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
\r
1374 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
\r
1375 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
\r
1376 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
\r
1377 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
\r
1378 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
\r
1379 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
\r
1380 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
\r
1381 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
\r
1382 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
\r
1383 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
\r
1384 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
\r
1385 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
\r
1386 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
\r
1387 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
\r
1388 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
\r
1389 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
\r
1390 #if defined(STM32F756xx) || defined(STM32F746xx)
\r
1391 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
\r
1392 #endif /* STM32F756xx || STM32F746xx */
\r
1393 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
\r
1394 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
\r
1395 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
\r
1396 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
\r
1397 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
\r
1398 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
\r
1399 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
\r
1400 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
\r
1401 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
\r
1402 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
\r
1403 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
\r
1404 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
\r
1405 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
\r
1406 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
\r
1407 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
\r
1408 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
\r
1409 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
\r
1410 #if defined(STM32F756xx) || defined(STM32F746xx)
\r
1411 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
\r
1412 #endif /* STM32F756xx || STM32F746xx */
\r
1417 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
\r
1418 * @brief Forces or releases AHB/APB peripheral reset.
\r
1422 /** @brief Force or release AHB1 peripheral reset.
\r
1424 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
\r
1425 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
\r
1426 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
\r
1427 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
\r
1428 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
\r
1429 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
\r
1430 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
\r
1431 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
\r
1432 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
\r
1433 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
\r
1434 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
\r
1435 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
\r
1436 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
\r
1437 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
\r
1438 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
\r
1440 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
\r
1441 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
\r
1442 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
\r
1443 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
\r
1444 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
\r
1445 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
\r
1446 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
\r
1447 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
\r
1448 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
\r
1449 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
\r
1450 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
\r
1451 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
\r
1452 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
\r
1453 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
\r
1454 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
\r
1456 /** @brief Force or release AHB2 peripheral reset.
\r
1458 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
\r
1459 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
\r
1461 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
\r
1462 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
\r
1464 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
\r
1465 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
\r
1466 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
\r
1467 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
\r
1469 #if defined(STM32F756xx)
\r
1470 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
\r
1471 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
\r
1472 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
\r
1473 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
\r
1474 #endif /* STM32F756xx */
\r
1476 /** @brief Force or release AHB3 peripheral reset
\r
1478 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
\r
1479 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
\r
1480 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
\r
1482 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
\r
1483 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
\r
1484 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
\r
1486 /** @brief Force or release APB1 peripheral reset.
\r
1488 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
\r
1489 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
\r
1490 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
\r
1491 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
\r
1492 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
\r
1493 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
\r
1494 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
\r
1495 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
\r
1496 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
\r
1497 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
\r
1498 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
\r
1499 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
\r
1500 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
\r
1501 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
\r
1502 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
\r
1503 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
\r
1504 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
\r
1505 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
\r
1506 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
\r
1507 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
\r
1508 #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))
\r
1509 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
\r
1510 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
\r
1511 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
\r
1512 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
\r
1513 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
\r
1514 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
\r
1516 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
\r
1517 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
\r
1518 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
\r
1519 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
\r
1520 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
\r
1521 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
\r
1522 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
\r
1523 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
\r
1524 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
\r
1525 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
\r
1526 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
\r
1527 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
\r
1528 #define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
\r
1529 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
\r
1530 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
\r
1531 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
\r
1532 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
\r
1533 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
\r
1534 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
\r
1535 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
\r
1536 #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
\r
1537 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
\r
1538 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
\r
1539 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
\r
1540 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
\r
1541 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
\r
1542 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
\r
1544 /** @brief Force or release APB2 peripheral reset.
\r
1546 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
\r
1547 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
\r
1548 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
\r
1549 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
\r
1550 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
\r
1551 #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))
\r
1552 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
\r
1553 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
\r
1554 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
\r
1555 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
\r
1556 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
\r
1557 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
\r
1558 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
\r
1559 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
\r
1560 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
\r
1561 #if defined(STM32F756xx) || defined(STM32F746xx)
\r
1562 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
\r
1563 #endif /* STM32F756xx || STM32F746xx */
\r
1565 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
\r
1566 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
\r
1567 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
\r
1568 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
\r
1569 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
\r
1570 #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
\r
1571 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
\r
1572 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
\r
1573 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
\r
1574 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
\r
1575 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
\r
1576 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
\r
1577 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
\r
1578 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
\r
1579 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
\r
1580 #if defined(STM32F756xx) || defined(STM32F746xx)
\r
1581 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
\r
1582 #endif /* STM32F756xx || STM32F746xx */
\r
1587 /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
\r
1588 * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.
\r
1589 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1590 * power consumption.
\r
1591 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1592 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1596 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
\r
1598 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
\r
1599 #define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))
\r
1600 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
\r
1601 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
\r
1602 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
\r
1603 #define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))
\r
1604 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
\r
1605 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
\r
1606 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
\r
1607 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
\r
1608 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
\r
1609 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
\r
1610 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
\r
1611 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
\r
1612 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
\r
1613 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
\r
1614 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
\r
1615 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
\r
1616 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
\r
1617 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
\r
1618 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
\r
1619 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
\r
1620 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
\r
1621 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
\r
1622 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
\r
1624 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
\r
1625 #define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))
\r
1626 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
\r
1627 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
\r
1628 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
\r
1629 #define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))
\r
1630 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
\r
1631 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
\r
1632 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
\r
1633 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
\r
1634 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
\r
1635 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
\r
1636 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
\r
1637 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
\r
1638 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
\r
1639 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
\r
1640 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
\r
1641 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
\r
1642 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
\r
1643 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
\r
1644 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
\r
1645 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
\r
1646 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
\r
1647 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
\r
1648 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
\r
1650 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
\r
1651 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1652 * power consumption.
\r
1653 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1654 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1656 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
\r
1657 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
\r
1659 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
\r
1660 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
\r
1662 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
\r
1663 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
\r
1665 #if defined(STM32F756xx)
\r
1666 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
\r
1667 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
\r
1669 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
\r
1670 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
\r
1671 #endif /* STM32F756xx */
\r
1673 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
\r
1674 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1675 * power consumption.
\r
1676 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1677 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1679 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
\r
1680 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
\r
1682 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
\r
1683 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
\r
1685 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
\r
1686 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1687 * power consumption.
\r
1688 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1689 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1691 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
\r
1692 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
\r
1693 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
\r
1694 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
\r
1695 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
\r
1696 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
\r
1697 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
\r
1698 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
\r
1699 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
\r
1700 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
\r
1701 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
\r
1702 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
\r
1703 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
\r
1704 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
\r
1705 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
\r
1706 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
\r
1707 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
\r
1708 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
\r
1709 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
\r
1710 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
\r
1711 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))
\r
1712 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
\r
1713 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
\r
1714 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
\r
1715 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
\r
1716 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
\r
1717 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
\r
1719 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
\r
1720 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
\r
1721 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
\r
1722 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
\r
1723 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
\r
1724 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
\r
1725 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
\r
1726 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
\r
1727 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
\r
1728 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
\r
1729 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
\r
1730 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
\r
1731 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
\r
1732 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
\r
1733 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
\r
1734 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
\r
1735 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
\r
1736 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
\r
1737 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
\r
1738 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
\r
1739 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
\r
1740 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
\r
1741 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
\r
1742 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
\r
1743 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
\r
1744 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
\r
1745 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
\r
1747 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
\r
1748 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1749 * power consumption.
\r
1750 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1751 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1753 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
\r
1754 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
\r
1755 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
\r
1756 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
\r
1757 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
\r
1758 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
\r
1759 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
\r
1760 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))
\r
1761 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
\r
1762 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
\r
1763 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
\r
1764 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
\r
1765 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
\r
1766 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
\r
1767 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
\r
1768 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
\r
1769 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
\r
1770 #if defined(STM32F756xx) || defined(STM32F746xx)
\r
1771 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
\r
1772 #endif /* STM32F756xx || STM32F746xx */
\r
1774 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
\r
1775 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
\r
1776 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
\r
1777 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
\r
1778 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
\r
1779 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
\r
1780 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
\r
1781 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))
\r
1782 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
\r
1783 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
\r
1784 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
\r
1785 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
\r
1786 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
\r
1787 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
\r
1788 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
\r
1789 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
\r
1790 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
\r
1791 #if defined(STM32F756xx) || defined(STM32F746xx)
\r
1792 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
\r
1793 #endif /* STM32F756xx || STM32F746xx */
\r
1798 /** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status
\r
1799 * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.
\r
1800 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1801 * power consumption.
\r
1802 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1803 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1807 /** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
\r
1808 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1809 * power consumption.
\r
1810 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1811 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1813 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
\r
1814 #define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
\r
1815 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
\r
1816 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
\r
1817 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
\r
1818 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
\r
1819 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
\r
1820 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
\r
1821 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
\r
1822 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
\r
1823 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
\r
1824 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
\r
1825 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
\r
1826 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
\r
1827 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
\r
1828 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
\r
1829 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
\r
1830 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
\r
1831 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
\r
1832 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
\r
1833 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
\r
1834 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
\r
1835 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
\r
1836 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
\r
1837 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
\r
1839 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
\r
1840 #define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
\r
1841 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
\r
1842 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
\r
1843 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
\r
1844 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
\r
1845 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
\r
1846 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
\r
1847 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
\r
1848 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
\r
1849 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
\r
1850 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
\r
1851 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
\r
1852 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
\r
1853 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
\r
1854 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
\r
1855 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
\r
1856 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
\r
1857 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
\r
1858 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
\r
1859 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
\r
1860 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
\r
1861 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
\r
1862 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
\r
1863 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
\r
1865 /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.
\r
1866 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1867 * power consumption.
\r
1868 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1869 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1871 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
\r
1872 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
\r
1874 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
\r
1875 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
\r
1877 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
\r
1878 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
\r
1880 #if defined(STM32F756xx)
\r
1881 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)
\r
1882 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)
\r
1884 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)
\r
1885 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)
\r
1886 #endif /* STM32F756xx */
\r
1888 /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.
\r
1889 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1890 * power consumption.
\r
1891 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1892 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1894 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
\r
1895 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
\r
1897 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
\r
1898 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
\r
1900 /** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
\r
1901 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1902 * power consumption.
\r
1903 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1904 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1906 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
\r
1907 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
\r
1908 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
\r
1909 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
\r
1910 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
\r
1911 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
\r
1912 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
\r
1913 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
\r
1914 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
\r
1915 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
\r
1916 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
\r
1917 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
\r
1918 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
\r
1919 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
\r
1920 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
\r
1921 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
\r
1922 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
\r
1923 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
\r
1924 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
\r
1925 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
\r
1926 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
\r
1927 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
\r
1928 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
\r
1929 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
\r
1930 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
\r
1931 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
\r
1932 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
\r
1934 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
\r
1935 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
\r
1936 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
\r
1937 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
\r
1938 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
\r
1939 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
\r
1940 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
\r
1941 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
\r
1942 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
\r
1943 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
\r
1944 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
\r
1945 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
\r
1946 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
\r
1947 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
\r
1948 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
\r
1949 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
\r
1950 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
\r
1951 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
\r
1952 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
\r
1953 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
\r
1954 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
\r
1955 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
\r
1956 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
\r
1957 #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
\r
1958 #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
\r
1959 #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
\r
1960 #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
\r
1962 /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
\r
1963 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
1964 * power consumption.
\r
1965 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
1966 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
1968 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
\r
1969 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
\r
1970 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
\r
1971 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
\r
1972 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
\r
1973 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
\r
1974 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
\r
1975 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
\r
1976 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
\r
1977 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
\r
1978 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
\r
1979 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
\r
1980 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
\r
1981 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
\r
1982 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
\r
1983 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
\r
1984 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
\r
1985 #if defined(STM32F756xx) || defined(STM32F746xx)
\r
1986 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)
\r
1987 #endif /* STM32F756xx || STM32F746xx */
\r
1989 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
\r
1990 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
\r
1991 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
\r
1992 #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
\r
1993 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
\r
1994 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
\r
1995 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
\r
1996 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
\r
1997 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
\r
1998 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
\r
1999 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
\r
2000 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
\r
2001 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
\r
2002 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
\r
2003 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
\r
2004 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
\r
2005 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
\r
2006 #if defined(STM32F756xx) || defined(STM32F746xx)
\r
2007 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)
\r
2008 #endif /* STM32F756xx || STM32F746xx */
\r
2013 /*---------------------------------------------------------------------------------------------*/
\r
2015 /** @brief Macro to configure the Timers clocks prescalers
\r
2016 * @param __PRESC__ : specifies the Timers clocks prescalers selection
\r
2017 * This parameter can be one of the following values:
\r
2018 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
\r
2019 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
\r
2020 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
\r
2021 * division by 4 or more.
\r
2022 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
\r
2023 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
\r
2024 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
\r
2025 * to division by 8 or more.
\r
2027 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
\r
2028 RCC->DCKCFGR1 |= (__PRESC__);\
\r
2031 /** @brief Macros to Enable or Disable the PLLISAI.
\r
2032 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
\r
2034 #define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))
\r
2035 #define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
\r
2037 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
\r
2038 * @note This function must be used only when the PLLSAI is disabled.
\r
2039 * @note PLLSAI clock source is common with the main PLL (configured in
\r
2040 * RCC_PLLConfig function )
\r
2041 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
\r
2042 * This parameter must be a number between Min_Data = 49 and Max_Data = 432.
\r
2043 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
\r
2044 * output frequency is between Min_Data = 49 and Max_Data = 432 MHz.
\r
2045 * @param __PLLSAIQ__: specifies the division factor for SAI clock
\r
2046 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
\r
2047 * @param __PLLSAIR__: specifies the division factor for LTDC clock
\r
2048 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
\r
2049 * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
\r
2050 * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider .
\r
2052 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIP__) << 16) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
\r
2054 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
\r
2055 * @note This macro must be used only when the PLLI2S is disabled.
\r
2056 * @note PLLI2S clock source is common with the main PLL (configured in
\r
2057 * HAL_RCC_ClockConfig() API)
\r
2058 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
\r
2059 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
\r
2060 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
\r
2061 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
\r
2062 * @param __PLLI2SQ__: specifies the division factor for SAI clock.
\r
2063 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
\r
2064 * @param __PLLI2SR__: specifies the division factor for I2S clock
\r
2065 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
\r
2066 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
\r
2067 * on the I2S clock frequency.
\r
2068 * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.
\r
2069 * This parameter can be a number between 0 and 3 for respective values 2, 4, 6 and 8
\r
2071 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SP__) << 16) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
\r
2073 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
\r
2074 * @note This function must be called before enabling the PLLI2S.
\r
2075 * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
\r
2076 * This parameter must be a number between 1 and 32.
\r
2077 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
\r
2079 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
\r
2081 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
\r
2082 * @note This function must be called before enabling the PLLSAI.
\r
2083 * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
\r
2084 * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
\r
2085 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
\r
2087 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
\r
2089 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
\r
2091 * @note This function must be called before enabling the PLLSAI.
\r
2092 * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
\r
2093 * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
\r
2094 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
\r
2096 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\
\r
2097 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
\r
2099 /** @brief Macro to configure SAI1 clock source selection.
\r
2100 * @note This function must be called before enabling PLLSAI, PLLI2S and
\r
2102 * @param __SOURCE__: specifies the SAI1 clock source.
\r
2103 * This parameter can be one of the following values:
\r
2104 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
\r
2106 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
\r
2108 * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
\r
2109 * used as SAI1 clock.
\r
2111 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\
\r
2112 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
\r
2114 /** @brief Macro to get the SAI1 clock source.
\r
2115 * @retval The clock source can be one of the following values:
\r
2116 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
\r
2118 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
\r
2120 * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
\r
2121 * used as SAI1 clock.
\r
2123 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
\r
2126 /** @brief Macro to configure SAI2 clock source selection.
\r
2127 * @note This function must be called before enabling PLLSAI, PLLI2S and
\r
2129 * @param __SOURCE__: specifies the SAI2 clock source.
\r
2130 * This parameter can be one of the following values:
\r
2131 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
\r
2133 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
\r
2135 * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
\r
2136 * used as SAI2 clock.
\r
2138 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\
\r
2139 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
\r
2142 /** @brief Macro to get the SAI2 clock source.
\r
2143 * @retval The clock source can be one of the following values:
\r
2144 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
\r
2146 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
\r
2148 * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
\r
2149 * used as SAI2 clock.
\r
2151 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
\r
2154 /** @brief Enable PLLSAI_RDY interrupt.
\r
2156 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
\r
2158 /** @brief Disable PLLSAI_RDY interrupt.
\r
2160 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
\r
2162 /** @brief Clear the PLLSAI RDY interrupt pending bits.
\r
2164 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
\r
2166 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
\r
2167 * @retval The new state (TRUE or FALSE).
\r
2169 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
\r
2171 /** @brief Check PLLSAI RDY flag is set or not.
\r
2172 * @retval The new state (TRUE or FALSE).
\r
2174 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
\r
2176 /** @brief Macro to Get I2S clock source selection.
\r
2177 * @retval The clock source can be one of the following values:
\r
2178 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
\r
2179 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source
\r
2181 #define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
\r
2183 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
\r
2185 * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
\r
2186 * This parameter can be one of the following values:
\r
2187 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
\r
2188 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
\r
2189 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
\r
2191 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
\r
2192 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
\r
2194 /** @brief Macro to get the I2C1 clock source.
\r
2195 * @retval The clock source can be one of the following values:
\r
2196 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
\r
2197 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
\r
2198 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
\r
2200 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
\r
2202 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
\r
2204 * @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source.
\r
2205 * This parameter can be one of the following values:
\r
2206 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
\r
2207 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
\r
2208 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
\r
2210 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
\r
2211 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
\r
2213 /** @brief Macro to get the I2C2 clock source.
\r
2214 * @retval The clock source can be one of the following values:
\r
2215 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
\r
2216 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
\r
2217 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
\r
2219 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
\r
2221 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
\r
2223 * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
\r
2224 * This parameter can be one of the following values:
\r
2225 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
\r
2226 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
\r
2227 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
\r
2229 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
\r
2230 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
\r
2232 /** @brief macro to get the I2C3 clock source.
\r
2233 * @retval The clock source can be one of the following values:
\r
2234 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
\r
2235 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
\r
2236 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
\r
2238 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
\r
2240 /** @brief Macro to configure the I2C4 clock (I2C4CLK).
\r
2242 * @param __I2C4_CLKSOURCE__: specifies the I2C4 clock source.
\r
2243 * This parameter can be one of the following values:
\r
2244 * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
\r
2245 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
\r
2246 * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
\r
2248 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
\r
2249 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
\r
2251 /** @brief macro to get the I2C4 clock source.
\r
2252 * @retval The clock source can be one of the following values:
\r
2253 * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
\r
2254 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
\r
2255 * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
\r
2257 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
\r
2259 /** @brief Macro to configure the USART1 clock (USART1CLK).
\r
2261 * @param __USART1_CLKSOURCE__: specifies the USART1 clock source.
\r
2262 * This parameter can be one of the following values:
\r
2263 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
\r
2264 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
\r
2265 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
\r
2266 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
\r
2268 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
\r
2269 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
\r
2271 /** @brief macro to get the USART1 clock source.
\r
2272 * @retval The clock source can be one of the following values:
\r
2273 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
\r
2274 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
\r
2275 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
\r
2276 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
\r
2278 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
\r
2280 /** @brief Macro to configure the USART2 clock (USART2CLK).
\r
2282 * @param __USART2_CLKSOURCE__: specifies the USART2 clock source.
\r
2283 * This parameter can be one of the following values:
\r
2284 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
\r
2285 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
\r
2286 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
\r
2287 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
\r
2289 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
\r
2290 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
\r
2292 /** @brief macro to get the USART2 clock source.
\r
2293 * @retval The clock source can be one of the following values:
\r
2294 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
\r
2295 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
\r
2296 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
\r
2297 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
\r
2299 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
\r
2301 /** @brief Macro to configure the USART3 clock (USART3CLK).
\r
2303 * @param __USART3_CLKSOURCE__: specifies the USART3 clock source.
\r
2304 * This parameter can be one of the following values:
\r
2305 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
\r
2306 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
\r
2307 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
\r
2308 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
\r
2310 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
\r
2311 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
\r
2313 /** @brief macro to get the USART3 clock source.
\r
2314 * @retval The clock source can be one of the following values:
\r
2315 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
\r
2316 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
\r
2317 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
\r
2318 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
\r
2320 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
\r
2322 /** @brief Macro to configure the UART4 clock (UART4CLK).
\r
2324 * @param __UART4_CLKSOURCE__: specifies the UART4 clock source.
\r
2325 * This parameter can be one of the following values:
\r
2326 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
\r
2327 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
\r
2328 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
\r
2329 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
\r
2331 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
\r
2332 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
\r
2334 /** @brief macro to get the UART4 clock source.
\r
2335 * @retval The clock source can be one of the following values:
\r
2336 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
\r
2337 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
\r
2338 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
\r
2339 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
\r
2341 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
\r
2343 /** @brief Macro to configure the UART5 clock (UART5CLK).
\r
2345 * @param __UART5_CLKSOURCE__: specifies the UART5 clock source.
\r
2346 * This parameter can be one of the following values:
\r
2347 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
\r
2348 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
\r
2349 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
\r
2350 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
\r
2352 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
\r
2353 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
\r
2355 /** @brief macro to get the UART5 clock source.
\r
2356 * @retval The clock source can be one of the following values:
\r
2357 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
\r
2358 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
\r
2359 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
\r
2360 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
\r
2362 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
\r
2364 /** @brief Macro to configure the USART6 clock (USART6CLK).
\r
2366 * @param __USART6_CLKSOURCE__: specifies the USART6 clock source.
\r
2367 * This parameter can be one of the following values:
\r
2368 * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
\r
2369 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
\r
2370 * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
\r
2371 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
\r
2373 #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \
\r
2374 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
\r
2376 /** @brief macro to get the USART6 clock source.
\r
2377 * @retval The clock source can be one of the following values:
\r
2378 * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
\r
2379 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
\r
2380 * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
\r
2381 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
\r
2383 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
\r
2385 /** @brief Macro to configure the UART7 clock (UART7CLK).
\r
2387 * @param __UART7_CLKSOURCE__: specifies the UART7 clock source.
\r
2388 * This parameter can be one of the following values:
\r
2389 * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
\r
2390 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
\r
2391 * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
\r
2392 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
\r
2394 #define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \
\r
2395 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
\r
2397 /** @brief macro to get the UART7 clock source.
\r
2398 * @retval The clock source can be one of the following values:
\r
2399 * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
\r
2400 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
\r
2401 * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
\r
2402 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
\r
2404 #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
\r
2406 /** @brief Macro to configure the UART8 clock (UART8CLK).
\r
2408 * @param __UART8_CLKSOURCE__: specifies the UART8 clock source.
\r
2409 * This parameter can be one of the following values:
\r
2410 * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
\r
2411 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
\r
2412 * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
\r
2413 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
\r
2415 #define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \
\r
2416 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
\r
2418 /** @brief macro to get the UART8 clock source.
\r
2419 * @retval The clock source can be one of the following values:
\r
2420 * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
\r
2421 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
\r
2422 * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
\r
2423 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
\r
2425 #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
\r
2427 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
\r
2429 * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
\r
2430 * This parameter can be one of the following values:
\r
2431 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
\r
2432 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
\r
2433 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
\r
2434 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
\r
2436 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
\r
2437 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
\r
2439 /** @brief macro to get the LPTIM1 clock source.
\r
2440 * @retval The clock source can be one of the following values:
\r
2441 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
\r
2442 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
\r
2443 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
\r
2444 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
\r
2446 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
\r
2448 /** @brief Macro to configure the CEC clock (CECCLK).
\r
2450 * @param __CEC_CLKSOURCE__: specifies the CEC clock source.
\r
2451 * This parameter can be one of the following values:
\r
2452 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
\r
2453 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
\r
2455 #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
\r
2456 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
\r
2458 /** @brief macro to get the CEC clock source.
\r
2459 * @retval The clock source can be one of the following values:
\r
2460 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
\r
2461 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
\r
2463 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
\r
2465 /** @brief Macro to configure the CLK48 source (CLK48CLK).
\r
2467 * @param __CLK48_SOURCE__: specifies the CLK48 clock source.
\r
2468 * This parameter can be one of the following values:
\r
2469 * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
\r
2470 * @arg RCC_CLK48SOURCE_PLSAI1: PLLSAI1 selected as CLK48 source
\r
2472 #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
\r
2473 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
\r
2475 /** @brief macro to get the CLK48 source.
\r
2476 * @retval The clock source can be one of the following values:
\r
2477 * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
\r
2478 * @arg RCC_CLK48SOURCE_PLSAI1: PLLSAI1 used as CLK48 source
\r
2480 #define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
\r
2482 /** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK).
\r
2484 * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.
\r
2485 * This parameter can be one of the following values:
\r
2486 * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
\r
2487 * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock
\r
2489 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
\r
2490 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
\r
2492 /** @brief macro to get the SDMMC1 clock source.
\r
2493 * @retval The clock source can be one of the following values:
\r
2494 * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock
\r
2495 * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock
\r
2497 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
\r
2503 /* Exported functions --------------------------------------------------------*/
\r
2504 /** @addtogroup RCCEx_Exported_Functions_Group1
\r
2507 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
\r
2508 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
\r
2509 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
\r
2514 /* Private macros ------------------------------------------------------------*/
\r
2515 /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
\r
2518 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
\r
2521 #if defined(STM32F756xx) || defined(STM32F746xx)
\r
2522 #define IS_RCC_PERIPHCLOCK(SELECTION) \
\r
2523 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
\r
2524 (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \
\r
2525 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
\r
2526 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
\r
2527 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
\r
2528 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
\r
2529 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
\r
2530 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
\r
2531 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
\r
2532 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
\r
2533 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
\r
2534 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
\r
2535 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
\r
2536 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
\r
2537 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
\r
2538 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
\r
2539 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
\r
2540 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
\r
2541 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
\r
2542 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
\r
2543 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
\r
2544 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
\r
2545 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
\r
2546 #elif defined(STM32F745xx)
\r
2547 #define IS_RCC_PERIPHCLOCK(SELECTION) \
\r
2548 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
\r
2549 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
\r
2550 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
\r
2551 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
\r
2552 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
\r
2553 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
\r
2554 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
\r
2555 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
\r
2556 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
\r
2557 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
\r
2558 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
\r
2559 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
\r
2560 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
\r
2561 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
\r
2562 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
\r
2563 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
\r
2564 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
\r
2565 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
\r
2566 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
\r
2567 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
\r
2568 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
\r
2569 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
\r
2570 #endif /* STM32F756xx || STM32F746xx */
\r
2571 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
\r
2572 #define IS_RCC_PLLI2SP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8))
\r
2573 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
\r
2574 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
\r
2576 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
\r
2577 #define IS_RCC_PLLSAIP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8))
\r
2578 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
\r
2579 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
\r
2581 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
\r
2583 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
\r
2585 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
\r
2586 ((VALUE) == RCC_PLLSAIDIVR_4) ||\
\r
2587 ((VALUE) == RCC_PLLSAIDIVR_8) ||\
\r
2588 ((VALUE) == RCC_PLLSAIDIVR_16))
\r
2589 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \
\r
2590 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
\r
2591 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
\r
2592 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
\r
2593 ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
\r
2594 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
\r
2595 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
\r
2596 ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
\r
2598 #define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \
\r
2599 ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))
\r
2601 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
\r
2602 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
\r
2603 #define IS_RCC_USART1CLKSOURCE(SOURCE) \
\r
2604 (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
\r
2605 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
\r
2606 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
\r
2607 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
\r
2609 #define IS_RCC_USART2CLKSOURCE(SOURCE) \
\r
2610 (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
\r
2611 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
\r
2612 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
\r
2613 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
\r
2614 #define IS_RCC_USART3CLKSOURCE(SOURCE) \
\r
2615 (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
\r
2616 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
\r
2617 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
\r
2618 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
\r
2620 #define IS_RCC_UART4CLKSOURCE(SOURCE) \
\r
2621 (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
\r
2622 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
\r
2623 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
\r
2624 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
\r
2626 #define IS_RCC_UART5CLKSOURCE(SOURCE) \
\r
2627 (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
\r
2628 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
\r
2629 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
\r
2630 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
\r
2632 #define IS_RCC_USART6CLKSOURCE(SOURCE) \
\r
2633 (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \
\r
2634 ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \
\r
2635 ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \
\r
2636 ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
\r
2638 #define IS_RCC_UART7CLKSOURCE(SOURCE) \
\r
2639 (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \
\r
2640 ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \
\r
2641 ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \
\r
2642 ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
\r
2644 #define IS_RCC_UART8CLKSOURCE(SOURCE) \
\r
2645 (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \
\r
2646 ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \
\r
2647 ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \
\r
2648 ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
\r
2649 #define IS_RCC_I2C1CLKSOURCE(SOURCE) \
\r
2650 (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \
\r
2651 ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
\r
2652 ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))
\r
2653 #define IS_RCC_I2C2CLKSOURCE(SOURCE) \
\r
2654 (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \
\r
2655 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
\r
2656 ((SOURCE) == RCC_I2C2CLKSOURCE_HSI))
\r
2658 #define IS_RCC_I2C3CLKSOURCE(SOURCE) \
\r
2659 (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \
\r
2660 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
\r
2661 ((SOURCE) == RCC_I2C3CLKSOURCE_HSI))
\r
2662 #define IS_RCC_I2C4CLKSOURCE(SOURCE) \
\r
2663 (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \
\r
2664 ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
\r
2665 ((SOURCE) == RCC_I2C4CLKSOURCE_HSI))
\r
2666 #define IS_RCC_LPTIM1CLK(SOURCE) \
\r
2667 (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || \
\r
2668 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \
\r
2669 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
\r
2670 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
\r
2671 #define IS_RCC_CLK48SOURCE(SOURCE) \
\r
2672 (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \
\r
2673 ((SOURCE) == RCC_CLK48SOURCE_PLL))
\r
2674 #define IS_RCC_TIMPRES(VALUE) \
\r
2675 (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
\r
2676 ((VALUE) == RCC_TIMPRES_ACTIVATED))
\r
2692 #ifdef __cplusplus
\r
2696 #endif /* __STM32F7xx_HAL_RCC_EX_H */
\r
2698 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r
projects / freertos / blob