2 ******************************************************************************
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3 * @file stm32f7xx_hal_spi.h
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4 * @author MCD Application Team
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6 * @date 24-March-2015
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7 * @brief Header file of SPI HAL module.
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8 ******************************************************************************
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11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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35 ******************************************************************************
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32F7xx_HAL_SPI_H
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40 #define __STM32F7xx_HAL_SPI_H
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32f7xx_hal_def.h"
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49 /** @addtogroup STM32F7xx_HAL_Driver
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57 /* Exported types ------------------------------------------------------------*/
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58 /** @defgroup SPI_Exported_Types SPI Exported Types
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63 * @brief SPI Configuration Structure definition
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67 uint32_t Mode; /*!< Specifies the SPI operating mode.
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68 This parameter can be a value of @ref SPI_Mode */
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70 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
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71 This parameter can be a value of @ref SPI_Direction */
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73 uint32_t DataSize; /*!< Specifies the SPI data size.
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74 This parameter can be a value of @ref SPI_Data_Size */
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76 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
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77 This parameter can be a value of @ref SPI_Clock_Polarity */
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79 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
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80 This parameter can be a value of @ref SPI_Clock_Phase */
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82 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
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83 hardware (NSS pin) or by software using the SSI bit.
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84 This parameter can be a value of @ref SPI_Slave_Select_management */
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86 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
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87 used to configure the transmit and receive SCK clock.
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88 This parameter can be a value of @ref SPI_BaudRate_Prescaler
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89 @note The communication clock is derived from the master
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90 clock. The slave clock does not need to be set. */
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92 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
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93 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
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95 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not .
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96 This parameter can be a value of @ref SPI_TI_mode */
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98 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
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99 This parameter can be a value of @ref SPI_CRC_Calculation */
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101 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
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102 This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
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104 uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
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105 CRC Length is only used with Data8 and Data16, not other data size
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106 This parameter can be a value of @ref SPI_CRC_length */
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108 uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
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109 This parameter can be a value of @ref SPI_NSSP_Mode
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110 This mode is activated by the NSSP bit in the SPIx_CR2 register and
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111 it takes effect only if the SPI interface is configured as Motorola SPI
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112 master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
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113 CPOL setting is ignored).. */
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117 * @brief HAL State structures definition
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121 HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */
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122 HAL_SPI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
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123 HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
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124 HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
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125 HAL_SPI_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
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126 HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing*/
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127 HAL_SPI_STATE_ERROR = 0x06 /*!< SPI error state */
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128 }HAL_SPI_StateTypeDef;
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131 * @brief SPI handle Structure definition
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133 typedef struct __SPI_HandleTypeDef
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135 SPI_TypeDef *Instance; /* SPI registers base address */
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137 SPI_InitTypeDef Init; /* SPI communication parameters */
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139 uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
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141 uint16_t TxXferSize; /* SPI Tx Transfer size */
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143 uint16_t TxXferCount; /* SPI Tx Transfer Counter */
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145 uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
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147 uint16_t RxXferSize; /* SPI Rx Transfer size */
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149 uint16_t RxXferCount; /* SPI Rx Transfer Counter */
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151 uint32_t CRCSize; /* SPI CRC size used for the transfer */
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153 void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler */
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155 void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler */
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157 DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */
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159 DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */
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161 HAL_LockTypeDef Lock; /* Locking object */
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163 HAL_SPI_StateTypeDef State; /* SPI communication state */
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165 uint32_t ErrorCode; /* SPI Error code */
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167 }SPI_HandleTypeDef;
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173 /* Exported constants --------------------------------------------------------*/
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175 /** @defgroup SPI_Exported_Constants SPI Exported Constants
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179 /** @defgroup SPI_Error_Code SPI Error Code
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182 #define HAL_SPI_ERROR_NONE (uint32_t)0x00000000 /*!< No error */
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183 #define HAL_SPI_ERROR_MODF (uint32_t)0x00000001 /*!< MODF error */
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184 #define HAL_SPI_ERROR_CRC (uint32_t)0x00000002 /*!< CRC error */
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185 #define HAL_SPI_ERROR_OVR (uint32_t)0x00000004 /*!< OVR error */
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186 #define HAL_SPI_ERROR_FRE (uint32_t)0x00000008 /*!< FRE error */
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187 #define HAL_SPI_ERROR_DMA (uint32_t)0x00000010 /*!< DMA transfer error */
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188 #define HAL_SPI_ERROR_FLAG (uint32_t)0x00000020 /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
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189 #define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040 /*!< Unknow Error error */
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195 /** @defgroup SPI_Mode SPI Mode
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198 #define SPI_MODE_SLAVE ((uint32_t)0x00000000)
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199 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
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204 /** @defgroup SPI_Direction SPI Direction Mode
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207 #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
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208 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
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209 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
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214 /** @defgroup SPI_Data_Size SPI Data Size
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217 #define SPI_DATASIZE_4BIT ((uint32_t)0x0300)
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218 #define SPI_DATASIZE_5BIT ((uint32_t)0x0400)
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219 #define SPI_DATASIZE_6BIT ((uint32_t)0x0500)
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220 #define SPI_DATASIZE_7BIT ((uint32_t)0x0600)
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221 #define SPI_DATASIZE_8BIT ((uint32_t)0x0700)
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222 #define SPI_DATASIZE_9BIT ((uint32_t)0x0800)
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223 #define SPI_DATASIZE_10BIT ((uint32_t)0x0900)
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224 #define SPI_DATASIZE_11BIT ((uint32_t)0x0A00)
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225 #define SPI_DATASIZE_12BIT ((uint32_t)0x0B00)
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226 #define SPI_DATASIZE_13BIT ((uint32_t)0x0C00)
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227 #define SPI_DATASIZE_14BIT ((uint32_t)0x0D00)
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228 #define SPI_DATASIZE_15BIT ((uint32_t)0x0E00)
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229 #define SPI_DATASIZE_16BIT ((uint32_t)0x0F00)
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234 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
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237 #define SPI_POLARITY_LOW ((uint32_t)0x00000000)
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238 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
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243 /** @defgroup SPI_Clock_Phase SPI Clock Phase
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246 #define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
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247 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
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252 /** @defgroup SPI_Slave_Select_management SPI Slave Select management
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255 #define SPI_NSS_SOFT SPI_CR1_SSM
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256 #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
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257 #define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
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262 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
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265 #define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
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266 #define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000)
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271 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
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274 #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
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275 #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
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276 #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
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277 #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
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278 #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
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279 #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
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280 #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
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281 #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
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286 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
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289 #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
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290 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
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295 /** @defgroup SPI_TI_mode SPI TI mode
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298 #define SPI_TIMODE_DISABLE ((uint32_t)0x00000000)
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299 #define SPI_TIMODE_ENABLE SPI_CR2_FRF
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304 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
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307 #define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
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308 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
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313 /** @defgroup SPI_CRC_length SPI CRC Length
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315 * This parameter can be one of the following values:
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316 * SPI_CRC_LENGTH_DATASIZE: aligned with the data size
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317 * SPI_CRC_LENGTH_8BIT : CRC 8bit
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318 * SPI_CRC_LENGTH_16BIT : CRC 16bit
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320 #define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000)
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321 #define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001)
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322 #define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002)
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327 /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
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329 * This parameter can be one of the following values:
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330 * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
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331 * RXNE event is generated if the FIFO
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332 * level is greater or equal to 1/2(16-bits).
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333 * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
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334 * level is greater or equal to 1/4(8 bits). */
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335 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
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336 #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
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337 #define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000)
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343 /** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
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344 * @brief SPI Interrupt definition
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345 * Elements values convention: 0xXXXXXXXX
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346 * - XXXXXXXX : Interrupt control mask
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349 #define SPI_IT_TXE SPI_CR2_TXEIE
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350 #define SPI_IT_RXNE SPI_CR2_RXNEIE
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351 #define SPI_IT_ERR SPI_CR2_ERRIE
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357 /** @defgroup SPI_Flag_definition SPI Flag definition
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358 * @brief Flag definition
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359 * Elements values convention: 0xXXXXYYYY
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360 * - XXXX : Flag register Index
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361 * - YYYY : Flag mask
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364 #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
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365 #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
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366 #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
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367 #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
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368 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
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369 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
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370 #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
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371 #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
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372 #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
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377 /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
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380 #define SPI_FTLVL_EMPTY ((uint32_t)0x0000)
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381 #define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800)
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382 #define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000)
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383 #define SPI_FTLVL_FULL ((uint32_t)0x1800)
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389 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
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392 #define SPI_FRLVL_EMPTY ((uint32_t)0x0000)
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393 #define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200)
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394 #define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400)
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395 #define SPI_FRLVL_FULL ((uint32_t)0x0600)
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404 /* Exported macros ------------------------------------------------------------*/
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405 /** @defgroup SPI_Exported_Macros SPI Exported Macros
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409 /** @brief Reset SPI handle state
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410 * @param __HANDLE__: SPI handle.
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413 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
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415 /** @brief Enables or disables the specified SPI interrupts.
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416 * @param __HANDLE__ : specifies the SPI Handle.
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417 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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418 * @param __INTERRUPT__ : specifies the interrupt source to enable or disable.
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419 * This parameter can be one of the following values:
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420 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
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421 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
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422 * @arg SPI_IT_ERR: Error interrupt enable
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425 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
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426 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
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428 /** @brief Checks if the specified SPI interrupt source is enabled or disabled.
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429 * @param __HANDLE__ : specifies the SPI Handle.
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430 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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431 * @param __INTERRUPT__ : specifies the SPI interrupt source to check.
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432 * This parameter can be one of the following values:
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433 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
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434 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
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435 * @arg SPI_IT_ERR: Error interrupt enable
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436 * @retval The new state of __IT__ (TRUE or FALSE).
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438 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
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440 /** @brief Checks whether the specified SPI flag is set or not.
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441 * @param __HANDLE__ : specifies the SPI Handle.
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442 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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443 * @param __FLAG__ : specifies the flag to check.
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444 * This parameter can be one of the following values:
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445 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
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446 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
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447 * @arg SPI_FLAG_CRCERR: CRC error flag
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448 * @arg SPI_FLAG_MODF: Mode fault flag
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449 * @arg SPI_FLAG_OVR: Overrun flag
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450 * @arg SPI_FLAG_BSY: Busy flag
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451 * @arg SPI_FLAG_FRE: Frame format error flag
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452 * @arg SPI_FLAG_FTLVL: SPI fifo transmission level
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453 * @arg SPI_FLAG_FRLVL: SPI fifo reception level
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454 * @retval The new state of __FLAG__ (TRUE or FALSE).
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456 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
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458 /** @brief Clears the SPI CRCERR pending flag.
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459 * @param __HANDLE__ : specifies the SPI Handle.
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460 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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463 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
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465 /** @brief Clears the SPI MODF pending flag.
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466 * @param __HANDLE__ : specifies the SPI Handle.
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467 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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471 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
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473 __IO uint32_t tmpreg; \
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474 tmpreg = (__HANDLE__)->Instance->SR; \
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475 (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
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479 /** @brief Clears the SPI OVR pending flag.
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480 * @param __HANDLE__ : specifies the SPI Handle.
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481 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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485 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
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487 __IO uint32_t tmpreg; \
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488 tmpreg = (__HANDLE__)->Instance->DR; \
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489 tmpreg = (__HANDLE__)->Instance->SR; \
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493 /** @brief Clears the SPI FRE pending flag.
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494 * @param __HANDLE__ : specifies the SPI Handle.
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495 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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499 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
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501 __IO uint32_t tmpreg; \
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502 tmpreg = (__HANDLE__)->Instance->SR; \
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506 /** @brief Enables the SPI.
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507 * @param __HANDLE__ : specifies the SPI Handle.
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508 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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511 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
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513 /** @brief Disables the SPI.
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514 * @param __HANDLE__ : specifies the SPI Handle.
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515 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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518 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
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524 /* Private macros --------------------------------------------------------*/
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525 /** @defgroup SPI_Private_Macros SPI Private Macros
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529 /** @brief Sets the SPI transmit-only mode.
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530 * @param __HANDLE__ : specifies the SPI Handle.
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531 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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534 #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
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536 /** @brief Sets the SPI receive-only mode.
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537 * @param __HANDLE__ : specifies the SPI Handle.
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538 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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541 #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
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543 /** @brief Resets the CRC calculation of the SPI.
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544 * @param __HANDLE__ : specifies the SPI Handle.
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545 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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548 #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
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549 (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
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551 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
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552 ((MODE) == SPI_MODE_MASTER))
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554 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
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555 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
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556 ((MODE) == SPI_DIRECTION_1LINE))
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558 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
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560 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
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561 ((MODE) == SPI_DIRECTION_1LINE))
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563 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
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564 ((DATASIZE) == SPI_DATASIZE_15BIT) || \
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565 ((DATASIZE) == SPI_DATASIZE_14BIT) || \
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566 ((DATASIZE) == SPI_DATASIZE_13BIT) || \
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567 ((DATASIZE) == SPI_DATASIZE_12BIT) || \
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568 ((DATASIZE) == SPI_DATASIZE_11BIT) || \
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569 ((DATASIZE) == SPI_DATASIZE_10BIT) || \
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570 ((DATASIZE) == SPI_DATASIZE_9BIT) || \
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571 ((DATASIZE) == SPI_DATASIZE_8BIT) || \
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572 ((DATASIZE) == SPI_DATASIZE_7BIT) || \
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573 ((DATASIZE) == SPI_DATASIZE_6BIT) || \
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574 ((DATASIZE) == SPI_DATASIZE_5BIT) || \
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575 ((DATASIZE) == SPI_DATASIZE_4BIT))
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577 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
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578 ((CPOL) == SPI_POLARITY_HIGH))
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580 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
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581 ((CPHA) == SPI_PHASE_2EDGE))
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583 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
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584 ((NSS) == SPI_NSS_HARD_INPUT) || \
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585 ((NSS) == SPI_NSS_HARD_OUTPUT))
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587 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
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588 ((NSSP) == SPI_NSS_PULSE_DISABLE))
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590 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
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591 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
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592 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
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593 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
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594 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
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595 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
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596 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
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597 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
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599 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
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600 ((BIT) == SPI_FIRSTBIT_LSB))
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602 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
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603 ((MODE) == SPI_TIMODE_ENABLE))
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605 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
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606 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
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608 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
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609 ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
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610 ((LENGTH) == SPI_CRC_LENGTH_16BIT))
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612 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
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619 /* Exported functions --------------------------------------------------------*/
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620 /** @addtogroup SPI_Exported_Functions SPI Exported Functions
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624 /** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
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628 /* Initialization and de-initialization functions ****************************/
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629 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
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630 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
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631 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
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632 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
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637 /** @addtogroup SPI_Exported_Functions_Group2 Input and Output operation functions
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641 /* IO operation functions *****************************************************/
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642 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
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643 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
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644 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
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645 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
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646 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
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647 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
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648 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
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649 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
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650 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
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651 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
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652 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
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653 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
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655 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
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656 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
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657 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
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658 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
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659 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
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660 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
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661 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
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662 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
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667 /** @addtogroup SPI_Exported_Functions_Group3 Peripheral Control functions
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671 /* Peripheral State and Error functions ***************************************/
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672 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
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673 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
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694 #endif /* __STM32F7xx_HAL_SPI_H */
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696 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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