2 ******************************************************************************
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3 * @file stm32f7xx_hal_tim_ex.h
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4 * @author MCD Application Team
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6 * @date 24-March-2015
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7 * @brief Header file of TIM HAL Extension module.
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8 ******************************************************************************
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11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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35 ******************************************************************************
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32F7xx_HAL_TIM_EX_H
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40 #define __STM32F7xx_HAL_TIM_EX_H
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32f7xx_hal_def.h"
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49 /** @addtogroup STM32F7xx_HAL
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53 /** @addtogroup TIMEx
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57 /* Exported types ------------------------------------------------------------*/
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58 /** @defgroup TIMEx_Exported_Types TIM Exported Types
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63 * @brief TIM Hall sensor Configuration Structure definition
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69 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
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70 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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72 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
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73 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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75 uint32_t IC1Filter; /*!< Specifies the input capture filter.
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76 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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77 uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
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78 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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79 } TIM_HallSensor_InitTypeDef;
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82 * @brief TIM Master configuration Structure definition
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85 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection.
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86 This parameter can be a value of @ref TIM_Master_Mode_Selection */
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87 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
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88 This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */
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89 uint32_t MasterSlaveMode; /*!< Master/slave mode selection.
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90 This parameter can be a value of @ref TIM_Master_Slave_Mode */
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91 }TIM_MasterConfigTypeDef;
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94 * @brief TIM Break input(s) and Dead time configuration Structure definition
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95 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
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96 * filter and polarity.
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100 uint32_t OffStateRunMode; /*!< TIM off state in run mode.
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101 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
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102 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.
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103 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
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104 uint32_t LockLevel; /*!< TIM Lock level.
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105 This parameter can be a value of @ref TIM_Lock_level */
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106 uint32_t DeadTime; /*!< TIM dead Time.
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107 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
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108 uint32_t BreakState; /*!< TIM Break State.
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109 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
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110 uint32_t BreakPolarity; /*!< TIM Break input polarity.
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111 This parameter can be a value of @ref TIM_Break_Polarity */
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112 uint32_t BreakFilter; /*!< Specifies the break input filter.
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113 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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114 uint32_t Break2State; /*!< TIM Break2 State
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115 This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
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116 uint32_t Break2Polarity; /*!< TIM Break2 input polarity
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117 This parameter can be a value of @ref TIMEx_Break2_Polarity */
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118 uint32_t Break2Filter; /*!< TIM break2 input filter.
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119 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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120 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
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121 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
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122 } TIM_BreakDeadTimeConfigTypeDef;
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128 /* Exported constants --------------------------------------------------------*/
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129 /** @defgroup TIMEx_Exported_Constants TIM Exported Constants
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133 /** @defgroup TIMEx_Channel TIM Channel
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137 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
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138 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
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139 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
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140 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
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141 #define TIM_CHANNEL_5 ((uint32_t)0x0010)
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142 #define TIM_CHANNEL_6 ((uint32_t)0x0014)
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143 #define TIM_CHANNEL_ALL ((uint32_t)0x003C)
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149 /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIM Extended Output Compare and PWM Modes
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152 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
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153 #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
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154 #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
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155 #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
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156 #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
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157 #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
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158 #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
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159 #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
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161 #define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
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162 #define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
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163 #define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
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164 #define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
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165 #define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
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166 #define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
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171 /** @defgroup TIMEx_Remap TIM Remap
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174 #define TIM_TIM2_TIM8_TRGO (0x00000000)
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175 #define TIM_TIM2_ETH_PTP (0x00000400)
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176 #define TIM_TIM2_USBFS_SOF (0x00000800)
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177 #define TIM_TIM2_USBHS_SOF (0x00000C00)
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178 #define TIM_TIM5_GPIO (0x00000000)
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179 #define TIM_TIM5_LSI (0x00000040)
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180 #define TIM_TIM5_LSE (0x00000080)
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181 #define TIM_TIM5_RTC (0x000000C0)
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182 #define TIM_TIM11_GPIO (0x00000000)
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183 #define TIM_TIM11_SPDIFRX (0x00000001)
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184 #define TIM_TIM11_HSE (0x00000002)
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185 #define TIM_TIM11_MCO1 (0x00000003)
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190 /** @defgroup TIMEx_ClearInput_Source TIM Extended Clear Input Source
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193 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
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194 #define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
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195 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
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200 /** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable
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203 #define TIM_BREAK2_DISABLE ((uint32_t)0x00000000)
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204 #define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
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209 /** @defgroup TIMEx_Break2_Polarity TIMEx Break2 Polarity
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212 #define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)
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213 #define TIM_BREAK2POLARITY_HIGH (TIM_BDTR_BK2P)
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218 /** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
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221 #define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
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222 #define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
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223 #define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
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224 #define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
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229 /** @defgroup TIMEx_Master_Mode_Selection_2 TIM Extended Master Mode Selection 2 (TRGO2)
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232 #define TIM_TRGO2_RESET ((uint32_t)0x00000000)
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233 #define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
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234 #define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
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235 #define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
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236 #define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
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237 #define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
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238 #define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
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239 #define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
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240 #define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
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241 #define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
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242 #define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
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243 #define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
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244 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
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245 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
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246 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
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247 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
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252 /** @defgroup TIMEx_Slave_Mode TIM Extended Slave mode
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255 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
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256 #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
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257 #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
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258 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
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259 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
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260 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
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268 /* Exported macro ------------------------------------------------------------*/
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269 /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
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274 * @brief Sets the TIM Capture Compare Register value on runtime without
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275 * calling another time ConfigChannel function.
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276 * @param __HANDLE__: TIM handle.
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277 * @param __CHANNEL__ : TIM Channels to be configured.
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278 * This parameter can be one of the following values:
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279 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
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280 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
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281 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
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282 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
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283 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
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284 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
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285 * @param __COMPARE__: specifies the Capture Compare register new value.
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288 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
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289 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
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290 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
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291 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
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292 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
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293 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
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294 ((__HANDLE__)->Instance->CCR6 |= (__COMPARE__)))
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297 * @brief Gets the TIM Capture Compare Register value on runtime
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298 * @param __HANDLE__: TIM handle.
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299 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
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300 * This parameter can be one of the following values:
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301 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
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302 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
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303 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
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304 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
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305 * @arg TIM_CHANNEL_5: get capture/compare 5 register value
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306 * @arg TIM_CHANNEL_6: get capture/compare 6 register value
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309 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
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310 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
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311 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
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312 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
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313 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
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314 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
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315 ((__HANDLE__)->Instance->CCR6))
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321 /* Exported functions --------------------------------------------------------*/
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322 /** @addtogroup TIMEx_Exported_Functions
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326 /** @addtogroup TIMEx_Exported_Functions_Group1
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329 /* Timer Hall Sensor functions **********************************************/
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330 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
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331 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
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333 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);
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334 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);
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336 /* Blocking mode: Polling */
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337 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);
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338 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);
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339 /* Non-Blocking mode: Interrupt */
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340 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);
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341 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
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342 /* Non-Blocking mode: DMA */
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343 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
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344 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
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349 /** @addtogroup TIMEx_Exported_Functions_Group2
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352 /* Timer Complementary Output Compare functions *****************************/
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353 /* Blocking mode: Polling */
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354 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
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355 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
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357 /* Non-Blocking mode: Interrupt */
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358 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
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359 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
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361 /* Non-Blocking mode: DMA */
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362 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
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363 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
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368 /** @addtogroup TIMEx_Exported_Functions_Group3
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371 /* Timer Complementary PWM functions ****************************************/
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372 /* Blocking mode: Polling */
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373 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
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374 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
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376 /* Non-Blocking mode: Interrupt */
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377 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
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378 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
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379 /* Non-Blocking mode: DMA */
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380 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
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381 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
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386 /** @addtogroup TIMEx_Exported_Functions_Group4
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389 /* Timer Complementary One Pulse functions **********************************/
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390 /* Blocking mode: Polling */
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391 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
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392 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
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394 /* Non-Blocking mode: Interrupt */
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395 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
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396 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
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401 /** @addtogroup TIMEx_Exported_Functions_Group5
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404 /* Extension Control functions ************************************************/
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405 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
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406 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
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407 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
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408 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
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409 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
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410 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
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411 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef);
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416 /** @addtogroup TIMEx_Exported_Functions_Group6
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419 /* Extension Callback *********************************************************/
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420 void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
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421 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
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422 void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
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427 /** @addtogroup TIMEx_Exported_Functions_Group7
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430 /* Extension Peripheral State functions **************************************/
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431 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
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440 /* Private types -------------------------------------------------------------*/
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441 /* Private variables ---------------------------------------------------------*/
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442 /* Private constants ---------------------------------------------------------*/
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443 /* Private macros ------------------------------------------------------------*/
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444 /** @defgroup TIMEx_Private_Macros TIM Private Macros
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447 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
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448 ((CHANNEL) == TIM_CHANNEL_2) || \
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449 ((CHANNEL) == TIM_CHANNEL_3) || \
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450 ((CHANNEL) == TIM_CHANNEL_4) || \
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451 ((CHANNEL) == TIM_CHANNEL_5) || \
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452 ((CHANNEL) == TIM_CHANNEL_6) || \
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453 ((CHANNEL) == TIM_CHANNEL_ALL))
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455 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
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456 ((CHANNEL) == TIM_CHANNEL_2))
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458 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
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459 ((CHANNEL) == TIM_CHANNEL_2))
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461 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
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462 ((CHANNEL) == TIM_CHANNEL_2) || \
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463 ((CHANNEL) == TIM_CHANNEL_3))
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464 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
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465 ((MODE) == TIM_OCMODE_PWM2) || \
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466 ((MODE) == TIM_OCMODE_COMBINED_PWM1) || \
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467 ((MODE) == TIM_OCMODE_COMBINED_PWM2) || \
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468 ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
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469 ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
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471 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
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472 ((MODE) == TIM_OCMODE_ACTIVE) || \
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473 ((MODE) == TIM_OCMODE_INACTIVE) || \
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474 ((MODE) == TIM_OCMODE_TOGGLE) || \
\r
475 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
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476 ((MODE) == TIM_OCMODE_FORCED_INACTIVE) || \
\r
477 ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
\r
478 ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
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479 #define IS_TIM_REMAP(__TIM_REMAP__) (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\
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480 ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP)||\
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481 ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\
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482 ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\
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483 ((__TIM_REMAP__) == TIM_TIM5_GPIO)||\
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484 ((__TIM_REMAP__) == TIM_TIM5_LSI)||\
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485 ((__TIM_REMAP__) == TIM_TIM5_LSE)||\
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486 ((__TIM_REMAP__) == TIM_TIM5_RTC)||\
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487 ((__TIM_REMAP__) == TIM_TIM11_GPIO)||\
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488 ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX)||\
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489 ((__TIM_REMAP__) == TIM_TIM11_HSE)||\
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490 ((__TIM_REMAP__) == TIM_TIM11_MCO1))
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491 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF)
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492 #define IS_TIM_BREAK_FILTER(__FILTER__) ((__FILTER__) <= 0xF)
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493 #define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \
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494 ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
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495 ((MODE) == TIM_CLEARINPUTSOURCE_NONE))
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496 #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \
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497 ((STATE) == TIM_BREAK2_DISABLE))
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498 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
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499 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
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500 #define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))
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501 #define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) || \
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502 ((SOURCE) == TIM_TRGO2_ENABLE) || \
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503 ((SOURCE) == TIM_TRGO2_UPDATE) || \
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504 ((SOURCE) == TIM_TRGO2_OC1) || \
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505 ((SOURCE) == TIM_TRGO2_OC1REF) || \
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506 ((SOURCE) == TIM_TRGO2_OC2REF) || \
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507 ((SOURCE) == TIM_TRGO2_OC3REF) || \
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508 ((SOURCE) == TIM_TRGO2_OC3REF) || \
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509 ((SOURCE) == TIM_TRGO2_OC4REF) || \
\r
510 ((SOURCE) == TIM_TRGO2_OC5REF) || \
\r
511 ((SOURCE) == TIM_TRGO2_OC6REF) || \
\r
512 ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
\r
513 ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
\r
514 ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
\r
515 ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
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516 ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
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517 ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
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518 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
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519 ((MODE) == TIM_SLAVEMODE_RESET) || \
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520 ((MODE) == TIM_SLAVEMODE_GATED) || \
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521 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
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522 ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \
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523 ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
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529 /* Private functions ---------------------------------------------------------*/
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530 /** @defgroup TIMEx_Private_Functions TIM Private Functions
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550 #endif /* __STM32F7xx_HAL_TIM_EX_H */
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552 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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