2 ******************************************************************************
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3 * @file stm32f7xx_ll_sdmmc.h
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4 * @author MCD Application Team
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7 * @brief Header file of SDMMC HAL module.
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8 ******************************************************************************
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11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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35 ******************************************************************************
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32F7xx_LL_SDMMC_H
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40 #define __STM32F7xx_LL_SDMMC_H
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32f7xx_hal_def.h"
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49 /** @addtogroup STM32F7xx_Driver
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53 /** @addtogroup SDMMC_LL
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57 /* Exported types ------------------------------------------------------------*/
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58 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
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63 * @brief SDMMC Configuration Structure definition
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67 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
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68 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
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70 uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
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71 enabled or disabled.
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72 This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
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74 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
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75 disabled when the bus is idle.
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76 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
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78 uint32_t BusWide; /*!< Specifies the SDMMC bus width.
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79 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
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81 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
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82 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
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84 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
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85 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
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91 * @brief SDMMC Command Control structure
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95 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
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96 to a card as part of a command message. If a command
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97 contains an argument, it must be loaded into this register
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98 before writing the command to the command register. */
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100 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
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103 uint32_t Response; /*!< Specifies the SDMMC response type.
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104 This parameter can be a value of @ref SDMMC_LL_Response_Type */
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106 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
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107 enabled or disabled.
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108 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
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110 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
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111 is enabled or disabled.
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112 This parameter can be a value of @ref SDMMC_LL_CPSM_State */
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113 }SDMMC_CmdInitTypeDef;
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117 * @brief SDMMC Data Control structure
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121 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
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123 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
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125 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
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126 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
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128 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
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129 is a read or write.
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130 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
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132 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
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133 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
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135 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
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136 is enabled or disabled.
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137 This parameter can be a value of @ref SDMMC_LL_DPSM_State */
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138 }SDMMC_DataInitTypeDef;
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144 /* Exported constants --------------------------------------------------------*/
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145 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
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149 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge
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152 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
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153 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
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155 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
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156 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
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161 /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
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164 #define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
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165 #define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS
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167 #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \
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168 ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
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173 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
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176 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
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177 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
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179 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
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180 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
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185 /** @defgroup SDMMC_LL_Bus_Wide Bus Width
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188 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000)
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189 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
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190 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
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192 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
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193 ((WIDE) == SDMMC_BUS_WIDE_4B) || \
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194 ((WIDE) == SDMMC_BUS_WIDE_8B))
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199 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
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202 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
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203 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
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205 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
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206 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
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211 /** @defgroup SDMMC_LL_Clock_Division Clock Division
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214 #define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF)
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219 /** @defgroup SDMMC_LL_Command_Index Command Index
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222 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40)
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227 /** @defgroup SDMMC_LL_Response_Type Response Type
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230 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000)
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231 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
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232 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
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234 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \
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235 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
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236 ((RESPONSE) == SDMMC_RESPONSE_LONG))
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241 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
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244 #define SDMMC_WAIT_NO ((uint32_t)0x00000000)
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245 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
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246 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
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248 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
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249 ((WAIT) == SDMMC_WAIT_IT) || \
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250 ((WAIT) == SDMMC_WAIT_PEND))
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255 /** @defgroup SDMMC_LL_CPSM_State CPSM State
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258 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000)
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259 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
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261 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
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262 ((CPSM) == SDMMC_CPSM_ENABLE))
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267 /** @defgroup SDMMC_LL_Response_Registers Response Register
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270 #define SDMMC_RESP1 ((uint32_t)0x00000000)
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271 #define SDMMC_RESP2 ((uint32_t)0x00000004)
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272 #define SDMMC_RESP3 ((uint32_t)0x00000008)
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273 #define SDMMC_RESP4 ((uint32_t)0x0000000C)
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275 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
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276 ((RESP) == SDMMC_RESP2) || \
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277 ((RESP) == SDMMC_RESP3) || \
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278 ((RESP) == SDMMC_RESP4))
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283 /** @defgroup SDMMC_LL_Data_Length Data Lenght
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286 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
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291 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
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294 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
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295 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
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296 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
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297 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
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298 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
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299 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
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300 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
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301 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
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302 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
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303 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
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304 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
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305 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
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306 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
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307 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
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308 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
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310 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \
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311 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
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312 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \
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313 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \
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314 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \
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315 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \
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316 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \
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317 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \
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318 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \
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319 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \
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320 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
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321 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
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322 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
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323 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
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324 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
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329 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
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332 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
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333 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
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335 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
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336 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
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341 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type
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344 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
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345 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE
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347 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
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348 ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
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353 /** @defgroup SDMMC_LL_DPSM_State DPSM State
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356 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000)
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357 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
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359 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
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360 ((DPSM) == SDMMC_DPSM_ENABLE))
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365 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
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368 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000)
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369 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
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371 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
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372 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
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377 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
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380 #define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL
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381 #define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL
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382 #define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT
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383 #define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT
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384 #define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR
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385 #define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR
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386 #define SDMMC_IT_CMDREND SDMMC_STA_CMDREND
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387 #define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT
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388 #define SDMMC_IT_DATAEND SDMMC_STA_DATAEND
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389 #define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND
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390 #define SDMMC_IT_CMDACT SDMMC_STA_CMDACT
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391 #define SDMMC_IT_TXACT SDMMC_STA_TXACT
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392 #define SDMMC_IT_RXACT SDMMC_STA_RXACT
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393 #define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE
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394 #define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF
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395 #define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF
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396 #define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF
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397 #define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE
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398 #define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE
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399 #define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL
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400 #define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL
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401 #define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT
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406 /** @defgroup SDMMC_LL_Flags Flags
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409 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
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410 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
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411 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
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412 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
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413 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
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414 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
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415 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
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416 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
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417 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
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418 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
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419 #define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT
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420 #define SDMMC_FLAG_TXACT SDMMC_STA_TXACT
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421 #define SDMMC_FLAG_RXACT SDMMC_STA_RXACT
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422 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
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423 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
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424 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
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425 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
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426 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
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427 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
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428 #define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL
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429 #define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL
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430 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
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439 /* Exported macro ------------------------------------------------------------*/
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440 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
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444 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
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445 * @brief SDMMC_LL registers bit address in the alias region
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448 /* ---------------------- SDMMC registers bit mask --------------------------- */
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449 /* --- CLKCR Register ---*/
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450 /* CLKCR register clear mask */
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451 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\
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452 SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\
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453 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))
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455 /* --- DCTRL Register ---*/
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456 /* SDMMC DCTRL Clear Mask */
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457 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\
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458 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE))
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460 /* --- CMD Register ---*/
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461 /* CMD Register clear mask */
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462 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
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463 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\
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464 SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND))
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466 /* SDMMC Initialization Frequency (400KHz max) */
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467 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
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469 /* SDMMC Data Transfer Frequency (25MHz max) */
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470 #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
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476 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
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477 * @brief macros to handle interrupts and specific clock configurations
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482 * @brief Enable the SDMMC device.
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483 * @param __INSTANCE__: SDMMC Instance
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486 #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)
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489 * @brief Disable the SDMMC device.
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490 * @param __INSTANCE__: SDMMC Instance
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493 #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
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496 * @brief Enable the SDMMC DMA transfer.
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497 * @param __INSTANCE__: SDMMC Instance
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500 #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)
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502 * @brief Disable the SDMMC DMA transfer.
\r
503 * @param __INSTANCE__: SDMMC Instance
\r
506 #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
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509 * @brief Enable the SDMMC device interrupt.
\r
510 * @param __INSTANCE__ : Pointer to SDMMC register base
\r
511 * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled.
\r
512 * This parameter can be one or a combination of the following values:
\r
513 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
\r
514 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
\r
515 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
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516 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
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517 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
\r
518 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
\r
519 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
\r
520 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
\r
521 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
\r
522 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
\r
523 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
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524 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
\r
525 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
\r
526 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
\r
527 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
\r
528 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
\r
529 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
\r
530 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
\r
531 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
\r
532 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
\r
533 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
\r
534 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
\r
537 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
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540 * @brief Disable the SDMMC device interrupt.
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541 * @param __INSTANCE__ : Pointer to SDMMC register base
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542 * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled.
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543 * This parameter can be one or a combination of the following values:
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544 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
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545 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
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546 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
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547 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
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548 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
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549 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
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550 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
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551 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
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552 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
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553 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
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554 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
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555 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
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556 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
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557 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
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558 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
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559 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
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560 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
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561 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
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562 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
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563 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
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564 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
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565 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
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568 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
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571 * @brief Checks whether the specified SDMMC flag is set or not.
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572 * @param __INSTANCE__ : Pointer to SDMMC register base
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573 * @param __FLAG__: specifies the flag to check.
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574 * This parameter can be one of the following values:
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575 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
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576 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
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577 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
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578 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
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579 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
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580 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
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581 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
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582 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
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583 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
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584 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
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585 * @arg SDMMC_FLAG_CMDACT: Command transfer in progress
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586 * @arg SDMMC_FLAG_TXACT: Data transmit in progress
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587 * @arg SDMMC_FLAG_RXACT: Data receive in progress
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588 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
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589 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
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590 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
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591 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
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592 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
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593 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
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594 * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
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595 * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
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596 * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
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597 * @retval The new state of SDMMC_FLAG (SET or RESET).
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599 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
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603 * @brief Clears the SDMMC pending flags.
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604 * @param __INSTANCE__ : Pointer to SDMMC register base
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605 * @param __FLAG__: specifies the flag to clear.
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606 * This parameter can be one or a combination of the following values:
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607 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
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608 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
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609 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
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610 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
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611 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
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612 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
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613 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
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614 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
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615 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
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616 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
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617 * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
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620 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
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623 * @brief Checks whether the specified SDMMC interrupt has occurred or not.
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624 * @param __INSTANCE__ : Pointer to SDMMC register base
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625 * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
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626 * This parameter can be one of the following values:
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627 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
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628 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
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629 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
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630 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
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631 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
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632 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
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633 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
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634 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
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635 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
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636 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
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637 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
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638 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
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639 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
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640 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
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641 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
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642 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
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643 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
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644 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
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645 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
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646 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
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647 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
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648 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
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649 * @retval The new state of SDMMC_IT (SET or RESET).
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651 #define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
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654 * @brief Clears the SDMMC's interrupt pending bits.
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655 * @param __INSTANCE__ : Pointer to SDMMC register base
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656 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
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657 * This parameter can be one or a combination of the following values:
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658 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
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659 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
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660 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
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661 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
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662 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
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663 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
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664 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
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665 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
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666 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
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667 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
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670 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
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673 * @brief Enable Start the SD I/O Read Wait operation.
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674 * @param __INSTANCE__ : Pointer to SDMMC register base
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677 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
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680 * @brief Disable Start the SD I/O Read Wait operations.
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681 * @param __INSTANCE__ : Pointer to SDMMC register base
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684 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
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687 * @brief Enable Start the SD I/O Read Wait operation.
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688 * @param __INSTANCE__ : Pointer to SDMMC register base
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691 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
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694 * @brief Disable Stop the SD I/O Read Wait operations.
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695 * @param __INSTANCE__ : Pointer to SDMMC register base
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698 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
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701 * @brief Enable the SD I/O Mode Operation.
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702 * @param __INSTANCE__ : Pointer to SDMMC register base
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705 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
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708 * @brief Disable the SD I/O Mode Operation.
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709 * @param __INSTANCE__ : Pointer to SDMMC register base
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712 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
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715 * @brief Enable the SD I/O Suspend command sending.
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716 * @param __INSTANCE__ : Pointer to SDMMC register base
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719 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND)
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722 * @brief Disable the SD I/O Suspend command sending.
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723 * @param __INSTANCE__ : Pointer to SDMMC register base
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726 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
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736 /* Exported functions --------------------------------------------------------*/
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737 /** @addtogroup SDMMC_LL_Exported_Functions
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741 /* Initialization/de-initialization functions **********************************/
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742 /** @addtogroup HAL_SDMMC_LL_Group1
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745 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
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750 /* I/O operation functions *****************************************************/
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751 /** @addtogroup HAL_SDMMC_LL_Group2
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754 /* Blocking mode: Polling */
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755 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
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756 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
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761 /* Peripheral Control functions ************************************************/
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762 /** @addtogroup HAL_SDMMC_LL_Group3
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765 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
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766 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
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767 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
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769 /* Command path state machine (CPSM) management functions */
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770 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
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771 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
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772 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
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774 /* Data path state machine (DPSM) management functions */
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775 HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
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776 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
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777 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
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779 /* SDMMC Cards mode management functions */
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780 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
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802 #endif /* __STM32F7xx_LL_SDMMC_H */
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804 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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