2 ******************************************************************************
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3 * @file stm32f7xx_hal_cec.c
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4 * @author MCD Application Team
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6 * @date 24-March-2015
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7 * @brief CEC HAL module driver.
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9 * This file provides firmware functions to manage the following
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10 * functionalities of the High Definition Multimedia Interface
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11 * Consumer Electronics Control Peripheral (CEC).
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12 * + Initialization and de-initialization function
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13 * + IO operation function
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14 * + Peripheral Control function
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18 ===============================================================================
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19 ##### How to use this driver #####
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20 ===============================================================================
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22 The CEC HAL driver can be used as follow:
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24 (#) Declare a CEC_HandleTypeDef handle structure.
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25 (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
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26 (##) Enable the CEC interface clock.
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27 (##) CEC pins configuration:
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28 (+) Enable the clock for the CEC GPIOs.
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29 (+) Configure these CEC pins as alternate function pull-up.
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30 (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
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31 and HAL_CEC_Receive_IT() APIs):
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32 (+) Configure the CEC interrupt priority.
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33 (+) Enable the NVIC CEC IRQ handle.
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34 (@) The specific CEC interrupts (Transmission complete interrupt,
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35 RXNE interrupt and Error Interrupts) will be managed using the macros
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36 __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
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37 and receive process.
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39 (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
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40 in case of Bit Rising Error, Error-Bit generation conditions, device logical
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41 address and Listen mode in the hcec Init structure.
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43 (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
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45 (@) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
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46 by calling the customed HAL_CEC_MspInit() API.
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49 ******************************************************************************
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52 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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54 * Redistribution and use in source and binary forms, with or without modification,
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55 * are permitted provided that the following conditions are met:
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56 * 1. Redistributions of source code must retain the above copyright notice,
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57 * this list of conditions and the following disclaimer.
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58 * 2. Redistributions in binary form must reproduce the above copyright notice,
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59 * this list of conditions and the following disclaimer in the documentation
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60 * and/or other materials provided with the distribution.
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61 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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62 * may be used to endorse or promote products derived from this software
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63 * without specific prior written permission.
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65 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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66 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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68 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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69 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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70 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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71 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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72 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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73 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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74 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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76 ******************************************************************************
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79 /* Includes ------------------------------------------------------------------*/
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80 #include "stm32f7xx_hal.h"
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82 /** @addtogroup STM32F7xx_HAL_Driver
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86 /** @defgroup CEC CEC
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87 * @brief HAL CEC module driver
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90 #ifdef HAL_CEC_MODULE_ENABLED
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92 /* Private typedef -----------------------------------------------------------*/
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93 /* Private define ------------------------------------------------------------*/
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94 /** @defgroup CEC_Private_Constants CEC Private Constants
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97 #define CEC_CFGR_FIELDS (CEC_CFGR_SFT | CEC_CFGR_RXTOL | CEC_CFGR_BRESTP \
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98 | CEC_CFGR_BREGEN | CEC_CFGR_LBPEGEN | CEC_CFGR_SFTOPT \
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99 | CEC_CFGR_BRDNOGEN | CEC_CFGR_OAR | CEC_CFGR_LSTN)
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104 /* Private macro -------------------------------------------------------------*/
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105 /* Private variables ---------------------------------------------------------*/
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106 /* Private function prototypes -----------------------------------------------*/
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107 /** @defgroup CEC_Private_Functions CEC Private Functions
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110 static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec);
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111 static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec);
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116 /* Exported functions ---------------------------------------------------------*/
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118 /** @defgroup CEC_Exported_Functions CEC Exported Functions
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122 /** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
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123 * @brief Initialization and Configuration functions
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126 ===============================================================================
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127 ##### Initialization and Configuration functions #####
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128 ===============================================================================
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130 This subsection provides a set of functions allowing to initialize the CEC
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131 (+) The following parameters need to be configured:
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132 (++) SignalFreeTime
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134 (++) BRERxStop (RX stopped or not upon Bit Rising Error)
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135 (++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error)
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136 (++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error)
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137 (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
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138 (++) SignalFreeTimeOption (SFT Timer start definition)
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139 (++) OwnAddress (CEC device address)
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147 * @brief Initializes the CEC mode according to the specified
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148 * parameters in the CEC_InitTypeDef and creates the associated handle .
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149 * @param hcec: CEC handle
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150 * @retval HAL status
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152 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
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154 uint32_t tmpreg = 0x0;
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156 /* Check the CEC handle allocation */
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162 /* Check the parameters */
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163 assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
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164 assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
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165 assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
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166 assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
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167 assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
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168 assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
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169 assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
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170 assert_param(IS_CEC_OAR_ADDRESS(hcec->Init.OwnAddress));
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171 assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
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172 assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress));
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175 if(hcec->State == HAL_CEC_STATE_RESET)
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177 /* Init the low level hardware : GPIO, CLOCK */
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178 HAL_CEC_MspInit(hcec);
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181 hcec->State = HAL_CEC_STATE_BUSY;
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183 /* Disable the Peripheral */
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184 __HAL_CEC_DISABLE(hcec);
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186 tmpreg = hcec->Init.SignalFreeTime;
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187 tmpreg |= hcec->Init.Tolerance;
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188 tmpreg |= hcec->Init.BRERxStop;
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189 tmpreg |= hcec->Init.BREErrorBitGen;
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190 tmpreg |= hcec->Init.LBPEErrorBitGen;
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191 tmpreg |= hcec->Init.BroadcastMsgNoErrorBitGen;
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192 tmpreg |= hcec->Init.SignalFreeTimeOption;
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193 tmpreg |= (hcec->Init.OwnAddress << CEC_CFGR_OAR_LSB_POS);
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194 tmpreg |= hcec->Init.ListenMode;
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196 /* Write to CEC Control Register */
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197 MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, tmpreg);
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199 /* Enable the Peripheral */
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200 __HAL_CEC_ENABLE(hcec);
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202 hcec->State = HAL_CEC_STATE_READY;
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208 * @brief DeInitializes the CEC peripheral
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209 * @param hcec: CEC handle
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210 * @retval HAL status
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212 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
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214 /* Check the CEC handle allocation */
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220 /* Check the parameters */
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221 assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
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223 hcec->State = HAL_CEC_STATE_BUSY;
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225 /* DeInit the low level hardware */
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226 HAL_CEC_MspDeInit(hcec);
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227 /* Disable the Peripheral */
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228 __HAL_CEC_DISABLE(hcec);
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230 hcec->ErrorCode = HAL_CEC_ERROR_NONE;
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231 hcec->State = HAL_CEC_STATE_RESET;
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233 /* Process Unlock */
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234 __HAL_UNLOCK(hcec);
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240 * @brief CEC MSP Init
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241 * @param hcec: CEC handle
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244 __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
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246 /* NOTE : This function should not be modified, when the callback is needed,
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247 the HAL_CEC_MspInit can be implemented in the user file
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252 * @brief CEC MSP DeInit
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253 * @param hcec: CEC handle
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256 __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
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258 /* NOTE : This function should not be modified, when the callback is needed,
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259 the HAL_CEC_MspDeInit can be implemented in the user file
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267 /** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
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268 * @brief CEC Transmit/Receive functions
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271 ===============================================================================
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272 ##### I/O operation functions #####
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273 ===============================================================================
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274 This subsection provides a set of functions allowing to manage the CEC data transfers.
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276 (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
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277 logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
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279 (#) There are two mode of transfer:
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280 (+) Blocking mode: The communication is performed in polling mode.
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281 The HAL status of all data processing is returned by the same function
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282 after finishing transfer.
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283 (+) No-Blocking mode: The communication is performed using Interrupts.
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284 These API's return the HAL status.
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285 The end of the data processing will be indicated through the
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286 dedicated CEC IRQ when using Interrupt mode.
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287 The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
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288 will be executed respectivelly at the end of the transmit or Receive process
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289 The HAL_CEC_ErrorCallback()user callback will be executed when a communication
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292 (#) Blocking mode API's are :
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293 (+) HAL_CEC_Transmit()
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294 (+) HAL_CEC_Receive()
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296 (#) Non-Blocking mode API's with Interrupt are :
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297 (+) HAL_CEC_Transmit_IT()
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298 (+) HAL_CEC_Receive_IT()
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299 (+) HAL_CEC_IRQHandler()
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301 (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
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302 (+) HAL_CEC_TxCpltCallback()
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303 (+) HAL_CEC_RxCpltCallback()
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304 (+) HAL_CEC_ErrorCallback()
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311 * @brief Send data in blocking mode
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312 * @param hcec: CEC handle
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313 * @param DestinationAddress: destination logical address
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314 * @param pData: pointer to input byte data buffer
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315 * @param Size: amount of data to be sent in bytes (without counting the header).
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316 * 0 means only the header is sent (ping operation).
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317 * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
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318 * @param Timeout: Timeout duration.
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319 * @retval HAL status
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321 HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout)
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324 uint32_t tempisr = 0;
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325 uint32_t tickstart = 0;
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327 if((hcec->State == HAL_CEC_STATE_READY) && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
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329 hcec->ErrorCode = HAL_CEC_ERROR_NONE;
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330 if((pData == NULL ) && (Size > 0))
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332 hcec->State = HAL_CEC_STATE_ERROR;
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336 assert_param(IS_CEC_ADDRESS(DestinationAddress));
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337 assert_param(IS_CEC_MSGSIZE(Size));
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339 /* Process Locked */
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342 hcec->State = HAL_CEC_STATE_BUSY_TX;
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344 hcec->TxXferCount = Size;
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346 /* case no data to be sent, sender is only pinging the system */
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349 /* Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
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350 __HAL_CEC_LAST_BYTE_TX_SET(hcec);
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353 /* send header block */
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354 temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;
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355 hcec->Instance->TXDR = temp;
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356 /* Set TX Start of Message (TXSOM) bit */
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357 __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
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359 while (hcec->TxXferCount > 0)
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361 hcec->TxXferCount--;
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363 tickstart = HAL_GetTick();
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364 while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_TXBR))
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366 if(Timeout != HAL_MAX_DELAY)
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368 if((HAL_GetTick() - tickstart) > Timeout)
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370 hcec->State = HAL_CEC_STATE_TIMEOUT;
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371 /* Process Unlocked */
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372 __HAL_UNLOCK(hcec);
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373 return HAL_TIMEOUT;
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377 /* check whether error occured while waiting for TXBR to be set:
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378 * has Tx underrun occurred ?
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379 * has Tx error occurred ?
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380 * has Tx Missing Acknowledge error occurred ?
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381 * has Arbitration Loss error occurred ? */
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382 tempisr = hcec->Instance->ISR;
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383 if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0)
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385 /* copy ISR for error handling purposes */
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386 hcec->ErrorCode = tempisr;
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387 /* clear all error flags by default */
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388 __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
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389 hcec->State = HAL_CEC_STATE_ERROR;
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390 __HAL_UNLOCK(hcec);
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394 /* TXBR to clear BEFORE writing TXDR register */
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395 __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
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396 if (hcec->TxXferCount == 0)
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398 /* if last byte transmission, set TX End of Message (TXEOM) bit */
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399 __HAL_CEC_LAST_BYTE_TX_SET(hcec);
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401 hcec->Instance->TXDR = *pData++;
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403 /* error check after TX byte write up */
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404 tempisr = hcec->Instance->ISR;
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405 if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0)
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407 /* copy ISR for error handling purposes */
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408 hcec->ErrorCode = tempisr;
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409 /* clear all error flags by default */
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410 __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
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411 hcec->State = HAL_CEC_STATE_ERROR;
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412 __HAL_UNLOCK(hcec);
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415 } /* end while (while (hcec->TxXferCount > 0)) */
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418 /* if no error up to this point, check that transmission is
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419 * complete, that is wait until TXEOM is reset */
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420 tickstart = HAL_GetTick();
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422 while (HAL_IS_BIT_SET(hcec->Instance->CR, CEC_CR_TXEOM))
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424 if(Timeout != HAL_MAX_DELAY)
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426 if((HAL_GetTick() - tickstart) > Timeout)
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428 hcec->State = HAL_CEC_STATE_ERROR;
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429 __HAL_UNLOCK(hcec);
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430 return HAL_TIMEOUT;
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435 /* Final error check once all bytes have been transmitted */
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436 tempisr = hcec->Instance->ISR;
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437 if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)) != 0)
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439 /* copy ISR for error handling purposes */
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440 hcec->ErrorCode = tempisr;
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441 /* clear all error flags by default */
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442 __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE));
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443 hcec->State = HAL_CEC_STATE_ERROR;
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444 __HAL_UNLOCK(hcec);
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448 hcec->State = HAL_CEC_STATE_READY;
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449 __HAL_UNLOCK(hcec);
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460 * @brief Receive data in blocking mode. Must be invoked when RXBR has been set.
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461 * @param hcec: CEC handle
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462 * @param pData: pointer to received data buffer.
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463 * @param Timeout: Timeout duration.
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464 * Note that the received data size is not known beforehand, the latter is known
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465 * when the reception is complete and is stored in hcec->RxXferSize.
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466 * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
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467 * If only a header is received, hcec->RxXferSize = 0
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468 * @retval HAL status
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470 HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout)
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473 uint32_t tickstart = 0;
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475 if (hcec->State == HAL_CEC_STATE_READY)
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477 hcec->ErrorCode = HAL_CEC_ERROR_NONE;
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478 if (pData == NULL )
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480 hcec->State = HAL_CEC_STATE_ERROR;
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484 hcec->RxXferSize = 0;
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485 /* Process Locked */
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489 /* Rx loop until CEC_ISR_RXEND is set */
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490 while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND))
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492 tickstart = HAL_GetTick();
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493 /* Wait for next byte to be received */
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494 while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR))
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496 if(Timeout != HAL_MAX_DELAY)
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498 if((HAL_GetTick() - tickstart) > Timeout)
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500 hcec->State = HAL_CEC_STATE_TIMEOUT;
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501 __HAL_UNLOCK(hcec);
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502 return HAL_TIMEOUT;
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505 /* any error so far ?
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506 * has Rx Missing Acknowledge occurred ?
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507 * has Rx Long Bit Period error occurred ?
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508 * has Rx Short Bit Period error occurred ?
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509 * has Rx Bit Rising error occurred ?
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510 * has Rx Overrun error occurred ? */
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511 temp = (uint32_t) (hcec->Instance->ISR);
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512 if ((temp & (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)) != 0)
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514 /* copy ISR for error handling purposes */
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515 hcec->ErrorCode = temp;
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516 /* clear all error flags by default */
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517 __HAL_CEC_CLEAR_FLAG(hcec,(CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR));
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518 hcec->State = HAL_CEC_STATE_ERROR;
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519 __HAL_UNLOCK(hcec);
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522 } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXBR)) */
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525 /* read received data */
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526 *pData++ = hcec->Instance->RXDR;
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527 temp = (uint32_t) (hcec->Instance->ISR);
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528 /* end of message ? */
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529 if ((temp & CEC_ISR_RXEND) != 0)
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531 assert_param(IS_CEC_MSGSIZE(hcec->RxXferSize));
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532 __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND);
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533 hcec->State = HAL_CEC_STATE_READY;
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534 __HAL_UNLOCK(hcec);
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538 /* clear Rx-Byte Received flag */
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539 __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR);
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540 /* increment payload byte counter */
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541 hcec->RxXferSize++;
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542 } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND)) */
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544 /* if the instructions below are executed, it means RXEND was set when RXBR was
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545 * set for the first time:
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546 * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND))"
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547 * loop has not been executed and this means a single byte has been sent */
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548 *pData++ = hcec->Instance->RXDR;
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549 /* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */
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550 hcec->RxXferSize = 0;
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551 __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
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553 hcec->State = HAL_CEC_STATE_READY;
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554 __HAL_UNLOCK(hcec);
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564 * @brief Send data in interrupt mode
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565 * @param hcec: CEC handle
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566 * @param DestinationAddress: destination logical address
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567 * @param pData: pointer to input byte data buffer
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568 * @param Size: amount of data to be sent in bytes (without counting the header).
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569 * 0 means only the header is sent (ping operation).
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570 * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
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571 * @retval HAL status
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573 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
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576 /* if the IP isn't already busy and if there is no previous transmission
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577 already pending due to arbitration lost */
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578 if (((hcec->State == HAL_CEC_STATE_READY) || (hcec->State == HAL_CEC_STATE_STANDBY_RX))
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579 && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
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581 if((pData == NULL ) && (Size > 0))
\r
583 hcec->State = HAL_CEC_STATE_ERROR;
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587 assert_param(IS_CEC_ADDRESS(DestinationAddress));
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588 assert_param(IS_CEC_MSGSIZE(Size));
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590 /* Process Locked */
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592 hcec->pTxBuffPtr = pData;
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593 hcec->State = HAL_CEC_STATE_BUSY_TX;
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594 hcec->ErrorCode = HAL_CEC_ERROR_NONE;
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596 /* Disable Peripheral to write CEC_IER register */
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597 __HAL_CEC_DISABLE(hcec);
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599 /* Enable the following two CEC Transmission interrupts as
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600 * well as the following CEC Transmission Errors interrupts:
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601 * Tx Byte Request IT
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602 * End of Transmission IT
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603 * Tx Missing Acknowledge IT
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605 * Tx-Buffer Underrun IT
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606 * Tx arbitration lost */
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607 __HAL_CEC_ENABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
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609 /* Enable the Peripheral */
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610 __HAL_CEC_ENABLE(hcec);
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612 /* initialize the number of bytes to send,
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613 * 0 means only one header is sent (ping operation) */
\r
614 hcec->TxXferCount = Size;
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616 /* Process Unlocked */
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617 __HAL_UNLOCK(hcec);
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619 /* in case of no payload (Size = 0), sender is only pinging the system;
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620 * Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
\r
623 __HAL_CEC_LAST_BYTE_TX_SET(hcec);
\r
626 /* send header block */
\r
627 temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;
\r
628 hcec->Instance->TXDR = temp;
\r
629 /* Set TX Start of Message (TXSOM) bit */
\r
630 __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
\r
634 /* if the IP is already busy or if there is a previous transmission
\r
635 already pending due to arbitration loss */
\r
636 else if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
\r
637 || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
\r
640 /* set state to BUSY TX, in case it wasn't set already (case
\r
641 * of transmission new attempt after arbitration loss) */
\r
642 if (hcec->State != HAL_CEC_STATE_BUSY_TX)
\r
644 hcec->State = HAL_CEC_STATE_BUSY_TX;
\r
647 /* if all data have been sent */
\r
648 if(hcec->TxXferCount == 0)
\r
650 /* Disable Peripheral to write CEC_IER register */
\r
651 __HAL_CEC_DISABLE(hcec);
\r
653 /* Disable the CEC Transmission Interrupts */
\r
654 __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
\r
655 /* Disable the CEC Transmission Error Interrupts */
\r
656 __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
\r
658 /* Enable the Peripheral */
\r
659 __HAL_CEC_ENABLE(hcec);
\r
661 __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR|CEC_FLAG_TXEND);
\r
663 hcec->State = HAL_CEC_STATE_READY;
\r
664 /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
\r
665 start again the Transmission under the Tx call back API */
\r
666 __HAL_UNLOCK(hcec);
\r
668 HAL_CEC_TxCpltCallback(hcec);
\r
674 if (hcec->TxXferCount == 1)
\r
676 /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
\r
677 __HAL_CEC_LAST_BYTE_TX_SET(hcec);
\r
679 /* clear Tx-Byte request flag */
\r
680 __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
\r
681 hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
\r
682 hcec->TxXferCount--;
\r
684 /* Process Unlocked */
\r
685 __HAL_UNLOCK(hcec);
\r
697 * @brief Receive data in interrupt mode.
\r
698 * @param hcec: CEC handle
\r
699 * @param pData: pointer to received data buffer.
\r
700 * Note that the received data size is not known beforehand, the latter is known
\r
701 * when the reception is complete and is stored in hcec->RxXferSize.
\r
702 * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
\r
703 * If only a header is received, hcec->RxXferSize = 0
\r
704 * @retval HAL status
\r
706 HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData)
\r
708 if(hcec->State == HAL_CEC_STATE_READY)
\r
710 if(pData == NULL )
\r
712 hcec->State = HAL_CEC_STATE_ERROR;
\r
716 /* Process Locked */
\r
718 hcec->RxXferSize = 0;
\r
719 hcec->pRxBuffPtr = pData;
\r
720 hcec->ErrorCode = HAL_CEC_ERROR_NONE;
\r
721 /* the IP is moving to a ready to receive state */
\r
722 hcec->State = HAL_CEC_STATE_STANDBY_RX;
\r
724 /* Disable Peripheral to write CEC_IER register */
\r
725 __HAL_CEC_DISABLE(hcec);
\r
727 /* Enable the following CEC Reception Error Interrupts:
\r
729 * Rx bit rising error
\r
730 * Rx short bit period error
\r
731 * Rx long bit period error
\r
732 * Rx missing acknowledge */
\r
733 __HAL_CEC_ENABLE_IT(hcec, CEC_IER_RX_ALL_ERR);
\r
735 /* Process Unlocked */
\r
736 __HAL_UNLOCK(hcec);
\r
738 /* Enable the following two CEC Reception interrupts:
\r
739 * Rx Byte Received IT
\r
740 * End of Reception IT */
\r
741 __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND);
\r
743 __HAL_CEC_ENABLE(hcec);
\r
754 * @brief Get size of the received frame.
\r
755 * @param hcec: CEC handle
\r
756 * @retval Frame size
\r
758 uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec)
\r
760 return hcec->RxXferSize;
\r
764 * @brief This function handles CEC interrupt requests.
\r
765 * @param hcec: CEC handle
\r
768 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
\r
770 /* save interrupts register for further error or interrupts handling purposes */
\r
771 hcec->ErrorCode = hcec->Instance->ISR;
\r
772 /* CEC TX missing acknowledge error interrupt occurred -------------------------------------*/
\r
773 if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXACKE) != RESET))
\r
775 __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXACKE);
\r
776 hcec->State = HAL_CEC_STATE_ERROR;
\r
779 /* CEC transmit error interrupt occured --------------------------------------*/
\r
780 if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXERR) != RESET))
\r
782 __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXERR);
\r
783 hcec->State = HAL_CEC_STATE_ERROR;
\r
786 /* CEC TX underrun error interrupt occured --------------------------------------*/
\r
787 if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXUDR) != RESET))
\r
789 __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXUDR);
\r
790 hcec->State = HAL_CEC_STATE_ERROR;
\r
793 /* CEC TX arbitration error interrupt occured --------------------------------------*/
\r
794 if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_ARBLST) != RESET))
\r
796 __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
\r
797 hcec->State = HAL_CEC_STATE_ERROR;
\r
800 /* CEC RX overrun error interrupt occured --------------------------------------*/
\r
801 if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXOVR) != RESET))
\r
803 __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXOVR);
\r
804 hcec->State = HAL_CEC_STATE_ERROR;
\r
807 /* CEC RX bit rising error interrupt occured --------------------------------------*/
\r
808 if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_BRE) != RESET))
\r
810 __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_BRE);
\r
811 hcec->State = HAL_CEC_STATE_ERROR;
\r
814 /* CEC RX short bit period error interrupt occured --------------------------------------*/
\r
815 if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_SBPE) != RESET))
\r
817 __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_SBPE);
\r
818 hcec->State = HAL_CEC_STATE_ERROR;
\r
821 /* CEC RX long bit period error interrupt occured --------------------------------------*/
\r
822 if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_LBPE) != RESET))
\r
824 __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_LBPE);
\r
825 hcec->State = HAL_CEC_STATE_ERROR;
\r
828 /* CEC RX missing acknowledge error interrupt occured --------------------------------------*/
\r
829 if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXACKE) != RESET))
\r
831 __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXACKE);
\r
832 hcec->State = HAL_CEC_STATE_ERROR;
\r
835 if ((hcec->ErrorCode & CEC_ISR_ALL_ERROR) != 0)
\r
837 HAL_CEC_ErrorCallback(hcec);
\r
840 /* CEC RX byte received interrupt ---------------------------------------------------*/
\r
841 if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXBR) != RESET))
\r
843 /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
\r
844 CEC_Receive_IT(hcec);
\r
847 /* CEC RX end received interrupt ---------------------------------------------------*/
\r
848 if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXEND) != RESET))
\r
850 /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
\r
851 CEC_Receive_IT(hcec);
\r
855 /* CEC TX byte request interrupt ------------------------------------------------*/
\r
856 if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXBR) != RESET))
\r
858 /* TXBR IT is cleared during HAL_CEC_Transmit_IT processing */
\r
859 CEC_Transmit_IT(hcec);
\r
862 /* CEC TX end interrupt ------------------------------------------------*/
\r
863 if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXEND) != RESET))
\r
865 /* TXEND IT is cleared during HAL_CEC_Transmit_IT processing */
\r
866 CEC_Transmit_IT(hcec);
\r
871 * @brief Tx Transfer completed callback
\r
872 * @param hcec: CEC handle
\r
875 __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
\r
877 /* NOTE : This function should not be modified, when the callback is needed,
\r
878 the HAL_CEC_TxCpltCallback can be implemented in the user file
\r
883 * @brief Rx Transfer completed callback
\r
884 * @param hcec: CEC handle
\r
887 __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec)
\r
889 /* NOTE : This function should not be modified, when the callback is needed,
\r
890 the HAL_CEC_TxCpltCallback can be implemented in the user file
\r
895 * @brief CEC error callbacks
\r
896 * @param hcec: CEC handle
\r
899 __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
\r
901 /* NOTE : This function should not be modified, when the callback is needed,
\r
902 the HAL_CEC_ErrorCallback can be implemented in the user file
\r
909 /** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
\r
910 * @brief CEC control functions
\r
913 ===============================================================================
\r
914 ##### Peripheral Control function #####
\r
915 ===============================================================================
\r
917 This subsection provides a set of functions allowing to control the CEC.
\r
918 (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
\r
923 * @brief return the CEC state
\r
924 * @param hcec: CEC handle
\r
925 * @retval HAL state
\r
927 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
\r
929 return hcec->State;
\r
933 * @brief Return the CEC error code
\r
934 * @param hcec : pointer to a CEC_HandleTypeDef structure that contains
\r
935 * the configuration information for the specified CEC.
\r
936 * @retval CEC Error Code
\r
938 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
\r
940 return hcec->ErrorCode;
\r
948 * @brief Send data in interrupt mode
\r
949 * @param hcec: CEC handle.
\r
950 * Function called under interruption only, once
\r
951 * interruptions have been enabled by HAL_CEC_Transmit_IT()
\r
952 * @retval HAL status
\r
954 static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
\r
956 /* if the IP is already busy or if there is a previous transmission
\r
957 already pending due to arbitration loss */
\r
958 if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
\r
959 || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
\r
962 /* set state to BUSY TX, in case it wasn't set already (case
\r
963 * of transmission new attempt after arbitration loss) */
\r
964 if (hcec->State != HAL_CEC_STATE_BUSY_TX)
\r
966 hcec->State = HAL_CEC_STATE_BUSY_TX;
\r
969 /* if all data have been sent */
\r
970 if(hcec->TxXferCount == 0)
\r
972 /* Disable Peripheral to write CEC_IER register */
\r
973 __HAL_CEC_DISABLE(hcec);
\r
975 /* Disable the CEC Transmission Interrupts */
\r
976 __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
\r
977 /* Disable the CEC Transmission Error Interrupts */
\r
978 __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
\r
980 /* Enable the Peripheral */
\r
981 __HAL_CEC_ENABLE(hcec);
\r
983 __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND);
\r
985 hcec->State = HAL_CEC_STATE_READY;
\r
986 /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
\r
987 start again the Transmission under the Tx call back API */
\r
988 __HAL_UNLOCK(hcec);
\r
990 HAL_CEC_TxCpltCallback(hcec);
\r
996 if (hcec->TxXferCount == 1)
\r
998 /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
\r
999 __HAL_CEC_LAST_BYTE_TX_SET(hcec);
\r
1001 /* clear Tx-Byte request flag */
\r
1002 __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
\r
1003 hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
\r
1004 hcec->TxXferCount--;
\r
1006 /* Process Unlocked */
\r
1007 __HAL_UNLOCK(hcec);
\r
1020 * @brief Receive data in interrupt mode.
\r
1021 * @param hcec: CEC handle.
\r
1022 * Function called under interruption only, once
\r
1023 * interruptions have been enabled by HAL_CEC_Receive_IT()
\r
1024 * @retval HAL status
\r
1026 static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec)
\r
1030 /* Three different conditions are tested to carry out the RX IT processing:
\r
1031 * - the IP is in reception stand-by (the IP state is HAL_CEC_STATE_STANDBY_RX) and
\r
1032 * the reception of the first byte is starting
\r
1033 * - a message reception is already on-going (the IP state is HAL_CEC_STATE_BUSY_RX)
\r
1034 * and a new byte is being received
\r
1035 * - a transmission has just been started (the IP state is HAL_CEC_STATE_BUSY_TX)
\r
1036 * but has been interrupted by a new message reception or discarded due to
\r
1037 * arbitration loss: the reception of the first or higher priority message
\r
1038 * (the arbitration winner) is starting */
\r
1039 if ((hcec->State == HAL_CEC_STATE_STANDBY_RX)
\r
1040 || (hcec->State == HAL_CEC_STATE_BUSY_RX)
\r
1041 || (hcec->State == HAL_CEC_STATE_BUSY_TX))
\r
1043 /* reception is starting */
\r
1044 hcec->State = HAL_CEC_STATE_BUSY_RX;
\r
1045 tempisr = (uint32_t) (hcec->Instance->ISR);
\r
1046 if ((tempisr & CEC_FLAG_RXBR) != 0)
\r
1048 /* Process Locked */
\r
1050 /* read received byte */
\r
1051 *hcec->pRxBuffPtr++ = hcec->Instance->RXDR;
\r
1052 /* if last byte has been received */
\r
1053 if ((tempisr & CEC_FLAG_RXEND) != 0)
\r
1056 __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR|CEC_FLAG_RXEND);
\r
1057 /* RX interrupts are not disabled at this point.
\r
1058 * Indeed, to disable the IT, the IP must be disabled first
\r
1059 * which resets the TXSOM flag. In case of arbitration loss,
\r
1060 * this leads to a transmission abort.
\r
1061 * Therefore, RX interruptions disabling if so required,
\r
1062 * is done in HAL_CEC_RxCpltCallback */
\r
1064 /* IP state is moved to READY.
\r
1065 * If the IP must remain in standby mode to listen
\r
1066 * any new message, it is up to HAL_CEC_RxCpltCallback
\r
1067 * to move it again to HAL_CEC_STATE_STANDBY_RX */
\r
1068 hcec->State = HAL_CEC_STATE_READY;
\r
1070 /* Call the Process Unlocked before calling the Rx call back API */
\r
1071 __HAL_UNLOCK(hcec);
\r
1072 HAL_CEC_RxCpltCallback(hcec);
\r
1076 __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
\r
1078 hcec->RxXferSize++;
\r
1079 /* Process Unlocked */
\r
1080 __HAL_UNLOCK(hcec);
\r
1097 #endif /* HAL_CEC_MODULE_ENABLED */
\r
1106 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r