2 ******************************************************************************
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3 * @file stm32f7xx_hal_cortex.c
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4 * @author MCD Application Team
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6 * @date 24-March-2015
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7 * @brief CORTEX HAL module driver.
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8 * This file provides firmware functions to manage the following
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9 * functionalities of the CORTEX:
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10 * + Initialization and de-initialization functions
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11 * + Peripheral Control functions
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14 ==============================================================================
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15 ##### How to use this driver #####
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16 ==============================================================================
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19 *** How to configure Interrupts using CORTEX HAL driver ***
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20 ===========================================================
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22 This section provides functions allowing to configure the NVIC interrupts (IRQ).
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23 The Cortex-M4 exceptions are managed by CMSIS functions.
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25 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
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26 function according to the following table.
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27 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
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28 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
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29 (#) please refer to programing manual for details in how to configure priority.
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31 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
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32 The pending IRQ priority will be managed only by the sub priority.
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34 -@- IRQ priority order (sorted by highest to lowest priority):
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35 (+@) Lowest preemption priority
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36 (+@) Lowest sub priority
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37 (+@) Lowest hardware priority (IRQ number)
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40 *** How to configure Systick using CORTEX HAL driver ***
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41 ========================================================
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43 Setup SysTick Timer for time base.
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45 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
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46 is a CMSIS function that:
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47 (++) Configures the SysTick Reload register with value passed as function parameter.
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48 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
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49 (++) Resets the SysTick Counter register.
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50 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
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51 (++) Enables the SysTick Interrupt.
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52 (++) Starts the SysTick Counter.
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54 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
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55 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
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56 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
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57 inside the stm32f7xx_hal_cortex.h file.
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59 (+) You can change the SysTick IRQ priority by calling the
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60 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
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61 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
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63 (+) To adjust the SysTick time base, use the following formula:
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65 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
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66 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
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67 (++) Reload Value should not exceed 0xFFFFFF
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70 ******************************************************************************
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73 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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75 * Redistribution and use in source and binary forms, with or without modification,
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76 * are permitted provided that the following conditions are met:
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77 * 1. Redistributions of source code must retain the above copyright notice,
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78 * this list of conditions and the following disclaimer.
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79 * 2. Redistributions in binary form must reproduce the above copyright notice,
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80 * this list of conditions and the following disclaimer in the documentation
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81 * and/or other materials provided with the distribution.
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82 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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83 * may be used to endorse or promote products derived from this software
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84 * without specific prior written permission.
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86 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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87 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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88 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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89 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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90 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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91 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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92 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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93 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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94 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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95 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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97 ******************************************************************************
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100 /* Includes ------------------------------------------------------------------*/
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101 #include "stm32f7xx_hal.h"
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103 /** @addtogroup STM32F7xx_HAL_Driver
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107 /** @defgroup CORTEX CORTEX
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108 * @brief CORTEX HAL module driver
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112 #ifdef HAL_CORTEX_MODULE_ENABLED
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114 /* Private types -------------------------------------------------------------*/
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115 /* Private variables ---------------------------------------------------------*/
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116 /* Private constants ---------------------------------------------------------*/
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117 /* Private macros ------------------------------------------------------------*/
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118 /* Private functions ---------------------------------------------------------*/
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119 /* Exported functions --------------------------------------------------------*/
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121 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
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126 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
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127 * @brief Initialization and Configuration functions
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130 ==============================================================================
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131 ##### Initialization and de-initialization functions #####
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132 ==============================================================================
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134 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
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135 Systick functionalities
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143 * @brief Sets the priority grouping field (preemption priority and subpriority)
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144 * using the required unlock sequence.
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145 * @param PriorityGroup: The priority grouping bits length.
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146 * This parameter can be one of the following values:
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147 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
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148 * 4 bits for subpriority
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149 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
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150 * 3 bits for subpriority
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151 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
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152 * 2 bits for subpriority
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153 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
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154 * 1 bits for subpriority
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155 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
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156 * 0 bits for subpriority
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157 * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
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158 * The pending IRQ priority will be managed only by the subpriority.
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161 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
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163 /* Check the parameters */
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164 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
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166 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
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167 NVIC_SetPriorityGrouping(PriorityGroup);
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171 * @brief Sets the priority of an interrupt.
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172 * @param IRQn: External interrupt number.
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173 * This parameter can be an enumerator of IRQn_Type enumeration
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174 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
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175 * @param PreemptPriority: The preemption priority for the IRQn channel.
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176 * This parameter can be a value between 0 and 15
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177 * A lower priority value indicates a higher priority
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178 * @param SubPriority: the subpriority level for the IRQ channel.
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179 * This parameter can be a value between 0 and 15
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180 * A lower priority value indicates a higher priority.
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183 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
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185 uint32_t prioritygroup = 0x00;
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187 /* Check the parameters */
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188 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
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189 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
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191 prioritygroup = NVIC_GetPriorityGrouping();
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193 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
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197 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
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198 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
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199 * function should be called before.
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200 * @param IRQn External interrupt number.
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201 * This parameter can be an enumerator of IRQn_Type enumeration
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202 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
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205 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
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207 /* Check the parameters */
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208 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
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210 /* Enable interrupt */
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211 NVIC_EnableIRQ(IRQn);
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215 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
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216 * @param IRQn External interrupt number.
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217 * This parameter can be an enumerator of IRQn_Type enumeration
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218 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
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221 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
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223 /* Check the parameters */
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224 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
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226 /* Disable interrupt */
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227 NVIC_DisableIRQ(IRQn);
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231 * @brief Initiates a system reset request to reset the MCU.
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234 void HAL_NVIC_SystemReset(void)
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237 NVIC_SystemReset();
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241 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
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242 * Counter is in free running mode to generate periodic interrupts.
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243 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
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244 * @retval status: - 0 Function succeeded.
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245 * - 1 Function failed.
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247 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
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249 return SysTick_Config(TicksNumb);
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255 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
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256 * @brief Cortex control functions
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259 ==============================================================================
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260 ##### Peripheral Control functions #####
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261 ==============================================================================
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263 This subsection provides a set of functions allowing to control the CORTEX
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264 (NVIC, SYSTICK, MPU) functionalities.
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271 #if (__MPU_PRESENT == 1)
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273 * @brief Initializes and configures the Region and the memory to be protected.
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274 * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
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275 * the initialization and configuration information.
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278 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
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280 /* Check the parameters */
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281 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
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282 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
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284 /* Set the Region number */
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285 MPU->RNR = MPU_Init->Number;
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287 if ((MPU_Init->Enable) != RESET)
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289 /* Check the parameters */
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290 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
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291 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
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292 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
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293 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
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294 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
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295 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
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296 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
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297 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
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299 MPU->RBAR = MPU_Init->BaseAddress;
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300 MPU->RASR = (MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
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301 (MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
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302 (MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
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303 (MPU_Init->IsShareable << MPU_RASR_S_Pos) |
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304 (MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
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305 (MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
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306 (MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
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307 (MPU_Init->Size << MPU_RASR_SIZE_Pos) |
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308 (MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
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316 #endif /* __MPU_PRESENT */
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319 * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
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320 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
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322 uint32_t HAL_NVIC_GetPriorityGrouping(void)
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324 /* Get the PRIGROUP[10:8] field value */
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325 return NVIC_GetPriorityGrouping();
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329 * @brief Gets the priority of an interrupt.
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330 * @param IRQn: External interrupt number.
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331 * This parameter can be an enumerator of IRQn_Type enumeration
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332 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
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333 * @param PriorityGroup: the priority grouping bits length.
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334 * This parameter can be one of the following values:
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335 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
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336 * 4 bits for subpriority
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337 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
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338 * 3 bits for subpriority
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339 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
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340 * 2 bits for subpriority
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341 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
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342 * 1 bits for subpriority
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343 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
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344 * 0 bits for subpriority
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345 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
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346 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
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349 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
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351 /* Check the parameters */
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352 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
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353 /* Get priority for Cortex-M system or device specific interrupts */
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354 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
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358 * @brief Sets Pending bit of an external interrupt.
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359 * @param IRQn External interrupt number
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360 * This parameter can be an enumerator of IRQn_Type enumeration
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361 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
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364 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
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366 /* Check the parameters */
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367 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
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369 /* Set interrupt pending */
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370 NVIC_SetPendingIRQ(IRQn);
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374 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
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375 * and returns the pending bit for the specified interrupt).
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376 * @param IRQn External interrupt number.
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377 * This parameter can be an enumerator of IRQn_Type enumeration
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378 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
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379 * @retval status: - 0 Interrupt status is not pending.
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380 * - 1 Interrupt status is pending.
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382 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
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384 /* Check the parameters */
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385 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
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387 /* Return 1 if pending else 0 */
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388 return NVIC_GetPendingIRQ(IRQn);
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392 * @brief Clears the pending bit of an external interrupt.
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393 * @param IRQn External interrupt number.
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394 * This parameter can be an enumerator of IRQn_Type enumeration
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395 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
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398 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
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400 /* Check the parameters */
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401 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
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403 /* Clear pending interrupt */
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404 NVIC_ClearPendingIRQ(IRQn);
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408 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
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409 * @param IRQn External interrupt number
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410 * This parameter can be an enumerator of IRQn_Type enumeration
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411 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
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412 * @retval status: - 0 Interrupt status is not pending.
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413 * - 1 Interrupt status is pending.
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415 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
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417 /* Check the parameters */
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418 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
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420 /* Return 1 if active else 0 */
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421 return NVIC_GetActive(IRQn);
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425 * @brief Configures the SysTick clock source.
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426 * @param CLKSource: specifies the SysTick clock source.
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427 * This parameter can be one of the following values:
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428 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
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429 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
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432 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
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434 /* Check the parameters */
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435 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
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436 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
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438 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
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442 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
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447 * @brief This function handles SYSTICK interrupt request.
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450 void HAL_SYSTICK_IRQHandler(void)
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452 HAL_SYSTICK_Callback();
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456 * @brief SYSTICK callback.
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459 __weak void HAL_SYSTICK_Callback(void)
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461 /* NOTE : This function Should not be modified, when the callback is needed,
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462 the HAL_SYSTICK_Callback could be implemented in the user file
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474 #endif /* HAL_CORTEX_MODULE_ENABLED */
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483 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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