2 ******************************************************************************
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3 * @file stm32f7xx_hal_eth.c
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4 * @author MCD Application Team
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6 * @date 24-March-2015
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7 * @brief ETH HAL module driver.
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8 * This file provides firmware functions to manage the following
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9 * functionalities of the Ethernet (ETH) peripheral:
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10 * + Initialization and de-initialization functions
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11 * + IO operation functions
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12 * + Peripheral Control functions
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13 * + Peripheral State and Errors functions
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16 ==============================================================================
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17 ##### How to use this driver #####
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18 ==============================================================================
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20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
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21 ETH_HandleTypeDef heth;
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23 (#)Fill parameters of Init structure in heth handle
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25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
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27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
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28 (##) Enable the Ethernet interface clock using
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29 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
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30 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
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31 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
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33 (##) Initialize the related GPIO clocks
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34 (##) Configure Ethernet pin-out
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35 (##) Configure Ethernet NVIC interrupt (IT mode)
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37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
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38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
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39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
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41 (#)Enable MAC and DMA transmission and reception:
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42 (##) HAL_ETH_Start();
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44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
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45 the frame to MAC TX FIFO:
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46 (##) HAL_ETH_TransmitFrame();
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48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
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50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
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52 (#) Get a received frame when an ETH RX interrupt occurs:
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53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
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55 (#) Communicate with external PHY device:
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56 (##) Read a specific register from the PHY
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57 HAL_ETH_ReadPHYRegister();
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58 (##) Write data to a specific RHY register:
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59 HAL_ETH_WritePHYRegister();
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61 (#) Configure the Ethernet MAC after ETH peripheral initialization
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62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
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64 (#) Configure the Ethernet DMA after ETH peripheral initialization
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65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
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68 ******************************************************************************
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71 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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73 * Redistribution and use in source and binary forms, with or without modification,
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74 * are permitted provided that the following conditions are met:
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75 * 1. Redistributions of source code must retain the above copyright notice,
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76 * this list of conditions and the following disclaimer.
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77 * 2. Redistributions in binary form must reproduce the above copyright notice,
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78 * this list of conditions and the following disclaimer in the documentation
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79 * and/or other materials provided with the distribution.
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80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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81 * may be used to endorse or promote products derived from this software
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82 * without specific prior written permission.
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84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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95 ******************************************************************************
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98 /* Includes ------------------------------------------------------------------*/
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99 #include "stm32f7xx_hal.h"
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101 /** @addtogroup STM32F7xx_HAL_Driver
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105 /** @defgroup ETH ETH
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106 * @brief ETH HAL module driver
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110 #ifdef HAL_ETH_MODULE_ENABLED
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112 /* Private typedef -----------------------------------------------------------*/
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113 /* Private define ------------------------------------------------------------*/
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114 /** @defgroup ETH_Private_Constants ETH Private Constants
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117 #define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
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118 #define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */
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123 /* Private macro -------------------------------------------------------------*/
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124 /* Private variables ---------------------------------------------------------*/
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125 /* Private function prototypes -----------------------------------------------*/
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126 /** @defgroup ETH_Private_Functions ETH Private Functions
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129 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
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130 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
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131 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
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132 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
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133 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
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134 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
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135 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
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136 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
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137 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
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138 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
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139 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
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144 /* Private functions ---------------------------------------------------------*/
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146 /** @defgroup ETH_Exported_Functions ETH Exported Functions
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150 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
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151 * @brief Initialization and Configuration functions
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154 ===============================================================================
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155 ##### Initialization and de-initialization functions #####
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156 ===============================================================================
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157 [..] This section provides functions allowing to:
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158 (+) Initialize and configure the Ethernet peripheral
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159 (+) De-initialize the Ethernet peripheral
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166 * @brief Initializes the Ethernet MAC and DMA according to default
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168 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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169 * the configuration information for ETHERNET module
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170 * @retval HAL status
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172 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
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174 uint32_t tempreg = 0, phyreg = 0;
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175 uint32_t hclk = 60000000;
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176 uint32_t tickstart = 0;
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177 uint32_t err = ETH_SUCCESS;
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179 /* Check the ETH peripheral state */
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185 /* Check parameters */
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186 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
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187 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
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188 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
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189 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
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191 if(heth->State == HAL_ETH_STATE_RESET)
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193 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
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194 HAL_ETH_MspInit(heth);
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197 /* Enable SYSCFG Clock */
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198 __HAL_RCC_SYSCFG_CLK_ENABLE();
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200 /* Select MII or RMII Mode*/
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201 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
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202 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
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204 /* Ethernet Software reset */
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205 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
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206 /* After reset all the registers holds their respective reset values */
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207 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
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209 /* Wait for software reset */
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210 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
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214 /*-------------------------------- MAC Initialization ----------------------*/
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215 /* Get the ETHERNET MACMIIAR value */
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216 tempreg = (heth->Instance)->MACMIIAR;
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217 /* Clear CSR Clock Range CR[2:0] bits */
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218 tempreg &= ETH_MACMIIAR_CR_MASK;
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220 /* Get hclk frequency value */
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221 hclk = HAL_RCC_GetHCLKFreq();
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223 /* Set CR bits depending on hclk value */
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224 if((hclk >= 20000000)&&(hclk < 35000000))
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226 /* CSR Clock Range between 20-35 MHz */
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227 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
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229 else if((hclk >= 35000000)&&(hclk < 60000000))
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231 /* CSR Clock Range between 35-60 MHz */
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232 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
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234 else if((hclk >= 60000000)&&(hclk < 100000000))
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236 /* CSR Clock Range between 60-100 MHz */
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237 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
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239 else if((hclk >= 100000000)&&(hclk < 150000000))
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241 /* CSR Clock Range between 100-150 MHz */
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242 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
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244 else /* ((hclk >= 150000000)&&(hclk <= 200000000)) */
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246 /* CSR Clock Range between 150-200 MHz */
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247 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
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250 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
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251 (heth->Instance)->MACMIIAR = (uint32_t)tempreg;
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253 /*-------------------- PHY initialization and configuration ----------------*/
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254 /* Put the PHY in reset mode */
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255 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
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257 /* In case of write timeout */
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260 /* Config MAC and DMA */
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261 ETH_MACDMAConfig(heth, err);
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263 /* Set the ETH peripheral state to READY */
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264 heth->State = HAL_ETH_STATE_READY;
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266 /* Return HAL_ERROR */
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270 /* Delay to assure PHY reset */
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271 HAL_Delay(PHY_RESET_DELAY);
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273 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
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276 tickstart = HAL_GetTick();
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278 /* We wait for linked status */
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281 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
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283 /* Check for the Timeout */
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284 if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
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286 /* In case of write timeout */
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289 /* Config MAC and DMA */
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290 ETH_MACDMAConfig(heth, err);
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292 heth->State= HAL_ETH_STATE_READY;
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294 /* Process Unlocked */
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295 __HAL_UNLOCK(heth);
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297 return HAL_TIMEOUT;
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299 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
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302 /* Enable Auto-Negotiation */
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303 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
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305 /* In case of write timeout */
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308 /* Config MAC and DMA */
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309 ETH_MACDMAConfig(heth, err);
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311 /* Set the ETH peripheral state to READY */
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312 heth->State = HAL_ETH_STATE_READY;
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314 /* Return HAL_ERROR */
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319 tickstart = HAL_GetTick();
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321 /* Wait until the auto-negotiation will be completed */
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324 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
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326 /* Check for the Timeout */
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327 if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
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329 /* In case of write timeout */
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332 /* Config MAC and DMA */
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333 ETH_MACDMAConfig(heth, err);
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335 heth->State= HAL_ETH_STATE_READY;
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337 /* Process Unlocked */
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338 __HAL_UNLOCK(heth);
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340 return HAL_TIMEOUT;
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343 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
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345 /* Read the result of the auto-negotiation */
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346 if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
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348 /* In case of write timeout */
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351 /* Config MAC and DMA */
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352 ETH_MACDMAConfig(heth, err);
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354 /* Set the ETH peripheral state to READY */
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355 heth->State = HAL_ETH_STATE_READY;
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357 /* Return HAL_ERROR */
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361 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
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362 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
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364 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
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365 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
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369 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
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370 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
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372 /* Configure the MAC with the speed fixed by the auto-negotiation process */
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373 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
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375 /* Set Ethernet speed to 10M following the auto-negotiation */
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376 (heth->Init).Speed = ETH_SPEED_10M;
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380 /* Set Ethernet speed to 100M following the auto-negotiation */
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381 (heth->Init).Speed = ETH_SPEED_100M;
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384 else /* AutoNegotiation Disable */
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386 /* Check parameters */
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387 assert_param(IS_ETH_SPEED(heth->Init.Speed));
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388 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
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390 /* Set MAC Speed and Duplex Mode */
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391 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
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392 (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
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394 /* In case of write timeout */
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397 /* Config MAC and DMA */
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398 ETH_MACDMAConfig(heth, err);
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400 /* Set the ETH peripheral state to READY */
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401 heth->State = HAL_ETH_STATE_READY;
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403 /* Return HAL_ERROR */
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407 /* Delay to assure PHY configuration */
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408 HAL_Delay(PHY_CONFIG_DELAY);
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411 /* Config MAC and DMA */
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412 ETH_MACDMAConfig(heth, err);
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414 /* Set ETH HAL State to Ready */
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415 heth->State= HAL_ETH_STATE_READY;
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417 /* Return function status */
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422 * @brief De-Initializes the ETH peripheral.
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423 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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424 * the configuration information for ETHERNET module
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425 * @retval HAL status
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427 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
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429 /* Set the ETH peripheral state to BUSY */
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430 heth->State = HAL_ETH_STATE_BUSY;
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432 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
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433 HAL_ETH_MspDeInit(heth);
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435 /* Set ETH HAL state to Disabled */
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436 heth->State= HAL_ETH_STATE_RESET;
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439 __HAL_UNLOCK(heth);
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441 /* Return function status */
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446 * @brief Initializes the DMA Tx descriptors in chain mode.
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447 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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448 * the configuration information for ETHERNET module
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449 * @param DMATxDescTab: Pointer to the first Tx desc list
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450 * @param TxBuff: Pointer to the first TxBuffer list
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451 * @param TxBuffCount: Number of the used Tx desc in the list
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452 * @retval HAL status
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454 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
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457 ETH_DMADescTypeDef *dmatxdesc;
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459 /* Process Locked */
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462 /* Set the ETH peripheral state to BUSY */
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463 heth->State = HAL_ETH_STATE_BUSY;
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465 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
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466 heth->TxDesc = DMATxDescTab;
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468 /* Fill each DMATxDesc descriptor with the right values */
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469 for(i=0; i < TxBuffCount; i++)
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471 /* Get the pointer on the ith member of the Tx Desc list */
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472 dmatxdesc = DMATxDescTab + i;
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474 /* Set Second Address Chained bit */
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475 dmatxdesc->Status = ETH_DMATXDESC_TCH;
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477 /* Set Buffer1 address pointer */
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478 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
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480 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
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482 /* Set the DMA Tx descriptors checksum insertion */
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483 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
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486 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
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487 if(i < (TxBuffCount-1))
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489 /* Set next descriptor address register with next descriptor base address */
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490 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
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494 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
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495 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
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499 /* Set Transmit Descriptor List Address Register */
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500 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
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502 /* Set ETH HAL State to Ready */
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503 heth->State= HAL_ETH_STATE_READY;
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505 /* Process Unlocked */
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506 __HAL_UNLOCK(heth);
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508 /* Return function status */
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513 * @brief Initializes the DMA Rx descriptors in chain mode.
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514 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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515 * the configuration information for ETHERNET module
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516 * @param DMARxDescTab: Pointer to the first Rx desc list
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517 * @param RxBuff: Pointer to the first RxBuffer list
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518 * @param RxBuffCount: Number of the used Rx desc in the list
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519 * @retval HAL status
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521 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
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524 ETH_DMADescTypeDef *DMARxDesc;
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526 /* Process Locked */
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529 /* Set the ETH peripheral state to BUSY */
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530 heth->State = HAL_ETH_STATE_BUSY;
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532 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
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533 heth->RxDesc = DMARxDescTab;
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535 /* Fill each DMARxDesc descriptor with the right values */
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536 for(i=0; i < RxBuffCount; i++)
\r
538 /* Get the pointer on the ith member of the Rx Desc list */
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539 DMARxDesc = DMARxDescTab+i;
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541 /* Set Own bit of the Rx descriptor Status */
\r
542 DMARxDesc->Status = ETH_DMARXDESC_OWN;
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544 /* Set Buffer1 size and Second Address Chained bit */
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545 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
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547 /* Set Buffer1 address pointer */
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548 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
\r
550 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
\r
552 /* Enable Ethernet DMA Rx Descriptor interrupt */
\r
553 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
\r
556 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
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557 if(i < (RxBuffCount-1))
\r
559 /* Set next descriptor address register with next descriptor base address */
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560 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
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564 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
\r
565 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
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569 /* Set Receive Descriptor List Address Register */
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570 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
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572 /* Set ETH HAL State to Ready */
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573 heth->State= HAL_ETH_STATE_READY;
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575 /* Process Unlocked */
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576 __HAL_UNLOCK(heth);
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578 /* Return function status */
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583 * @brief Initializes the ETH MSP.
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584 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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585 * the configuration information for ETHERNET module
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588 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
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590 /* NOTE : This function Should not be modified, when the callback is needed,
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591 the HAL_ETH_MspInit could be implemented in the user file
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596 * @brief DeInitializes ETH MSP.
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597 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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598 * the configuration information for ETHERNET module
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601 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
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603 /* NOTE : This function Should not be modified, when the callback is needed,
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604 the HAL_ETH_MspDeInit could be implemented in the user file
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612 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
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613 * @brief Data transfers functions
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616 ==============================================================================
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617 ##### IO operation functions #####
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618 ==============================================================================
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619 [..] This section provides functions allowing to:
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620 (+) Transmit a frame
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621 HAL_ETH_TransmitFrame();
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622 (+) Receive a frame
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623 HAL_ETH_GetReceivedFrame();
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624 HAL_ETH_GetReceivedFrame_IT();
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625 (+) Read from an External PHY register
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626 HAL_ETH_ReadPHYRegister();
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627 (+) Write to an External PHY register
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628 HAL_ETH_WritePHYRegister();
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636 * @brief Sends an Ethernet frame.
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637 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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638 * the configuration information for ETHERNET module
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639 * @param FrameLength: Amount of data to be sent
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640 * @retval HAL status
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642 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
\r
644 uint32_t bufcount = 0, size = 0, i = 0;
\r
646 /* Process Locked */
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649 /* Set the ETH peripheral state to BUSY */
\r
650 heth->State = HAL_ETH_STATE_BUSY;
\r
652 if (FrameLength == 0)
\r
654 /* Set ETH HAL state to READY */
\r
655 heth->State = HAL_ETH_STATE_READY;
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657 /* Process Unlocked */
\r
658 __HAL_UNLOCK(heth);
\r
663 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
\r
664 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
\r
667 heth->State = HAL_ETH_STATE_BUSY_TX;
\r
669 /* Process Unlocked */
\r
670 __HAL_UNLOCK(heth);
\r
675 /* Get the number of needed Tx buffers for the current frame */
\r
676 if (FrameLength > ETH_TX_BUF_SIZE)
\r
678 bufcount = FrameLength/ETH_TX_BUF_SIZE;
\r
679 if (FrameLength % ETH_TX_BUF_SIZE)
\r
690 /* Set LAST and FIRST segment */
\r
691 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
\r
692 /* Set frame size */
\r
693 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
\r
694 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
\r
695 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
\r
696 /* Point to next descriptor */
\r
697 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
\r
701 for (i=0; i< bufcount; i++)
\r
703 /* Clear FIRST and LAST segment bits */
\r
704 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
\r
708 /* Setting the first segment bit */
\r
709 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
\r
713 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
\r
715 if (i == (bufcount-1))
\r
717 /* Setting the last segment bit */
\r
718 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
\r
719 size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
\r
720 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
\r
723 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
\r
724 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
\r
725 /* point to next descriptor */
\r
726 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
\r
730 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
\r
731 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
\r
733 /* Clear TBUS ETHERNET DMA flag */
\r
734 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
\r
735 /* Resume DMA transmission*/
\r
736 (heth->Instance)->DMATPDR = 0;
\r
739 /* Set ETH HAL State to Ready */
\r
740 heth->State = HAL_ETH_STATE_READY;
\r
742 /* Process Unlocked */
\r
743 __HAL_UNLOCK(heth);
\r
745 /* Return function status */
\r
750 * @brief Checks for received frames.
\r
751 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
752 * the configuration information for ETHERNET module
\r
753 * @retval HAL status
\r
755 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
\r
757 uint32_t framelength = 0;
\r
759 /* Process Locked */
\r
762 /* Check the ETH state to BUSY */
\r
763 heth->State = HAL_ETH_STATE_BUSY;
\r
765 /* Check if segment is not owned by DMA */
\r
766 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
\r
767 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
\r
769 /* Check if last segment */
\r
770 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
\r
772 /* increment segment count */
\r
773 (heth->RxFrameInfos).SegCount++;
\r
775 /* Check if last segment is first segment: one segment contains the frame */
\r
776 if ((heth->RxFrameInfos).SegCount == 1)
\r
778 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
\r
781 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
\r
783 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
\r
784 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
\r
785 heth->RxFrameInfos.length = framelength;
\r
787 /* Get the address of the buffer start address */
\r
788 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
\r
789 /* point to next descriptor */
\r
790 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
\r
792 /* Set HAL State to Ready */
\r
793 heth->State = HAL_ETH_STATE_READY;
\r
795 /* Process Unlocked */
\r
796 __HAL_UNLOCK(heth);
\r
798 /* Return function status */
\r
801 /* Check if first segment */
\r
802 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
\r
804 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
\r
805 (heth->RxFrameInfos).LSRxDesc = NULL;
\r
806 (heth->RxFrameInfos).SegCount = 1;
\r
807 /* Point to next descriptor */
\r
808 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
\r
810 /* Check if intermediate segment */
\r
813 (heth->RxFrameInfos).SegCount++;
\r
814 /* Point to next descriptor */
\r
815 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
\r
819 /* Set ETH HAL State to Ready */
\r
820 heth->State = HAL_ETH_STATE_READY;
\r
822 /* Process Unlocked */
\r
823 __HAL_UNLOCK(heth);
\r
825 /* Return function status */
\r
830 * @brief Gets the Received frame in interrupt mode.
\r
831 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
832 * the configuration information for ETHERNET module
\r
833 * @retval HAL status
\r
835 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
\r
837 uint32_t descriptorscancounter = 0;
\r
839 /* Process Locked */
\r
842 /* Set ETH HAL State to BUSY */
\r
843 heth->State = HAL_ETH_STATE_BUSY;
\r
845 /* Scan descriptors owned by CPU */
\r
846 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
\r
848 /* Just for security */
\r
849 descriptorscancounter++;
\r
851 /* Check if first segment in frame */
\r
852 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
\r
853 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
\r
855 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
\r
856 heth->RxFrameInfos.SegCount = 1;
\r
857 /* Point to next descriptor */
\r
858 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
\r
860 /* Check if intermediate segment */
\r
861 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
\r
862 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
\r
864 /* Increment segment count */
\r
865 (heth->RxFrameInfos.SegCount)++;
\r
866 /* Point to next descriptor */
\r
867 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
\r
869 /* Should be last segment */
\r
873 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
\r
875 /* Increment segment count */
\r
876 (heth->RxFrameInfos.SegCount)++;
\r
878 /* Check if last segment is first segment: one segment contains the frame */
\r
879 if ((heth->RxFrameInfos.SegCount) == 1)
\r
881 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
\r
884 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
\r
885 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
\r
887 /* Get the address of the buffer start address */
\r
888 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
\r
890 /* Point to next descriptor */
\r
891 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
\r
893 /* Set HAL State to Ready */
\r
894 heth->State = HAL_ETH_STATE_READY;
\r
896 /* Process Unlocked */
\r
897 __HAL_UNLOCK(heth);
\r
899 /* Return function status */
\r
904 /* Set HAL State to Ready */
\r
905 heth->State = HAL_ETH_STATE_READY;
\r
907 /* Process Unlocked */
\r
908 __HAL_UNLOCK(heth);
\r
910 /* Return function status */
\r
915 * @brief This function handles ETH interrupt request.
\r
916 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
917 * the configuration information for ETHERNET module
\r
918 * @retval HAL status
\r
920 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
\r
922 /* Frame received */
\r
923 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
\r
925 /* Receive complete callback */
\r
926 HAL_ETH_RxCpltCallback(heth);
\r
928 /* Clear the Eth DMA Rx IT pending bits */
\r
929 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
\r
931 /* Set HAL State to Ready */
\r
932 heth->State = HAL_ETH_STATE_READY;
\r
934 /* Process Unlocked */
\r
935 __HAL_UNLOCK(heth);
\r
938 /* Frame transmitted */
\r
939 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
\r
941 /* Transfer complete callback */
\r
942 HAL_ETH_TxCpltCallback(heth);
\r
944 /* Clear the Eth DMA Tx IT pending bits */
\r
945 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
\r
947 /* Set HAL State to Ready */
\r
948 heth->State = HAL_ETH_STATE_READY;
\r
950 /* Process Unlocked */
\r
951 __HAL_UNLOCK(heth);
\r
954 /* Clear the interrupt flags */
\r
955 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
\r
957 /* ETH DMA Error */
\r
958 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
\r
960 /* Ethernet Error callback */
\r
961 HAL_ETH_ErrorCallback(heth);
\r
963 /* Clear the interrupt flags */
\r
964 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
\r
966 /* Set HAL State to Ready */
\r
967 heth->State = HAL_ETH_STATE_READY;
\r
969 /* Process Unlocked */
\r
970 __HAL_UNLOCK(heth);
\r
975 * @brief Tx Transfer completed callbacks.
\r
976 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
977 * the configuration information for ETHERNET module
\r
980 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
\r
982 /* NOTE : This function Should not be modified, when the callback is needed,
\r
983 the HAL_ETH_TxCpltCallback could be implemented in the user file
\r
988 * @brief Rx Transfer completed callbacks.
\r
989 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
990 * the configuration information for ETHERNET module
\r
993 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
\r
995 /* NOTE : This function Should not be modified, when the callback is needed,
\r
996 the HAL_ETH_TxCpltCallback could be implemented in the user file
\r
1001 * @brief Ethernet transfer error callbacks
\r
1002 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1003 * the configuration information for ETHERNET module
\r
1006 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
\r
1008 /* NOTE : This function Should not be modified, when the callback is needed,
\r
1009 the HAL_ETH_TxCpltCallback could be implemented in the user file
\r
1014 * @brief Reads a PHY register
\r
1015 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1016 * the configuration information for ETHERNET module
\r
1017 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
\r
1018 * This parameter can be one of the following values:
\r
1019 * PHY_BCR: Transceiver Basic Control Register,
\r
1020 * PHY_BSR: Transceiver Basic Status Register.
\r
1021 * More PHY register could be read depending on the used PHY
\r
1022 * @param RegValue: PHY register value
\r
1023 * @retval HAL status
\r
1025 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
\r
1027 uint32_t tmpreg = 0;
\r
1028 uint32_t tickstart = 0;
\r
1030 /* Check parameters */
\r
1031 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
\r
1033 /* Check the ETH peripheral state */
\r
1034 if(heth->State == HAL_ETH_STATE_BUSY_RD)
\r
1038 /* Set ETH HAL State to BUSY_RD */
\r
1039 heth->State = HAL_ETH_STATE_BUSY_RD;
\r
1041 /* Get the ETHERNET MACMIIAR value */
\r
1042 tmpreg = heth->Instance->MACMIIAR;
\r
1044 /* Keep only the CSR Clock Range CR[2:0] bits value */
\r
1045 tmpreg &= ~ETH_MACMIIAR_CR_MASK;
\r
1047 /* Prepare the MII address register value */
\r
1048 tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
\r
1049 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
\r
1050 tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
\r
1051 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
\r
1053 /* Write the result value into the MII Address register */
\r
1054 heth->Instance->MACMIIAR = tmpreg;
\r
1057 tickstart = HAL_GetTick();
\r
1059 /* Check for the Busy flag */
\r
1060 while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
\r
1062 /* Check for the Timeout */
\r
1063 if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
\r
1065 heth->State= HAL_ETH_STATE_READY;
\r
1067 /* Process Unlocked */
\r
1068 __HAL_UNLOCK(heth);
\r
1070 return HAL_TIMEOUT;
\r
1073 tmpreg = heth->Instance->MACMIIAR;
\r
1076 /* Get MACMIIDR value */
\r
1077 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
\r
1079 /* Set ETH HAL State to READY */
\r
1080 heth->State = HAL_ETH_STATE_READY;
\r
1082 /* Return function status */
\r
1087 * @brief Writes to a PHY register.
\r
1088 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1089 * the configuration information for ETHERNET module
\r
1090 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
\r
1091 * This parameter can be one of the following values:
\r
1092 * PHY_BCR: Transceiver Control Register.
\r
1093 * More PHY register could be written depending on the used PHY
\r
1094 * @param RegValue: the value to write
\r
1095 * @retval HAL status
\r
1097 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
\r
1099 uint32_t tmpreg = 0;
\r
1100 uint32_t tickstart = 0;
\r
1102 /* Check parameters */
\r
1103 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
\r
1105 /* Check the ETH peripheral state */
\r
1106 if(heth->State == HAL_ETH_STATE_BUSY_WR)
\r
1110 /* Set ETH HAL State to BUSY_WR */
\r
1111 heth->State = HAL_ETH_STATE_BUSY_WR;
\r
1113 /* Get the ETHERNET MACMIIAR value */
\r
1114 tmpreg = heth->Instance->MACMIIAR;
\r
1116 /* Keep only the CSR Clock Range CR[2:0] bits value */
\r
1117 tmpreg &= ~ETH_MACMIIAR_CR_MASK;
\r
1119 /* Prepare the MII register address value */
\r
1120 tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
\r
1121 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
\r
1122 tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
\r
1123 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
\r
1125 /* Give the value to the MII data register */
\r
1126 heth->Instance->MACMIIDR = (uint16_t)RegValue;
\r
1128 /* Write the result value into the MII Address register */
\r
1129 heth->Instance->MACMIIAR = tmpreg;
\r
1132 tickstart = HAL_GetTick();
\r
1134 /* Check for the Busy flag */
\r
1135 while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
\r
1137 /* Check for the Timeout */
\r
1138 if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
\r
1140 heth->State= HAL_ETH_STATE_READY;
\r
1142 /* Process Unlocked */
\r
1143 __HAL_UNLOCK(heth);
\r
1145 return HAL_TIMEOUT;
\r
1148 tmpreg = heth->Instance->MACMIIAR;
\r
1151 /* Set ETH HAL State to READY */
\r
1152 heth->State = HAL_ETH_STATE_READY;
\r
1154 /* Return function status */
\r
1162 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
\r
1163 * @brief Peripheral Control functions
\r
1166 ===============================================================================
\r
1167 ##### Peripheral Control functions #####
\r
1168 ===============================================================================
\r
1169 [..] This section provides functions allowing to:
\r
1170 (+) Enable MAC and DMA transmission and reception.
\r
1172 (+) Disable MAC and DMA transmission and reception.
\r
1174 (+) Set the MAC configuration in runtime mode
\r
1175 HAL_ETH_ConfigMAC();
\r
1176 (+) Set the DMA configuration in runtime mode
\r
1177 HAL_ETH_ConfigDMA();
\r
1184 * @brief Enables Ethernet MAC and DMA reception/transmission
\r
1185 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1186 * the configuration information for ETHERNET module
\r
1187 * @retval HAL status
\r
1189 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
\r
1191 /* Process Locked */
\r
1194 /* Set the ETH peripheral state to BUSY */
\r
1195 heth->State = HAL_ETH_STATE_BUSY;
\r
1197 /* Enable transmit state machine of the MAC for transmission on the MII */
\r
1198 ETH_MACTransmissionEnable(heth);
\r
1200 /* Enable receive state machine of the MAC for reception from the MII */
\r
1201 ETH_MACReceptionEnable(heth);
\r
1203 /* Flush Transmit FIFO */
\r
1204 ETH_FlushTransmitFIFO(heth);
\r
1206 /* Start DMA transmission */
\r
1207 ETH_DMATransmissionEnable(heth);
\r
1209 /* Start DMA reception */
\r
1210 ETH_DMAReceptionEnable(heth);
\r
1212 /* Set the ETH state to READY*/
\r
1213 heth->State= HAL_ETH_STATE_READY;
\r
1215 /* Process Unlocked */
\r
1216 __HAL_UNLOCK(heth);
\r
1218 /* Return function status */
\r
1223 * @brief Stop Ethernet MAC and DMA reception/transmission
\r
1224 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1225 * the configuration information for ETHERNET module
\r
1226 * @retval HAL status
\r
1228 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
\r
1230 /* Process Locked */
\r
1233 /* Set the ETH peripheral state to BUSY */
\r
1234 heth->State = HAL_ETH_STATE_BUSY;
\r
1236 /* Stop DMA transmission */
\r
1237 ETH_DMATransmissionDisable(heth);
\r
1239 /* Stop DMA reception */
\r
1240 ETH_DMAReceptionDisable(heth);
\r
1242 /* Disable receive state machine of the MAC for reception from the MII */
\r
1243 ETH_MACReceptionDisable(heth);
\r
1245 /* Flush Transmit FIFO */
\r
1246 ETH_FlushTransmitFIFO(heth);
\r
1248 /* Disable transmit state machine of the MAC for transmission on the MII */
\r
1249 ETH_MACTransmissionDisable(heth);
\r
1251 /* Set the ETH state*/
\r
1252 heth->State = HAL_ETH_STATE_READY;
\r
1254 /* Process Unlocked */
\r
1255 __HAL_UNLOCK(heth);
\r
1257 /* Return function status */
\r
1262 * @brief Set ETH MAC Configuration.
\r
1263 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1264 * the configuration information for ETHERNET module
\r
1265 * @param macconf: MAC Configuration structure
\r
1266 * @retval HAL status
\r
1268 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
\r
1270 uint32_t tmpreg = 0;
\r
1272 /* Process Locked */
\r
1275 /* Set the ETH peripheral state to BUSY */
\r
1276 heth->State= HAL_ETH_STATE_BUSY;
\r
1278 assert_param(IS_ETH_SPEED(heth->Init.Speed));
\r
1279 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
\r
1281 if (macconf != NULL)
\r
1283 /* Check the parameters */
\r
1284 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
\r
1285 assert_param(IS_ETH_JABBER(macconf->Jabber));
\r
1286 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
\r
1287 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
\r
1288 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
\r
1289 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
\r
1290 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
\r
1291 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
\r
1292 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
\r
1293 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
\r
1294 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
\r
1295 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
\r
1296 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
\r
1297 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
\r
1298 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
\r
1299 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
\r
1300 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
\r
1301 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
\r
1302 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
\r
1303 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
\r
1304 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
\r
1305 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
\r
1306 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
\r
1307 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
\r
1308 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
\r
1309 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
\r
1310 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
\r
1312 /*------------------------ ETHERNET MACCR Configuration --------------------*/
\r
1313 /* Get the ETHERNET MACCR value */
\r
1314 tmpreg = (heth->Instance)->MACCR;
\r
1315 /* Clear WD, PCE, PS, TE and RE bits */
\r
1316 tmpreg &= ETH_MACCR_CLEAR_MASK;
\r
1318 tmpreg |= (uint32_t)(macconf->Watchdog |
\r
1319 macconf->Jabber |
\r
1320 macconf->InterFrameGap |
\r
1321 macconf->CarrierSense |
\r
1322 (heth->Init).Speed |
\r
1323 macconf->ReceiveOwn |
\r
1324 macconf->LoopbackMode |
\r
1325 (heth->Init).DuplexMode |
\r
1326 macconf->ChecksumOffload |
\r
1327 macconf->RetryTransmission |
\r
1328 macconf->AutomaticPadCRCStrip |
\r
1329 macconf->BackOffLimit |
\r
1330 macconf->DeferralCheck);
\r
1332 /* Write to ETHERNET MACCR */
\r
1333 (heth->Instance)->MACCR = (uint32_t)tmpreg;
\r
1335 /* Wait until the write operation will be taken into account :
\r
1336 at least four TX_CLK/RX_CLK clock cycles */
\r
1337 tmpreg = (heth->Instance)->MACCR;
\r
1338 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1339 (heth->Instance)->MACCR = tmpreg;
\r
1341 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
\r
1342 /* Write to ETHERNET MACFFR */
\r
1343 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
\r
1344 macconf->SourceAddrFilter |
\r
1345 macconf->PassControlFrames |
\r
1346 macconf->BroadcastFramesReception |
\r
1347 macconf->DestinationAddrFilter |
\r
1348 macconf->PromiscuousMode |
\r
1349 macconf->MulticastFramesFilter |
\r
1350 macconf->UnicastFramesFilter);
\r
1352 /* Wait until the write operation will be taken into account :
\r
1353 at least four TX_CLK/RX_CLK clock cycles */
\r
1354 tmpreg = (heth->Instance)->MACFFR;
\r
1355 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1356 (heth->Instance)->MACFFR = tmpreg;
\r
1358 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
\r
1359 /* Write to ETHERNET MACHTHR */
\r
1360 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
\r
1362 /* Write to ETHERNET MACHTLR */
\r
1363 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
\r
1364 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
\r
1366 /* Get the ETHERNET MACFCR value */
\r
1367 tmpreg = (heth->Instance)->MACFCR;
\r
1368 /* Clear xx bits */
\r
1369 tmpreg &= ETH_MACFCR_CLEAR_MASK;
\r
1371 tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
\r
1372 macconf->ZeroQuantaPause |
\r
1373 macconf->PauseLowThreshold |
\r
1374 macconf->UnicastPauseFrameDetect |
\r
1375 macconf->ReceiveFlowControl |
\r
1376 macconf->TransmitFlowControl);
\r
1378 /* Write to ETHERNET MACFCR */
\r
1379 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
\r
1381 /* Wait until the write operation will be taken into account :
\r
1382 at least four TX_CLK/RX_CLK clock cycles */
\r
1383 tmpreg = (heth->Instance)->MACFCR;
\r
1384 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1385 (heth->Instance)->MACFCR = tmpreg;
\r
1387 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
\r
1388 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
\r
1389 macconf->VLANTagIdentifier);
\r
1391 /* Wait until the write operation will be taken into account :
\r
1392 at least four TX_CLK/RX_CLK clock cycles */
\r
1393 tmpreg = (heth->Instance)->MACVLANTR;
\r
1394 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1395 (heth->Instance)->MACVLANTR = tmpreg;
\r
1397 else /* macconf == NULL : here we just configure Speed and Duplex mode */
\r
1399 /*------------------------ ETHERNET MACCR Configuration --------------------*/
\r
1400 /* Get the ETHERNET MACCR value */
\r
1401 tmpreg = (heth->Instance)->MACCR;
\r
1403 /* Clear FES and DM bits */
\r
1404 tmpreg &= ~((uint32_t)0x00004800);
\r
1406 tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
\r
1408 /* Write to ETHERNET MACCR */
\r
1409 (heth->Instance)->MACCR = (uint32_t)tmpreg;
\r
1411 /* Wait until the write operation will be taken into account:
\r
1412 at least four TX_CLK/RX_CLK clock cycles */
\r
1413 tmpreg = (heth->Instance)->MACCR;
\r
1414 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1415 (heth->Instance)->MACCR = tmpreg;
\r
1418 /* Set the ETH state to Ready */
\r
1419 heth->State= HAL_ETH_STATE_READY;
\r
1421 /* Process Unlocked */
\r
1422 __HAL_UNLOCK(heth);
\r
1424 /* Return function status */
\r
1429 * @brief Sets ETH DMA Configuration.
\r
1430 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1431 * the configuration information for ETHERNET module
\r
1432 * @param dmaconf: DMA Configuration structure
\r
1433 * @retval HAL status
\r
1435 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
\r
1437 uint32_t tmpreg = 0;
\r
1439 /* Process Locked */
\r
1442 /* Set the ETH peripheral state to BUSY */
\r
1443 heth->State= HAL_ETH_STATE_BUSY;
\r
1445 /* Check parameters */
\r
1446 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
\r
1447 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
\r
1448 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
\r
1449 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
\r
1450 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
\r
1451 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
\r
1452 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
\r
1453 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
\r
1454 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
\r
1455 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
\r
1456 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
\r
1457 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
\r
1458 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
\r
1459 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
\r
1460 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
\r
1461 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
\r
1463 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
\r
1464 /* Get the ETHERNET DMAOMR value */
\r
1465 tmpreg = (heth->Instance)->DMAOMR;
\r
1466 /* Clear xx bits */
\r
1467 tmpreg &= ETH_DMAOMR_CLEAR_MASK;
\r
1469 tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
\r
1470 dmaconf->ReceiveStoreForward |
\r
1471 dmaconf->FlushReceivedFrame |
\r
1472 dmaconf->TransmitStoreForward |
\r
1473 dmaconf->TransmitThresholdControl |
\r
1474 dmaconf->ForwardErrorFrames |
\r
1475 dmaconf->ForwardUndersizedGoodFrames |
\r
1476 dmaconf->ReceiveThresholdControl |
\r
1477 dmaconf->SecondFrameOperate);
\r
1479 /* Write to ETHERNET DMAOMR */
\r
1480 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
\r
1482 /* Wait until the write operation will be taken into account:
\r
1483 at least four TX_CLK/RX_CLK clock cycles */
\r
1484 tmpreg = (heth->Instance)->DMAOMR;
\r
1485 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1486 (heth->Instance)->DMAOMR = tmpreg;
\r
1488 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
\r
1489 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
\r
1490 dmaconf->FixedBurst |
\r
1491 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
\r
1492 dmaconf->TxDMABurstLength |
\r
1493 dmaconf->EnhancedDescriptorFormat |
\r
1494 (dmaconf->DescriptorSkipLength << 2) |
\r
1495 dmaconf->DMAArbitration |
\r
1496 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
\r
1498 /* Wait until the write operation will be taken into account:
\r
1499 at least four TX_CLK/RX_CLK clock cycles */
\r
1500 tmpreg = (heth->Instance)->DMABMR;
\r
1501 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1502 (heth->Instance)->DMABMR = tmpreg;
\r
1504 /* Set the ETH state to Ready */
\r
1505 heth->State= HAL_ETH_STATE_READY;
\r
1507 /* Process Unlocked */
\r
1508 __HAL_UNLOCK(heth);
\r
1510 /* Return function status */
\r
1518 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
\r
1519 * @brief Peripheral State functions
\r
1522 ===============================================================================
\r
1523 ##### Peripheral State functions #####
\r
1524 ===============================================================================
\r
1526 This subsection permits to get in run-time the status of the peripheral
\r
1527 and the data flow.
\r
1528 (+) Get the ETH handle state:
\r
1529 HAL_ETH_GetState();
\r
1537 * @brief Return the ETH HAL state
\r
1538 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1539 * the configuration information for ETHERNET module
\r
1540 * @retval HAL state
\r
1542 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
\r
1544 /* Return ETH state */
\r
1545 return heth->State;
\r
1556 /** @addtogroup ETH_Private_Functions
\r
1561 * @brief Configures Ethernet MAC and DMA with default parameters.
\r
1562 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1563 * the configuration information for ETHERNET module
\r
1564 * @param err: Ethernet Init error
\r
1565 * @retval HAL status
\r
1567 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
\r
1569 ETH_MACInitTypeDef macinit;
\r
1570 ETH_DMAInitTypeDef dmainit;
\r
1571 uint32_t tmpreg = 0;
\r
1573 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
\r
1575 /* Set Ethernet duplex mode to Full-duplex */
\r
1576 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
\r
1578 /* Set Ethernet speed to 100M */
\r
1579 (heth->Init).Speed = ETH_SPEED_100M;
\r
1582 /* Ethernet MAC default initialization **************************************/
\r
1583 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
\r
1584 macinit.Jabber = ETH_JABBER_ENABLE;
\r
1585 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
\r
1586 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
\r
1587 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
\r
1588 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
\r
1589 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
\r
1591 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
\r
1595 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
\r
1597 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
\r
1598 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
\r
1599 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
\r
1600 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
\r
1601 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
\r
1602 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
\r
1603 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
\r
1604 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
\r
1605 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
\r
1606 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
\r
1607 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
\r
1608 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
\r
1609 macinit.HashTableHigh = 0x0;
\r
1610 macinit.HashTableLow = 0x0;
\r
1611 macinit.PauseTime = 0x0;
\r
1612 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
\r
1613 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
\r
1614 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
\r
1615 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
\r
1616 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
\r
1617 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
\r
1618 macinit.VLANTagIdentifier = 0x0;
\r
1620 /*------------------------ ETHERNET MACCR Configuration --------------------*/
\r
1621 /* Get the ETHERNET MACCR value */
\r
1622 tmpreg = (heth->Instance)->MACCR;
\r
1623 /* Clear WD, PCE, PS, TE and RE bits */
\r
1624 tmpreg &= ETH_MACCR_CLEAR_MASK;
\r
1625 /* Set the WD bit according to ETH Watchdog value */
\r
1626 /* Set the JD: bit according to ETH Jabber value */
\r
1627 /* Set the IFG bit according to ETH InterFrameGap value */
\r
1628 /* Set the DCRS bit according to ETH CarrierSense value */
\r
1629 /* Set the FES bit according to ETH Speed value */
\r
1630 /* Set the DO bit according to ETH ReceiveOwn value */
\r
1631 /* Set the LM bit according to ETH LoopbackMode value */
\r
1632 /* Set the DM bit according to ETH Mode value */
\r
1633 /* Set the IPCO bit according to ETH ChecksumOffload value */
\r
1634 /* Set the DR bit according to ETH RetryTransmission value */
\r
1635 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
\r
1636 /* Set the BL bit according to ETH BackOffLimit value */
\r
1637 /* Set the DC bit according to ETH DeferralCheck value */
\r
1638 tmpreg |= (uint32_t)(macinit.Watchdog |
\r
1640 macinit.InterFrameGap |
\r
1641 macinit.CarrierSense |
\r
1642 (heth->Init).Speed |
\r
1643 macinit.ReceiveOwn |
\r
1644 macinit.LoopbackMode |
\r
1645 (heth->Init).DuplexMode |
\r
1646 macinit.ChecksumOffload |
\r
1647 macinit.RetryTransmission |
\r
1648 macinit.AutomaticPadCRCStrip |
\r
1649 macinit.BackOffLimit |
\r
1650 macinit.DeferralCheck);
\r
1652 /* Write to ETHERNET MACCR */
\r
1653 (heth->Instance)->MACCR = (uint32_t)tmpreg;
\r
1655 /* Wait until the write operation will be taken into account:
\r
1656 at least four TX_CLK/RX_CLK clock cycles */
\r
1657 tmpreg = (heth->Instance)->MACCR;
\r
1658 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1659 (heth->Instance)->MACCR = tmpreg;
\r
1661 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
\r
1662 /* Set the RA bit according to ETH ReceiveAll value */
\r
1663 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
\r
1664 /* Set the PCF bit according to ETH PassControlFrames value */
\r
1665 /* Set the DBF bit according to ETH BroadcastFramesReception value */
\r
1666 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
\r
1667 /* Set the PR bit according to ETH PromiscuousMode value */
\r
1668 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
\r
1669 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
\r
1670 /* Write to ETHERNET MACFFR */
\r
1671 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
\r
1672 macinit.SourceAddrFilter |
\r
1673 macinit.PassControlFrames |
\r
1674 macinit.BroadcastFramesReception |
\r
1675 macinit.DestinationAddrFilter |
\r
1676 macinit.PromiscuousMode |
\r
1677 macinit.MulticastFramesFilter |
\r
1678 macinit.UnicastFramesFilter);
\r
1680 /* Wait until the write operation will be taken into account:
\r
1681 at least four TX_CLK/RX_CLK clock cycles */
\r
1682 tmpreg = (heth->Instance)->MACFFR;
\r
1683 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1684 (heth->Instance)->MACFFR = tmpreg;
\r
1686 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
\r
1687 /* Write to ETHERNET MACHTHR */
\r
1688 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
\r
1690 /* Write to ETHERNET MACHTLR */
\r
1691 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
\r
1692 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
\r
1694 /* Get the ETHERNET MACFCR value */
\r
1695 tmpreg = (heth->Instance)->MACFCR;
\r
1696 /* Clear xx bits */
\r
1697 tmpreg &= ETH_MACFCR_CLEAR_MASK;
\r
1699 /* Set the PT bit according to ETH PauseTime value */
\r
1700 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
\r
1701 /* Set the PLT bit according to ETH PauseLowThreshold value */
\r
1702 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
\r
1703 /* Set the RFE bit according to ETH ReceiveFlowControl value */
\r
1704 /* Set the TFE bit according to ETH TransmitFlowControl value */
\r
1705 tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
\r
1706 macinit.ZeroQuantaPause |
\r
1707 macinit.PauseLowThreshold |
\r
1708 macinit.UnicastPauseFrameDetect |
\r
1709 macinit.ReceiveFlowControl |
\r
1710 macinit.TransmitFlowControl);
\r
1712 /* Write to ETHERNET MACFCR */
\r
1713 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
\r
1715 /* Wait until the write operation will be taken into account:
\r
1716 at least four TX_CLK/RX_CLK clock cycles */
\r
1717 tmpreg = (heth->Instance)->MACFCR;
\r
1718 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1719 (heth->Instance)->MACFCR = tmpreg;
\r
1721 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
\r
1722 /* Set the ETV bit according to ETH VLANTagComparison value */
\r
1723 /* Set the VL bit according to ETH VLANTagIdentifier value */
\r
1724 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
\r
1725 macinit.VLANTagIdentifier);
\r
1727 /* Wait until the write operation will be taken into account:
\r
1728 at least four TX_CLK/RX_CLK clock cycles */
\r
1729 tmpreg = (heth->Instance)->MACVLANTR;
\r
1730 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1731 (heth->Instance)->MACVLANTR = tmpreg;
\r
1733 /* Ethernet DMA default initialization ************************************/
\r
1734 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
\r
1735 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
\r
1736 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
\r
1737 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
\r
1738 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
\r
1739 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
\r
1740 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
\r
1741 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
\r
1742 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
\r
1743 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
\r
1744 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
\r
1745 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
\r
1746 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
\r
1747 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
\r
1748 dmainit.DescriptorSkipLength = 0x0;
\r
1749 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
\r
1751 /* Get the ETHERNET DMAOMR value */
\r
1752 tmpreg = (heth->Instance)->DMAOMR;
\r
1753 /* Clear xx bits */
\r
1754 tmpreg &= ETH_DMAOMR_CLEAR_MASK;
\r
1756 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
\r
1757 /* Set the RSF bit according to ETH ReceiveStoreForward value */
\r
1758 /* Set the DFF bit according to ETH FlushReceivedFrame value */
\r
1759 /* Set the TSF bit according to ETH TransmitStoreForward value */
\r
1760 /* Set the TTC bit according to ETH TransmitThresholdControl value */
\r
1761 /* Set the FEF bit according to ETH ForwardErrorFrames value */
\r
1762 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
\r
1763 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
\r
1764 /* Set the OSF bit according to ETH SecondFrameOperate value */
\r
1765 tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
\r
1766 dmainit.ReceiveStoreForward |
\r
1767 dmainit.FlushReceivedFrame |
\r
1768 dmainit.TransmitStoreForward |
\r
1769 dmainit.TransmitThresholdControl |
\r
1770 dmainit.ForwardErrorFrames |
\r
1771 dmainit.ForwardUndersizedGoodFrames |
\r
1772 dmainit.ReceiveThresholdControl |
\r
1773 dmainit.SecondFrameOperate);
\r
1775 /* Write to ETHERNET DMAOMR */
\r
1776 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
\r
1778 /* Wait until the write operation will be taken into account:
\r
1779 at least four TX_CLK/RX_CLK clock cycles */
\r
1780 tmpreg = (heth->Instance)->DMAOMR;
\r
1781 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1782 (heth->Instance)->DMAOMR = tmpreg;
\r
1784 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
\r
1785 /* Set the AAL bit according to ETH AddressAlignedBeats value */
\r
1786 /* Set the FB bit according to ETH FixedBurst value */
\r
1787 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
\r
1788 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
\r
1789 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
\r
1790 /* Set the DSL bit according to ETH DesciptorSkipLength value */
\r
1791 /* Set the PR and DA bits according to ETH DMAArbitration value */
\r
1792 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
\r
1793 dmainit.FixedBurst |
\r
1794 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
\r
1795 dmainit.TxDMABurstLength |
\r
1796 dmainit.EnhancedDescriptorFormat |
\r
1797 (dmainit.DescriptorSkipLength << 2) |
\r
1798 dmainit.DMAArbitration |
\r
1799 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
\r
1801 /* Wait until the write operation will be taken into account:
\r
1802 at least four TX_CLK/RX_CLK clock cycles */
\r
1803 tmpreg = (heth->Instance)->DMABMR;
\r
1804 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1805 (heth->Instance)->DMABMR = tmpreg;
\r
1807 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
\r
1809 /* Enable the Ethernet Rx Interrupt */
\r
1810 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
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1813 /* Initialize MAC address in ethernet MAC */
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1814 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
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1818 * @brief Configures the selected MAC address.
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1819 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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1820 * the configuration information for ETHERNET module
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1821 * @param MacAddr: The MAC address to configure
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1822 * This parameter can be one of the following values:
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1823 * @arg ETH_MAC_Address0: MAC Address0
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1824 * @arg ETH_MAC_Address1: MAC Address1
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1825 * @arg ETH_MAC_Address2: MAC Address2
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1826 * @arg ETH_MAC_Address3: MAC Address3
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1827 * @param Addr: Pointer to MAC address buffer data (6 bytes)
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1828 * @retval HAL status
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1830 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
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1834 /* Check the parameters */
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1835 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
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1837 /* Calculate the selected MAC address high register */
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1838 tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
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1839 /* Load the selected MAC address high register */
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1840 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
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1841 /* Calculate the selected MAC address low register */
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1842 tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
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1844 /* Load the selected MAC address low register */
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1845 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
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1849 * @brief Enables the MAC transmission.
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1850 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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1851 * the configuration information for ETHERNET module
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1854 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
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1856 __IO uint32_t tmpreg = 0;
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1858 /* Enable the MAC transmission */
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1859 (heth->Instance)->MACCR |= ETH_MACCR_TE;
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1861 /* Wait until the write operation will be taken into account:
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1862 at least four TX_CLK/RX_CLK clock cycles */
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1863 tmpreg = (heth->Instance)->MACCR;
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1864 HAL_Delay(ETH_REG_WRITE_DELAY);
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1865 (heth->Instance)->MACCR = tmpreg;
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1869 * @brief Disables the MAC transmission.
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1870 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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1871 * the configuration information for ETHERNET module
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1874 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
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1876 __IO uint32_t tmpreg = 0;
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1878 /* Disable the MAC transmission */
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1879 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
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1881 /* Wait until the write operation will be taken into account:
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1882 at least four TX_CLK/RX_CLK clock cycles */
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1883 tmpreg = (heth->Instance)->MACCR;
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1884 HAL_Delay(ETH_REG_WRITE_DELAY);
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1885 (heth->Instance)->MACCR = tmpreg;
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1889 * @brief Enables the MAC reception.
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1890 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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1891 * the configuration information for ETHERNET module
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1894 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
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1896 __IO uint32_t tmpreg = 0;
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1898 /* Enable the MAC reception */
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1899 (heth->Instance)->MACCR |= ETH_MACCR_RE;
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1901 /* Wait until the write operation will be taken into account:
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1902 at least four TX_CLK/RX_CLK clock cycles */
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1903 tmpreg = (heth->Instance)->MACCR;
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1904 HAL_Delay(ETH_REG_WRITE_DELAY);
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1905 (heth->Instance)->MACCR = tmpreg;
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1909 * @brief Disables the MAC reception.
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1910 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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1911 * the configuration information for ETHERNET module
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1914 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
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1916 __IO uint32_t tmpreg = 0;
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1918 /* Disable the MAC reception */
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1919 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
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1921 /* Wait until the write operation will be taken into account:
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1922 at least four TX_CLK/RX_CLK clock cycles */
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1923 tmpreg = (heth->Instance)->MACCR;
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1924 HAL_Delay(ETH_REG_WRITE_DELAY);
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1925 (heth->Instance)->MACCR = tmpreg;
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1929 * @brief Enables the DMA transmission.
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1930 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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1931 * the configuration information for ETHERNET module
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1934 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
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1936 /* Enable the DMA transmission */
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1937 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
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1941 * @brief Disables the DMA transmission.
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1942 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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1943 * the configuration information for ETHERNET module
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1946 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
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1948 /* Disable the DMA transmission */
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1949 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
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1953 * @brief Enables the DMA reception.
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1954 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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1955 * the configuration information for ETHERNET module
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1958 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
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1960 /* Enable the DMA reception */
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1961 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
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1965 * @brief Disables the DMA reception.
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1966 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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1967 * the configuration information for ETHERNET module
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1970 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
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1972 /* Disable the DMA reception */
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1973 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
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1977 * @brief Clears the ETHERNET transmit FIFO.
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1978 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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1979 * the configuration information for ETHERNET module
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1982 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
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1984 __IO uint32_t tmpreg = 0;
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1986 /* Set the Flush Transmit FIFO bit */
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1987 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
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1989 /* Wait until the write operation will be taken into account:
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1990 at least four TX_CLK/RX_CLK clock cycles */
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1991 tmpreg = (heth->Instance)->DMAOMR;
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1992 HAL_Delay(ETH_REG_WRITE_DELAY);
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1993 (heth->Instance)->DMAOMR = tmpreg;
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2000 #endif /* HAL_ETH_MODULE_ENABLED */
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2009 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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