2 ******************************************************************************
\r
3 * @file stm32f7xx_hal_flash_ex.c
\r
4 * @author MCD Application Team
\r
6 * @date 24-March-2015
\r
7 * @brief Extended FLASH HAL module driver.
\r
8 * This file provides firmware functions to manage the following
\r
9 * functionalities of the FLASH extension peripheral:
\r
10 * + Extended programming operations functions
\r
13 ==============================================================================
\r
14 ##### Flash Extension features #####
\r
15 ==============================================================================
\r
17 [..] Comparing to other previous devices, the FLASH interface for STM32F727xx/437xx and
\r
18 devices contains the following additional features
\r
20 (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
\r
22 (+) Dual bank memory organization
\r
23 (+) PCROP protection for all banks
\r
25 ##### How to use this driver #####
\r
26 ==============================================================================
\r
27 [..] This driver provides functions to configure and program the FLASH memory
\r
28 of all STM32F7xx devices. It includes
\r
29 (#) FLASH Memory Erase functions:
\r
30 (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
\r
31 HAL_FLASH_Lock() functions
\r
32 (++) Erase function: Erase sector, erase all sectors
\r
33 (++) There are two modes of erase :
\r
34 (+++) Polling Mode using HAL_FLASHEx_Erase()
\r
35 (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
\r
37 (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
\r
38 (++) Set/Reset the write protection
\r
39 (++) Set the Read protection Level
\r
40 (++) Set the BOR level
\r
41 (++) Program the user Option Bytes
\r
42 (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to :
\r
43 (++) Extended space (bank 2) erase function
\r
44 (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2)
\r
45 (++) Dual Boot activation
\r
46 (++) Write protection configuration for bank 2
\r
47 (++) PCROP protection configuration and control for both banks
\r
50 ******************************************************************************
\r
53 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
\r
55 * Redistribution and use in source and binary forms, with or without modification,
\r
56 * are permitted provided that the following conditions are met:
\r
57 * 1. Redistributions of source code must retain the above copyright notice,
\r
58 * this list of conditions and the following disclaimer.
\r
59 * 2. Redistributions in binary form must reproduce the above copyright notice,
\r
60 * this list of conditions and the following disclaimer in the documentation
\r
61 * and/or other materials provided with the distribution.
\r
62 * 3. Neither the name of STMicroelectronics nor the names of its contributors
\r
63 * may be used to endorse or promote products derived from this software
\r
64 * without specific prior written permission.
\r
66 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
\r
67 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
\r
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
\r
69 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
\r
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
\r
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
\r
72 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
\r
73 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
\r
74 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
\r
75 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\r
77 ******************************************************************************
\r
80 /* Includes ------------------------------------------------------------------*/
\r
81 #include "stm32f7xx_hal.h"
\r
83 /** @addtogroup STM32F7xx_HAL_Driver
\r
87 /** @defgroup FLASHEx FLASHEx
\r
88 * @brief FLASH HAL Extension module driver
\r
92 #ifdef HAL_FLASH_MODULE_ENABLED
\r
94 /* Private typedef -----------------------------------------------------------*/
\r
95 /* Private define ------------------------------------------------------------*/
\r
96 /** @addtogroup FLASHEx_Private_Constants
\r
99 #define SECTOR_MASK ((uint32_t)0xFFFFFF07)
\r
100 #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
\r
105 /* Private macro -------------------------------------------------------------*/
\r
106 /* Private variables ---------------------------------------------------------*/
\r
107 /** @addtogroup FLASHEx_Private_Variables
\r
110 extern FLASH_ProcessTypeDef pFlash;
\r
115 /* Private function prototypes -----------------------------------------------*/
\r
116 /** @addtogroup FLASHEx_Private_Functions
\r
119 /* Option bytes control */
\r
120 static void FLASH_MassErase(uint8_t VoltageRange);
\r
121 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector);
\r
122 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector);
\r
123 static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level);
\r
124 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);
\r
125 static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);
\r
126 static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);
\r
127 static uint32_t FLASH_OB_GetUser(void);
\r
128 static uint32_t FLASH_OB_GetWRP(void);
\r
129 static FlagStatus FLASH_OB_GetRDP(void);
\r
130 static uint32_t FLASH_OB_GetBOR(void);
\r
131 static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption);
\r
133 extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
\r
138 /* Exported functions --------------------------------------------------------*/
\r
139 /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
\r
143 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
\r
144 * @brief Extended IO operation functions
\r
147 ===============================================================================
\r
148 ##### Extended programming operation functions #####
\r
149 ===============================================================================
\r
151 This subsection provides a set of functions allowing to manage the Extension FLASH
\r
152 programming operations Operations.
\r
158 * @brief Perform a mass erase or erase the specified FLASH memory sectors
\r
159 * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
\r
160 * contains the configuration information for the erasing.
\r
162 * @param[out] SectorError: pointer to variable that
\r
163 * contains the configuration information on faulty sector in case of error
\r
164 * (0xFFFFFFFF means that all the sectors have been correctly erased)
\r
166 * @retval HAL Status
\r
168 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
\r
170 HAL_StatusTypeDef status = HAL_ERROR;
\r
171 uint32_t index = 0;
\r
173 /* Process Locked */
\r
174 __HAL_LOCK(&pFlash);
\r
176 /* Check the parameters */
\r
177 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
\r
179 /* Wait for last operation to be completed */
\r
180 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
\r
182 if(status == HAL_OK)
\r
184 /*Initialization of SectorError variable*/
\r
185 *SectorError = 0xFFFFFFFF;
\r
187 if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
\r
189 /*Mass erase to be done*/
\r
190 FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
\r
192 /* Wait for last operation to be completed */
\r
193 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
\r
195 /* if the erase operation is completed, disable the MER Bit */
\r
196 FLASH->CR &= (~FLASH_MER_BIT);
\r
200 /* Check the parameters */
\r
201 assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
\r
203 /* Erase by sector by sector to be done*/
\r
204 for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
\r
206 FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
\r
208 /* Wait for last operation to be completed */
\r
209 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
\r
211 /* If the erase operation is completed, disable the SER Bit */
\r
212 FLASH->CR &= (~FLASH_CR_SER);
\r
213 FLASH->CR &= SECTOR_MASK;
\r
215 if(status != HAL_OK)
\r
217 /* In case of error, stop erase procedure and return the faulty sector*/
\r
218 *SectorError = index;
\r
225 /* Process Unlocked */
\r
226 __HAL_UNLOCK(&pFlash);
\r
232 * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
\r
233 * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
\r
234 * contains the configuration information for the erasing.
\r
236 * @retval HAL Status
\r
238 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
\r
240 HAL_StatusTypeDef status = HAL_OK;
\r
242 /* Process Locked */
\r
243 __HAL_LOCK(&pFlash);
\r
245 /* Check the parameters */
\r
246 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
\r
248 /* Enable End of FLASH Operation interrupt */
\r
249 __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
\r
251 /* Enable Error source interrupt */
\r
252 __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
\r
254 /* Clear pending flags (if any) */
\r
255 __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
\r
256 FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);
\r
258 if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
\r
260 /*Mass erase to be done*/
\r
261 pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
\r
262 FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
\r
266 /* Erase by sector to be done*/
\r
268 /* Check the parameters */
\r
269 assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
\r
271 pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
\r
272 pFlash.NbSectorsToErase = pEraseInit->NbSectors;
\r
273 pFlash.Sector = pEraseInit->Sector;
\r
274 pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
\r
276 /*Erase 1st sector and wait for IT*/
\r
277 FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);
\r
284 * @brief Program option bytes
\r
285 * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
\r
286 * contains the configuration information for the programming.
\r
288 * @retval HAL Status
\r
290 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
\r
292 HAL_StatusTypeDef status = HAL_ERROR;
\r
294 /* Process Locked */
\r
295 __HAL_LOCK(&pFlash);
\r
297 /* Check the parameters */
\r
298 assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
\r
300 /* Write protection configuration */
\r
301 if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
\r
303 assert_param(IS_WRPSTATE(pOBInit->WRPState));
\r
304 if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
\r
306 /*Enable of Write protection on the selected Sector*/
\r
307 status = FLASH_OB_EnableWRP(pOBInit->WRPSector);
\r
311 /*Disable of Write protection on the selected Sector*/
\r
312 status = FLASH_OB_DisableWRP(pOBInit->WRPSector);
\r
316 /* Read protection configuration */
\r
317 if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
\r
319 status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
\r
322 /* USER configuration */
\r
323 if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
\r
325 status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW,
\r
326 pOBInit->USERConfig & OB_IWDG_SW,
\r
327 pOBInit->USERConfig & OB_STOP_NO_RST,
\r
328 pOBInit->USERConfig & OB_STDBY_NO_RST,
\r
329 pOBInit->USERConfig & OB_IWDG_STOP_FREEZE,
\r
330 pOBInit->USERConfig & OB_IWDG_STDBY_FREEZE);
\r
333 /* BOR Level configuration */
\r
334 if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
\r
336 status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
\r
339 /* Boot 0 Address configuration */
\r
340 if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0)
\r
342 status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0);
\r
345 /* Boot 1 Address configuration */
\r
346 if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1)
\r
348 status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1);
\r
351 /* Process Unlocked */
\r
352 __HAL_UNLOCK(&pFlash);
\r
358 * @brief Get the Option byte configuration
\r
359 * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
\r
360 * contains the configuration information for the programming.
\r
364 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
\r
366 pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
\r
367 OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;
\r
370 pOBInit->WRPSector = FLASH_OB_GetWRP();
\r
373 pOBInit->RDPLevel = FLASH_OB_GetRDP();
\r
376 pOBInit->USERConfig = FLASH_OB_GetUser();
\r
379 pOBInit->BORLevel = FLASH_OB_GetBOR();
\r
381 /*Get Boot Address when Boot pin = 0 */
\r
382 pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0);
\r
384 /*Get Boot Address when Boot pin = 1 */
\r
385 pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);
\r
393 * @brief Full erase of FLASH memory sectors
\r
394 * @param VoltageRange: The device voltage range which defines the erase parallelism.
\r
395 * This parameter can be one of the following values:
\r
396 * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
\r
397 * the operation will be done by byte (8-bit)
\r
398 * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
\r
399 * the operation will be done by half word (16-bit)
\r
400 * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
\r
401 * the operation will be done by word (32-bit)
\r
402 * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
\r
403 * the operation will be done by double word (64-bit)
\r
405 * @retval HAL Status
\r
407 static void FLASH_MassErase(uint8_t VoltageRange)
\r
409 uint32_t tmp_psize = 0;
\r
411 /* Check the parameters */
\r
412 assert_param(IS_VOLTAGERANGE(VoltageRange));
\r
414 /* if the previous operation is completed, proceed to erase all sectors */
\r
415 FLASH->CR &= CR_PSIZE_MASK;
\r
416 FLASH->CR |= tmp_psize;
\r
417 FLASH->CR |= FLASH_CR_MER;
\r
418 FLASH->CR |= FLASH_CR_STRT;
\r
419 /* Data synchronous Barrier (DSB) Just after the write operation
\r
420 This will force the CPU to respect the sequence of instruction (no optimization).*/
\r
425 * @brief Erase the specified FLASH memory sector
\r
426 * @param Sector: FLASH sector to erase
\r
427 * The value of this parameter depend on device used within the same series
\r
428 * @param VoltageRange: The device voltage range which defines the erase parallelism.
\r
429 * This parameter can be one of the following values:
\r
430 * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
\r
431 * the operation will be done by byte (8-bit)
\r
432 * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
\r
433 * the operation will be done by half word (16-bit)
\r
434 * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
\r
435 * the operation will be done by word (32-bit)
\r
436 * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
\r
437 * the operation will be done by double word (64-bit)
\r
441 void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
\r
443 uint32_t tmp_psize = 0;
\r
445 /* Check the parameters */
\r
446 assert_param(IS_FLASH_SECTOR(Sector));
\r
447 assert_param(IS_VOLTAGERANGE(VoltageRange));
\r
449 if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
\r
451 tmp_psize = FLASH_PSIZE_BYTE;
\r
453 else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
\r
455 tmp_psize = FLASH_PSIZE_HALF_WORD;
\r
457 else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
\r
459 tmp_psize = FLASH_PSIZE_WORD;
\r
463 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
\r
466 /* If the previous operation is completed, proceed to erase the sector */
\r
467 FLASH->CR &= CR_PSIZE_MASK;
\r
468 FLASH->CR |= tmp_psize;
\r
469 FLASH->CR &= SECTOR_MASK;
\r
470 FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
\r
471 FLASH->CR |= FLASH_CR_STRT;
\r
473 /* Data synchronous Barrier (DSB) Just after the write operation
\r
474 This will force the CPU to respect the sequence of instruction (no optimization).*/
\r
479 * @brief Enable the write protection of the desired bank1 or bank 2 sectors
\r
481 * @note When the memory read protection level is selected (RDP level = 1),
\r
482 * it is not possible to program or erase the flash sector i if CortexM4
\r
483 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
\r
484 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
\r
486 * @param WRPSector: specifies the sector(s) to be write protected.
\r
487 * This parameter can be one of the following values:
\r
488 * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7
\r
489 * @arg OB_WRP_SECTOR_All
\r
491 * @retval HAL FLASH State
\r
493 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)
\r
495 HAL_StatusTypeDef status = HAL_OK;
\r
497 /* Check the parameters */
\r
498 assert_param(IS_OB_WRP_SECTOR(WRPSector));
\r
500 /* Wait for last operation to be completed */
\r
501 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
\r
503 if(status == HAL_OK)
\r
505 /*Write protection enabled on sectors */
\r
506 FLASH->OPTCR &= (~WRPSector);
\r
513 * @brief Disable the write protection of the desired bank1 or bank 2 sectors
\r
515 * @note When the memory read protection level is selected (RDP level = 1),
\r
516 * it is not possible to program or erase the flash sector i if CortexM4
\r
517 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
\r
519 * @param WRPSector: specifies the sector(s) to be write protected.
\r
520 * This parameter can be one of the following values:
\r
521 * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7
\r
522 * @arg OB_WRP_Sector_All
\r
525 * @retval HAL Status
\r
527 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
\r
529 HAL_StatusTypeDef status = HAL_OK;
\r
531 /* Check the parameters */
\r
532 assert_param(IS_OB_WRP_SECTOR(WRPSector));
\r
534 /* Wait for last operation to be completed */
\r
535 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
\r
537 if(status == HAL_OK)
\r
539 /* Write protection disabled on sectors */
\r
540 FLASH->OPTCR |= (WRPSector);
\r
550 * @brief Set the read protection level.
\r
551 * @param Level: specifies the read protection level.
\r
552 * This parameter can be one of the following values:
\r
553 * @arg OB_RDP_LEVEL_0: No protection
\r
554 * @arg OB_RDP_LEVEL_1: Read protection of the memory
\r
555 * @arg OB_RDP_LEVEL_2: Full chip protection
\r
557 * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
\r
559 * @retval HAL Status
\r
561 static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level)
\r
563 HAL_StatusTypeDef status = HAL_OK;
\r
565 /* Check the parameters */
\r
566 assert_param(IS_OB_RDP_LEVEL(Level));
\r
568 /* Wait for last operation to be completed */
\r
569 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
\r
571 if(status == HAL_OK)
\r
573 MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_RDP, Level);
\r
580 * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
\r
581 * @param Wwdg: Selects the IWDG mode
\r
582 * This parameter can be one of the following values:
\r
583 * @arg OB_WWDG_SW: Software WWDG selected
\r
584 * @arg OB_WWDG_HW: Hardware WWDG selected
\r
585 * @param Iwdg: Selects the WWDG mode
\r
586 * This parameter can be one of the following values:
\r
587 * @arg OB_IWDG_SW: Software IWDG selected
\r
588 * @arg OB_IWDG_HW: Hardware IWDG selected
\r
589 * @param Stop: Reset event when entering STOP mode.
\r
590 * This parameter can be one of the following values:
\r
591 * @arg OB_STOP_NO_RST: No reset generated when entering in STOP
\r
592 * @arg OB_STOP_RST: Reset generated when entering in STOP
\r
593 * @param Stdby: Reset event when entering Standby mode.
\r
594 * This parameter can be one of the following values:
\r
595 * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
\r
596 * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
\r
597 * @param Iwdgstop: Independent watchdog counter freeze in Stop mode.
\r
598 * This parameter can be one of the following values:
\r
599 * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP
\r
600 * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP
\r
601 * @param Iwdgstdby: Independent watchdog counter freeze in standby mode.
\r
602 * This parameter can be one of the following values:
\r
603 * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY
\r
604 * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY
\r
605 * @retval HAL Status
\r
607 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby )
\r
609 uint32_t useroptionmask = 0x00;
\r
610 uint32_t useroptionvalue = 0x00;
\r
612 HAL_StatusTypeDef status = HAL_OK;
\r
614 /* Check the parameters */
\r
615 assert_param(IS_OB_WWDG_SOURCE(Wwdg));
\r
616 assert_param(IS_OB_IWDG_SOURCE(Iwdg));
\r
617 assert_param(IS_OB_STOP_SOURCE(Stop));
\r
618 assert_param(IS_OB_STDBY_SOURCE(Stdby));
\r
619 assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));
\r
620 assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));
\r
622 /* Wait for last operation to be completed */
\r
623 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
\r
625 if(status == HAL_OK)
\r
627 useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \
\r
628 FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY);
\r
630 useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby);
\r
632 /* Update User Option Byte */
\r
633 MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);
\r
641 * @brief Set the BOR Level.
\r
642 * @param Level: specifies the Option Bytes BOR Reset Level.
\r
643 * This parameter can be one of the following values:
\r
644 * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
\r
645 * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
\r
646 * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
\r
647 * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
\r
648 * @retval HAL Status
\r
650 static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
\r
652 /* Check the parameters */
\r
653 assert_param(IS_OB_BOR_LEVEL(Level));
\r
655 /* Set the BOR Level */
\r
656 MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level);
\r
663 * @brief Configure Boot base address.
\r
665 * @param BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1
\r
666 * This parameter can be one of the following values:
\r
667 * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0
\r
668 * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1
\r
669 * Address: specifies Boot base address
\r
670 * This parameter can be one of the following values:
\r
671 * @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)
\r
672 * @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000)
\r
673 * @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)
\r
674 * @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)
\r
675 * @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)
\r
676 * @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)
\r
677 * @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)
\r
679 * @retval HAL Status
\r
681 static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address)
\r
683 HAL_StatusTypeDef status = HAL_OK;
\r
685 /* Check the parameters */
\r
686 assert_param(IS_OB_BOOT_ADDRESS(Address));
\r
688 /* Wait for last operation to be completed */
\r
689 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
\r
691 if(status == HAL_OK)
\r
693 if(BootOption == OPTIONBYTE_BOOTADDR_0)
\r
695 MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address);
\r
699 MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));
\r
707 * @brief Return the FLASH User Option Byte value.
\r
708 * @retval uint32_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
\r
709 * and RST_STDBY(Bit2).
\r
711 static uint32_t FLASH_OB_GetUser(void)
\r
713 /* Return the User Option Byte */
\r
714 return ((uint32_t)(FLASH->OPTCR & 0xC00000F0));
\r
718 * @brief Return the FLASH Write Protection Option Bytes value.
\r
719 * @retval uint32_t FLASH Write Protection Option Bytes value
\r
721 static uint32_t FLASH_OB_GetWRP(void)
\r
723 /* Return the FLASH write protection Register value */
\r
724 return ((uint32_t)(FLASH->OPTCR & 0x00FF0000));
\r
728 * @brief Returns the FLASH Read Protection level.
\r
729 * @retval FlagStatus FLASH ReadOut Protection Status:
\r
730 * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
\r
731 * - RESET, when OB_RDP_Level_0 is set
\r
733 static FlagStatus FLASH_OB_GetRDP(void)
\r
735 FlagStatus readstatus = RESET;
\r
737 if (((uint16_t)(FLASH->OPTCR & 0xFF00)) != (uint16_t)OB_RDP_LEVEL_0)
\r
746 * @brief Returns the FLASH BOR level.
\r
747 * @retval uint32_t The FLASH BOR level:
\r
748 * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
\r
749 * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
\r
750 * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
\r
751 * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
\r
753 static uint32_t FLASH_OB_GetBOR(void)
\r
755 /* Return the FLASH BOR level */
\r
756 return ((uint32_t)(FLASH->OPTCR & 0x0C));
\r
760 * @brief Configure Boot base address.
\r
762 * @param BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1
\r
763 * This parameter can be one of the following values:
\r
764 * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0
\r
765 * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1
\r
767 * @retval uint32_t Boot Base Address:
\r
768 * - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)
\r
769 * - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000)
\r
770 * - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)
\r
771 * - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)
\r
772 * - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)
\r
773 * - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)
\r
774 * - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)
\r
776 static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption)
\r
778 uint32_t Address = 0;
\r
780 /* Return the Boot base Address */
\r
781 if(BootOption == OPTIONBYTE_BOOTADDR_0)
\r
783 Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0;
\r
787 Address = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16);
\r
797 #endif /* HAL_FLASH_MODULE_ENABLED */
\r
807 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r