2 ******************************************************************************
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3 * @file stm32f7xx_hal_qspi.c
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4 * @author MCD Application Team
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6 * @date 24-March-2015
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7 * @brief QSPI HAL module driver.
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9 * This file provides firmware functions to manage the following
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10 * functionalities of the QuadSPI interface (QSPI).
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11 * + Initialization and de-initialization functions
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12 * + Indirect functional mode management
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13 * + Memory-mapped functional mode management
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14 * + Auto-polling functional mode management
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15 * + Interrupts and flags management
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16 * + DMA channel configuration for indirect functional mode
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17 * + Errors management and abort functionality
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21 ===============================================================================
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22 ##### How to use this driver #####
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23 ===============================================================================
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25 *** Initialization ***
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26 ======================
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28 (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
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29 (+) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
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30 (+) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
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31 (+) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
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32 (+) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
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33 (+) If interrupt mode is used, enable and configure QuadSPI global
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34 interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
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35 (+) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
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36 with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
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37 link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
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38 DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
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39 (#) Configure the flash size, the clock prescaler, the fifo threshold, the
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40 clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
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42 *** Indirect functional mode ***
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43 ================================
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45 (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
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47 (+) Instruction phase : the mode used and if present the instruction opcode.
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48 (+) Address phase : the mode used and if present the size and the address value.
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49 (+) Alternate-bytes phase : the mode used and if present the size and the alternate
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51 (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
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52 (+) Data phase : the mode used and if present the number of bytes.
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53 (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
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55 (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
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56 (#) If no data is required for the command, it is sent directly to the memory :
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57 (+) In polling mode, the output of the function is done when the transfer is complete.
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58 (+) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
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59 (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
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60 HAL_QSPI_Transmit_IT() after the command configuration :
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61 (+) In polling mode, the output of the function is done when the transfer is complete.
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62 (+) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
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63 is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
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64 (+) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
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65 HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
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66 (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
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67 HAL_QSPI_Receive_IT() after the command configuration :
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68 (+) In polling mode, the output of the function is done when the transfer is complete.
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69 (+) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
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70 is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
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71 (+) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
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72 HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
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74 *** Auto-polling functional mode ***
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75 ====================================
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77 (#) Configure the command sequence and the auto-polling functional mode using the
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78 HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
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79 (+) Instruction phase : the mode used and if present the instruction opcode.
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80 (+) Address phase : the mode used and if present the size and the address value.
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81 (+) Alternate-bytes phase : the mode used and if present the size and the alternate
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83 (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
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84 (+) Data phase : the mode used.
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85 (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
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87 (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
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88 (+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
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89 the polling interval and the automatic stop activation.
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90 (#) After the configuration :
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91 (+) In polling mode, the output of the function is done when the status match is reached. The
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92 automatic stop is activated to avoid an infinite loop.
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93 (+) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
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95 *** Memory-mapped functional mode ***
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96 =====================================
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98 (#) Configure the command sequence and the memory-mapped functional mode using the
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99 HAL_QSPI_MemoryMapped() functions :
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100 (+) Instruction phase : the mode used and if present the instruction opcode.
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101 (+) Address phase : the mode used and the size.
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102 (+) Alternate-bytes phase : the mode used and if present the size and the alternate
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104 (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
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105 (+) Data phase : the mode used.
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106 (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
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108 (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
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109 (+) The timeout activation and the timeout period.
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110 (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
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111 the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
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113 *** Errors management and abort functionality ***
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114 ==================================================
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116 (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
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117 (#) HAL_QSPI_Abort() function aborts any on-going operation and flushes the fifo.
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118 (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
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120 *** Workarounds linked to Silicon Limitation ***
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121 ====================================================
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123 (#) Workarounds Implemented inside HAL Driver
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124 (+) Extra data written in the FIFO at the end of a read transfer
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127 ******************************************************************************
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130 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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132 * Redistribution and use in source and binary forms, with or without modification,
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133 * are permitted provided that the following conditions are met:
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134 * 1. Redistributions of source code must retain the above copyright notice,
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135 * this list of conditions and the following disclaimer.
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136 * 2. Redistributions in binary form must reproduce the above copyright notice,
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137 * this list of conditions and the following disclaimer in the documentation
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138 * and/or other materials provided with the distribution.
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139 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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140 * may be used to endorse or promote products derived from this software
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141 * without specific prior written permission.
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143 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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144 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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145 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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146 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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147 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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148 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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149 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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150 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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151 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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152 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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154 ******************************************************************************
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157 /* Includes ------------------------------------------------------------------*/
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158 #include "stm32f7xx_hal.h"
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160 /** @addtogroup STM32F7xx_HAL_Driver
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164 /** @defgroup QSPI QSPI
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165 * @brief HAL QSPI module driver
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168 #ifdef HAL_QSPI_MODULE_ENABLED
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170 /* Private typedef -----------------------------------------------------------*/
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171 /* Private define ------------------------------------------------------------*/
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172 /** @addtogroup QSPI_Private_Constants
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175 #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!<Indirect write mode*/
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176 #define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
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177 #define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
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178 #define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/
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183 /* Private macro -------------------------------------------------------------*/
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184 /** @addtogroup QSPI_Private_Macros QSPI Private Macros
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187 #define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
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188 ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \
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189 ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \
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190 ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
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195 /* Private variables ---------------------------------------------------------*/
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196 /* Private function prototypes -----------------------------------------------*/
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197 /** @addtogroup QSPI_Private_Functions QSPI Private Functions
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200 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
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201 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
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202 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
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203 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
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204 static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
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205 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);
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206 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
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211 /* Exported functions ---------------------------------------------------------*/
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213 /** @defgroup QSPI_Exported_Functions QSPI Exported Functions
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217 /** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
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218 * @brief Initialization and Configuration functions
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221 ===============================================================================
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222 ##### Initialization and Configuration functions #####
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223 ===============================================================================
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225 This subsection provides a set of functions allowing to :
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226 (+) Initialize the QuadSPI.
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227 (+) De-initialize the QuadSPI.
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234 * @brief Initializes the QSPI mode according to the specified parameters
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235 * in the QSPI_InitTypeDef and creates the associated handle.
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236 * @param hqspi: qspi handle
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237 * @retval HAL status
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239 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
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241 HAL_StatusTypeDef status = HAL_ERROR;
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243 /* Check the QSPI handle allocation */
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249 /* Check the parameters */
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250 assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
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251 assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
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252 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
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253 assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
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254 assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
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255 assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
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256 assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
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257 assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
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258 assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
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260 /* Process locked */
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263 if(hqspi->State == HAL_QSPI_STATE_RESET)
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265 /* Init the low level hardware : GPIO, CLOCK */
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266 HAL_QSPI_MspInit(hqspi);
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268 /* Configure the default timeout for the QSPI memory access */
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269 HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
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272 /* Configure QSPI FIFO Threshold */
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273 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));
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275 /* Wait till BUSY flag reset */
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276 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
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278 if(status == HAL_OK)
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281 /* Configure QSPI Clock Prescaler and Sample Shift */
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282 MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));
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284 /* Configure QSPI Flash Size, CS High Time and Clock Mode */
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285 MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
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286 ((hqspi->Init.FlashSize << 16) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
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288 /* Enable the QSPI peripheral */
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289 __HAL_QSPI_ENABLE(hqspi);
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291 /* Set QSPI error code to none */
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292 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
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294 /* Initialize the QSPI state */
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295 hqspi->State = HAL_QSPI_STATE_READY;
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299 __HAL_UNLOCK(hqspi);
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301 /* Return function status */
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306 * @brief DeInitializes the QSPI peripheral
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307 * @param hqspi: qspi handle
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308 * @retval HAL status
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310 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
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312 /* Check the QSPI handle allocation */
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318 /* Process locked */
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321 /* Disable the QSPI Peripheral Clock */
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322 __HAL_QSPI_DISABLE(hqspi);
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324 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
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325 HAL_QSPI_MspDeInit(hqspi);
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327 /* Set QSPI error code to none */
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328 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
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330 /* Initialize the QSPI state */
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331 hqspi->State = HAL_QSPI_STATE_RESET;
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334 __HAL_UNLOCK(hqspi);
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340 * @brief QSPI MSP Init
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341 * @param hqspi: QSPI handle
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344 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
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346 /* NOTE : This function should not be modified, when the callback is needed,
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347 the HAL_QSPI_MspInit can be implemented in the user file
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352 * @brief QSPI MSP DeInit
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353 * @param hqspi: QSPI handle
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356 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
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358 /* NOTE : This function should not be modified, when the callback is needed,
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359 the HAL_QSPI_MspDeInit can be implemented in the user file
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367 /** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
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368 * @brief QSPI Transmit/Receive functions
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371 ===============================================================================
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372 ##### I/O operation functions #####
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373 ===============================================================================
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375 This subsection provides a set of functions allowing to :
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376 (+) Handle the interrupts.
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377 (+) Handle the command sequence.
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378 (+) Transmit data in blocking, interrupt or DMA mode.
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379 (+) Receive data in blocking, interrupt or DMA mode.
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380 (+) Manage the auto-polling functional mode.
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381 (+) Manage the memory-mapped functional mode.
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388 * @brief This function handles QSPI interrupt request.
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389 * @param hqspi: QSPI handle
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392 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
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394 __IO uint32_t *data_reg;
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395 uint32_t flag = 0, itsource = 0;
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397 /* QSPI FIFO Threshold interrupt occurred ----------------------------------*/
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398 flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT);
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399 itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_FT);
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401 if((flag != RESET) && (itsource != RESET))
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403 data_reg = &hqspi->Instance->DR;
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405 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
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407 /* Transmission process */
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408 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
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410 if (hqspi->TxXferCount > 0)
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412 /* Fill the FIFO until it is full */
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413 *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
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414 hqspi->TxXferCount--;
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418 /* No more data available for the transfer */
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423 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
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425 /* Receiving Process */
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426 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
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428 if (hqspi->RxXferCount > 0)
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430 /* Read the FIFO until it is empty */
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431 *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
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432 hqspi->RxXferCount--;
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436 /* All data have been received for the transfer */
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442 /* FIFO Threshold callback */
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443 HAL_QSPI_FifoThresholdCallback(hqspi);
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446 /* QSPI Transfer Complete interrupt occurred -------------------------------*/
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447 flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TC);
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448 itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TC);
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450 if((flag != RESET) && (itsource != RESET))
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452 /* Clear interrupt */
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453 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
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455 /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
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456 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
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458 /* Transfer complete callback */
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459 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
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461 /* Clear Busy bit */
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462 HAL_QSPI_Abort(hqspi);
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464 /* TX Complete callback */
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465 HAL_QSPI_TxCpltCallback(hqspi);
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467 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
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469 data_reg = &hqspi->Instance->DR;
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470 while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
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472 if (hqspi->RxXferCount > 0)
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474 /* Read the last data received in the FIFO until it is empty */
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475 *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
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476 hqspi->RxXferCount--;
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480 /* All data have been received for the transfer */
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485 /* Workaround - Extra data written in the FIFO at the end of a read transfer */
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486 HAL_QSPI_Abort(hqspi);
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488 /* RX Complete callback */
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489 HAL_QSPI_RxCpltCallback(hqspi);
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491 else if(hqspi->State == HAL_QSPI_STATE_BUSY)
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493 /* Command Complete callback */
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494 HAL_QSPI_CmdCpltCallback(hqspi);
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497 /* Change state of QSPI */
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498 hqspi->State = HAL_QSPI_STATE_READY;
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501 /* QSPI Status Match interrupt occurred ------------------------------------*/
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502 flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_SM);
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503 itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_SM);
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505 if((flag != RESET) && (itsource != RESET))
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507 /* Clear interrupt */
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508 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
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510 /* Check if the automatic poll mode stop is activated */
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511 if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
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513 /* Disable the QSPI FIFO Threshold, Transfer Error and Status Match Interrupts */
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514 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TE);
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516 /* Change state of QSPI */
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517 hqspi->State = HAL_QSPI_STATE_READY;
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520 /* Status match callback */
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521 HAL_QSPI_StatusMatchCallback(hqspi);
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524 /* QSPI Transfer Error interrupt occurred ----------------------------------*/
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525 flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TE);
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526 itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TE);
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528 if((flag != RESET) && (itsource != RESET))
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530 /* Clear interrupt */
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531 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE);
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533 /* Disable all the QSPI Interrupts */
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534 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
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536 /* Set error code */
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537 hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
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539 /* Change state of QSPI */
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540 hqspi->State = HAL_QSPI_STATE_ERROR;
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542 /* Error callback */
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543 HAL_QSPI_ErrorCallback(hqspi);
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546 /* QSPI Time out interrupt occurred -----------------------------------------*/
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547 flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TO);
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548 itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TO);
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550 if((flag != RESET) && (itsource != RESET))
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552 /* Clear interrupt */
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553 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
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555 /* Time out callback */
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556 HAL_QSPI_TimeOutCallback(hqspi);
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561 * @brief Sets the command configuration.
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562 * @param hqspi: QSPI handle
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563 * @param cmd : structure that contains the command configuration information
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564 * @param Timeout : Time out duration
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565 * @note This function is used only in Indirect Read or Write Modes
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566 * @retval HAL status
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568 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
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570 HAL_StatusTypeDef status = HAL_ERROR;
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572 /* Check the parameters */
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573 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
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574 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
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576 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
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579 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
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580 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
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582 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
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585 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
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586 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
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588 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
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591 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
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592 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
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594 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
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595 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
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596 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
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598 /* Process locked */
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601 if(hqspi->State == HAL_QSPI_STATE_READY)
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603 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
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605 /* Update QSPI state */
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606 hqspi->State = HAL_QSPI_STATE_BUSY;
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608 /* Wait till BUSY flag reset */
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609 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
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611 if (status == HAL_OK)
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613 /* Call the configuration function */
\r
614 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
\r
616 if (cmd->DataMode == QSPI_DATA_NONE)
\r
618 /* When there is no data phase, the transfer start as soon as the configuration is done
\r
619 so wait until TC flag is set to go back in idle state */
\r
620 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
\r
622 status = HAL_TIMEOUT;
\r
626 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
\r
628 /* Update QSPI state */
\r
629 hqspi->State = HAL_QSPI_STATE_READY;
\r
635 /* Update QSPI state */
\r
636 hqspi->State = HAL_QSPI_STATE_READY;
\r
642 status = HAL_BUSY;
\r
645 /* Process unlocked */
\r
646 __HAL_UNLOCK(hqspi);
\r
648 /* Return function status */
\r
653 * @brief Sets the command configuration in interrupt mode.
\r
654 * @param hqspi: QSPI handle
\r
655 * @param cmd : structure that contains the command configuration information
\r
656 * @note This function is used only in Indirect Read or Write Modes
\r
657 * @retval HAL status
\r
659 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
\r
661 HAL_StatusTypeDef status = HAL_ERROR;
\r
663 /* Check the parameters */
\r
664 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
\r
665 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
\r
667 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
\r
670 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
\r
671 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
\r
673 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
\r
676 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
\r
677 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
\r
679 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
\r
682 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
\r
683 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
\r
685 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
\r
686 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
\r
687 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
\r
689 /* Process locked */
\r
692 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
694 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
696 /* Update QSPI state */
\r
697 hqspi->State = HAL_QSPI_STATE_BUSY;
\r
699 /* Wait till BUSY flag reset */
\r
700 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
\r
702 if (status == HAL_OK)
\r
704 if (cmd->DataMode == QSPI_DATA_NONE)
\r
706 /* When there is no data phase, the transfer start as soon as the configuration is done
\r
707 so activate TC and TE interrupts */
\r
708 /* Enable the QSPI Transfer Error Interrupt */
\r
709 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
\r
712 /* Call the configuration function */
\r
713 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
\r
715 if (cmd->DataMode != QSPI_DATA_NONE)
\r
717 /* Update QSPI state */
\r
718 hqspi->State = HAL_QSPI_STATE_READY;
\r
724 status = HAL_BUSY;
\r
727 /* Process unlocked */
\r
728 __HAL_UNLOCK(hqspi);
\r
730 /* Return function status */
\r
735 * @brief Transmit an amount of data in blocking mode.
\r
736 * @param hqspi: QSPI handle
\r
737 * @param pData: pointer to data buffer
\r
738 * @param Timeout : Time out duration
\r
739 * @note This function is used only in Indirect Write Mode
\r
740 * @retval HAL status
\r
742 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
\r
744 HAL_StatusTypeDef status = HAL_OK;
\r
745 __IO uint32_t *data_reg = &hqspi->Instance->DR;
\r
747 /* Process locked */
\r
750 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
754 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
757 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
\r
759 /* Configure counters and size of the handle */
\r
760 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
\r
761 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
\r
762 hqspi->pTxBuffPtr = pData;
\r
764 /* Configure QSPI: CCR register with functional as indirect write */
\r
765 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
\r
767 while(hqspi->TxXferCount > 0)
\r
769 /* Wait until FT flag is set to send data */
\r
770 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, Timeout) != HAL_OK)
\r
772 status = HAL_TIMEOUT;
\r
776 *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
\r
777 hqspi->TxXferCount--;
\r
780 if (status == HAL_OK)
\r
782 /* Wait until TC flag is set to go back in idle state */
\r
783 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
\r
785 status = HAL_TIMEOUT;
\r
789 /* Clear Transfer Complete bit */
\r
790 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
\r
792 /* Clear Busy bit */
\r
793 status = HAL_QSPI_Abort(hqspi);
\r
797 /* Update QSPI state */
\r
798 hqspi->State = HAL_QSPI_STATE_READY;
\r
802 status = HAL_ERROR;
\r
810 /* Process unlocked */
\r
811 __HAL_UNLOCK(hqspi);
\r
818 * @brief Receive an amount of data in blocking mode
\r
819 * @param hqspi: QSPI handle
\r
820 * @param pData: pointer to data buffer
\r
821 * @param Timeout : Time out duration
\r
822 * @note This function is used only in Indirect Read Mode
\r
823 * @retval HAL status
\r
825 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
\r
827 HAL_StatusTypeDef status = HAL_OK;
\r
828 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
\r
829 __IO uint32_t *data_reg = &hqspi->Instance->DR;
\r
831 /* Process locked */
\r
834 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
838 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
841 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
\r
843 /* Configure counters and size of the handle */
\r
844 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
\r
845 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
\r
846 hqspi->pRxBuffPtr = pData;
\r
848 /* Configure QSPI: CCR register with functional as indirect read */
\r
849 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
\r
851 /* Start the transfer by re-writing the address in AR register */
\r
852 WRITE_REG(hqspi->Instance->AR, addr_reg);
\r
854 while(hqspi->RxXferCount > 0)
\r
856 /* Wait until FT or TC flag is set to read received data */
\r
857 if(QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, Timeout) != HAL_OK)
\r
859 status = HAL_TIMEOUT;
\r
863 *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
\r
864 hqspi->RxXferCount--;
\r
867 if (status == HAL_OK)
\r
869 /* Wait until TC flag is set to go back in idle state */
\r
870 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
\r
872 status = HAL_TIMEOUT;
\r
876 /* Clear Transfer Complete bit */
\r
877 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
\r
879 /* Workaround - Extra data written in the FIFO at the end of a read transfer */
\r
880 status = HAL_QSPI_Abort(hqspi);
\r
884 /* Update QSPI state */
\r
885 hqspi->State = HAL_QSPI_STATE_READY;
\r
889 status = HAL_ERROR;
\r
897 /* Process unlocked */
\r
898 __HAL_UNLOCK(hqspi);
\r
904 * @brief Send an amount of data in interrupt mode
\r
905 * @param hqspi: QSPI handle
\r
906 * @param pData: pointer to data buffer
\r
907 * @note This function is used only in Indirect Write Mode
\r
908 * @retval HAL status
\r
910 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
\r
912 HAL_StatusTypeDef status = HAL_OK;
\r
914 /* Process locked */
\r
917 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
921 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
924 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
\r
926 /* Configure counters and size of the handle */
\r
927 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
\r
928 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
\r
929 hqspi->pTxBuffPtr = pData;
\r
931 /* Configure QSPI: CCR register with functional as indirect write */
\r
932 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
\r
934 /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
\r
935 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
\r
940 status = HAL_ERROR;
\r
948 /* Process unlocked */
\r
949 __HAL_UNLOCK(hqspi);
\r
955 * @brief Receive an amount of data in no-blocking mode with Interrupt
\r
956 * @param hqspi: QSPI handle
\r
957 * @param pData: pointer to data buffer
\r
958 * @note This function is used only in Indirect Read Mode
\r
959 * @retval HAL status
\r
961 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
\r
963 HAL_StatusTypeDef status = HAL_OK;
\r
964 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
\r
966 /* Process locked */
\r
969 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
973 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
976 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
\r
978 /* Configure counters and size of the handle */
\r
979 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
\r
980 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
\r
981 hqspi->pRxBuffPtr = pData;
\r
983 /* Configure QSPI: CCR register with functional as indirect read */
\r
984 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
\r
986 /* Start the transfer by re-writing the address in AR register */
\r
987 WRITE_REG(hqspi->Instance->AR, addr_reg);
\r
989 /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
\r
990 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
\r
994 status = HAL_ERROR;
\r
999 status = HAL_BUSY;
\r
1002 /* Process unlocked */
\r
1003 __HAL_UNLOCK(hqspi);
\r
1009 * @brief Sends an amount of data in non blocking mode with DMA.
\r
1010 * @param hqspi: QSPI handle
\r
1011 * @param pData: pointer to data buffer
\r
1012 * @note This function is used only in Indirect Write Mode
\r
1013 * @retval HAL status
\r
1015 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
\r
1017 HAL_StatusTypeDef status = HAL_OK;
\r
1020 /* Process locked */
\r
1021 __HAL_LOCK(hqspi);
\r
1023 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
1025 if(pData != NULL )
\r
1027 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
1029 /* Update state */
\r
1030 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
\r
1032 /* Configure counters and size of the handle */
\r
1033 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
\r
1034 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
\r
1035 hqspi->pTxBuffPtr = pData;
\r
1037 /* Configure QSPI: CCR register with functional mode as indirect write */
\r
1038 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
\r
1040 /* Set the QSPI DMA transfer complete callback */
\r
1041 hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
\r
1043 /* Set the QSPI DMA Half transfer complete callback */
\r
1044 hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
\r
1046 /* Set the DMA error callback */
\r
1047 hqspi->hdma->XferErrorCallback = QSPI_DMAError;
\r
1049 /* Configure the direction of the DMA */
\r
1050 hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
\r
1051 MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
\r
1053 /* Enable the QSPI transmit DMA Channel */
\r
1054 tmp = (uint32_t*)&pData;
\r
1055 HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
\r
1057 /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
\r
1058 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
\r
1067 status = HAL_BUSY;
\r
1070 /* Process unlocked */
\r
1071 __HAL_UNLOCK(hqspi);
\r
1077 * @brief Receives an amount of data in non blocking mode with DMA.
\r
1078 * @param hqspi: QSPI handle
\r
1079 * @param pData: pointer to data buffer.
\r
1080 * @note This function is used only in Indirect Read Mode
\r
1081 * @retval HAL status
\r
1083 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
\r
1085 HAL_StatusTypeDef status = HAL_OK;
\r
1087 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
\r
1089 /* Process locked */
\r
1090 __HAL_LOCK(hqspi);
\r
1092 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
1094 if(pData != NULL )
\r
1096 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
1098 /* Update state */
\r
1099 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
\r
1101 /* Configure counters and size of the handle */
\r
1102 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
\r
1103 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
\r
1104 hqspi->pRxBuffPtr = pData;
\r
1106 /* Set the QSPI DMA transfer complete callback */
\r
1107 hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
\r
1109 /* Set the QSPI DMA Half transfer complete callback */
\r
1110 hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
\r
1112 /* Set the DMA error callback */
\r
1113 hqspi->hdma->XferErrorCallback = QSPI_DMAError;
\r
1115 /* Configure the direction of the DMA */
\r
1116 hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
\r
1117 MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
\r
1119 /* Enable the DMA Channel */
\r
1120 tmp = (uint32_t*)&pData;
\r
1121 HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
\r
1123 /* Configure QSPI: CCR register with functional as indirect read */
\r
1124 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
\r
1126 /* Start the transfer by re-writing the address in AR register */
\r
1127 WRITE_REG(hqspi->Instance->AR, addr_reg);
\r
1129 /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
\r
1130 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
\r
1134 status = HAL_ERROR;
\r
1139 status = HAL_BUSY;
\r
1142 /* Process unlocked */
\r
1143 __HAL_UNLOCK(hqspi);
\r
1149 * @brief Configure the QSPI Automatic Polling Mode in blocking mode.
\r
1150 * @param hqspi: QSPI handle
\r
1151 * @param cmd: structure that contains the command configuration information.
\r
1152 * @param cfg: structure that contains the polling configuration information.
\r
1153 * @param Timeout : Time out duration
\r
1154 * @note This function is used only in Automatic Polling Mode
\r
1155 * @retval HAL status
\r
1157 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
\r
1159 HAL_StatusTypeDef status = HAL_ERROR;
\r
1161 /* Check the parameters */
\r
1162 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
\r
1163 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
\r
1165 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
\r
1168 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
\r
1169 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
\r
1171 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
\r
1174 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
\r
1175 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
\r
1177 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
\r
1180 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
\r
1181 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
\r
1183 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
\r
1184 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
\r
1185 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
\r
1187 assert_param(IS_QSPI_INTERVAL(cfg->Interval));
\r
1188 assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
\r
1189 assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
\r
1191 /* Process locked */
\r
1192 __HAL_LOCK(hqspi);
\r
1194 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
1197 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
1199 /* Update state */
\r
1200 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
\r
1202 /* Wait till BUSY flag reset */
\r
1203 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
\r
1205 if (status == HAL_OK)
\r
1207 /* Configure QSPI: PSMAR register with the status match value */
\r
1208 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
\r
1210 /* Configure QSPI: PSMKR register with the status mask value */
\r
1211 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
\r
1213 /* Configure QSPI: PIR register with the interval value */
\r
1214 WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
\r
1216 /* Configure QSPI: CR register with Match mode and Automatic stop enabled
\r
1217 (otherwise there will be an infinite loop in blocking mode) */
\r
1218 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
\r
1219 (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
\r
1221 /* Call the configuration function */
\r
1222 cmd->NbData = cfg->StatusBytesSize;
\r
1223 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
\r
1225 /* Wait until SM flag is set to go back in idle state */
\r
1226 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, Timeout) != HAL_OK)
\r
1228 status = HAL_TIMEOUT;
\r
1232 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
\r
1234 /* Update state */
\r
1235 hqspi->State = HAL_QSPI_STATE_READY;
\r
1241 status = HAL_BUSY;
\r
1243 /* Process unlocked */
\r
1244 __HAL_UNLOCK(hqspi);
\r
1246 /* Return function status */
\r
1251 * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
\r
1252 * @param hqspi: QSPI handle
\r
1253 * @param cmd: structure that contains the command configuration information.
\r
1254 * @param cfg: structure that contains the polling configuration information.
\r
1255 * @note This function is used only in Automatic Polling Mode
\r
1256 * @retval HAL status
\r
1258 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
\r
1260 HAL_StatusTypeDef status = HAL_ERROR;
\r
1262 /* Check the parameters */
\r
1263 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
\r
1264 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
\r
1266 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
\r
1269 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
\r
1270 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
\r
1272 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
\r
1275 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
\r
1276 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
\r
1278 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
\r
1281 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
\r
1282 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
\r
1284 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
\r
1285 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
\r
1286 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
\r
1288 assert_param(IS_QSPI_INTERVAL(cfg->Interval));
\r
1289 assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
\r
1290 assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
\r
1291 assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
\r
1293 /* Process locked */
\r
1294 __HAL_LOCK(hqspi);
\r
1296 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
1298 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
1300 /* Update state */
\r
1301 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
\r
1303 /* Wait till BUSY flag reset */
\r
1304 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
\r
1306 if (status == HAL_OK)
\r
1308 /* Configure QSPI: PSMAR register with the status match value */
\r
1309 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
\r
1311 /* Configure QSPI: PSMKR register with the status mask value */
\r
1312 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
\r
1314 /* Configure QSPI: PIR register with the interval value */
\r
1315 WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
\r
1317 /* Configure QSPI: CR register with Match mode and Automatic stop mode */
\r
1318 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
\r
1319 (cfg->MatchMode | cfg->AutomaticStop));
\r
1321 /* Call the configuration function */
\r
1322 cmd->NbData = cfg->StatusBytesSize;
\r
1323 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
\r
1325 /* Enable the QSPI Transfer Error, FIFO threshold and status match Interrupt */
\r
1326 __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_FT | QSPI_IT_SM | QSPI_IT_TE));
\r
1331 status = HAL_BUSY;
\r
1334 /* Process unlocked */
\r
1335 __HAL_UNLOCK(hqspi);
\r
1337 /* Return function status */
\r
1342 * @brief Configure the Memory Mapped mode.
\r
1343 * @param hqspi: QSPI handle
\r
1344 * @param cmd: structure that contains the command configuration information.
\r
1345 * @param cfg: structure that contains the memory mapped configuration information.
\r
1346 * @note This function is used only in Memory mapped Mode
\r
1347 * @retval HAL status
\r
1349 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
\r
1351 HAL_StatusTypeDef status = HAL_ERROR;
\r
1353 /* Check the parameters */
\r
1354 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
\r
1355 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
\r
1357 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
\r
1360 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
\r
1361 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
\r
1363 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
\r
1366 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
\r
1367 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
\r
1369 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
\r
1372 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
\r
1373 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
\r
1375 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
\r
1376 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
\r
1377 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
\r
1379 assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
\r
1381 /* Process locked */
\r
1382 __HAL_LOCK(hqspi);
\r
1384 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
1386 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
1388 /* Update state */
\r
1389 hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
\r
1391 /* Wait till BUSY flag reset */
\r
1392 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
\r
1394 if (status == HAL_OK)
\r
1396 /* Configure QSPI: CR register with time out counter enable */
\r
1397 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
\r
1399 if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
\r
1401 assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
\r
1403 /* Configure QSPI: LPTR register with the low-power time out value */
\r
1404 WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
\r
1406 /* Enable the QSPI TimeOut Interrupt */
\r
1407 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
\r
1410 /* Call the configuration function */
\r
1411 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
\r
1417 status = HAL_BUSY;
\r
1421 /* Process unlocked */
\r
1422 __HAL_UNLOCK(hqspi);
\r
1424 /* Return function status */
\r
1429 * @brief Transfer Error callbacks
\r
1430 * @param hqspi: QSPI handle
\r
1433 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
\r
1435 /* NOTE : This function Should not be modified, when the callback is needed,
\r
1436 the HAL_QSPI_ErrorCallback could be implemented in the user file
\r
1441 * @brief Command completed callbacks.
\r
1442 * @param hqspi: QSPI handle
\r
1445 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
\r
1447 /* NOTE: This function Should not be modified, when the callback is needed,
\r
1448 the HAL_QSPI_CmdCpltCallback could be implemented in the user file
\r
1453 * @brief Rx Transfer completed callbacks.
\r
1454 * @param hqspi: QSPI handle
\r
1457 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
\r
1459 /* NOTE: This function Should not be modified, when the callback is needed,
\r
1460 the HAL_QSPI_RxCpltCallback could be implemented in the user file
\r
1465 * @brief Tx Transfer completed callbacks.
\r
1466 * @param hqspi: QSPI handle
\r
1469 __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
\r
1471 /* NOTE: This function Should not be modified, when the callback is needed,
\r
1472 the HAL_QSPI_TxCpltCallback could be implemented in the user file
\r
1477 * @brief Rx Half Transfer completed callbacks.
\r
1478 * @param hqspi: QSPI handle
\r
1481 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
\r
1483 /* NOTE: This function Should not be modified, when the callback is needed,
\r
1484 the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
\r
1489 * @brief Tx Half Transfer completed callbacks.
\r
1490 * @param hqspi: QSPI handle
\r
1493 __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
\r
1495 /* NOTE: This function Should not be modified, when the callback is needed,
\r
1496 the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
\r
1501 * @brief FIFO Threshold callbacks
\r
1502 * @param hqspi: QSPI handle
\r
1505 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
\r
1507 /* NOTE : This function Should not be modified, when the callback is needed,
\r
1508 the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
\r
1513 * @brief Status Match callbacks
\r
1514 * @param hqspi: QSPI handle
\r
1517 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
\r
1519 /* NOTE : This function Should not be modified, when the callback is needed,
\r
1520 the HAL_QSPI_StatusMatchCallback could be implemented in the user file
\r
1525 * @brief Timeout callbacks
\r
1526 * @param hqspi: QSPI handle
\r
1529 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
\r
1531 /* NOTE : This function Should not be modified, when the callback is needed,
\r
1532 the HAL_QSPI_TimeOutCallback could be implemented in the user file
\r
1540 /** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
\r
1541 * @brief QSPI control and State functions
\r
1544 ===============================================================================
\r
1545 ##### Peripheral Control and State functions #####
\r
1546 ===============================================================================
\r
1548 This subsection provides a set of functions allowing to :
\r
1549 (+) Check in run-time the state of the driver.
\r
1550 (+) Check the error code set during last operation.
\r
1551 (+) Abort any operation.
\r
1558 * @brief Return the QSPI state.
\r
1559 * @param hqspi: QSPI handle
\r
1560 * @retval HAL state
\r
1562 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
\r
1564 return hqspi->State;
\r
1568 * @brief Return the QSPI error code
\r
1569 * @param hqspi: QSPI handle
\r
1570 * @retval QSPI Error Code
\r
1572 uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
\r
1574 return hqspi->ErrorCode;
\r
1578 * @brief Abort the current transmission
\r
1579 * @param hqspi: QSPI handle
\r
1580 * @retval HAL status
\r
1582 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
\r
1584 HAL_StatusTypeDef status = HAL_ERROR;
\r
1586 /* Configure QSPI: CR register with Abort request */
\r
1587 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
\r
1589 /* Wait until TC flag is set to go back in idle state */
\r
1590 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
\r
1592 status = HAL_TIMEOUT;
\r
1596 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
\r
1598 /* Wait until BUSY flag is reset */
\r
1599 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
\r
1601 /* Update state */
\r
1602 hqspi->State = HAL_QSPI_STATE_READY;
\r
1608 /** @brief Set QSPI timeout
\r
1609 * @param hqspi: QSPI handle.
\r
1610 * @param Timeout: Timeout for the QSPI memory access.
\r
1613 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
\r
1615 hqspi->Timeout = Timeout;
\r
1622 /* Private functions ---------------------------------------------------------*/
\r
1625 * @brief DMA QSPI receive process complete callback.
\r
1626 * @param hdma: DMA handle
\r
1629 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
\r
1631 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
1632 hqspi->RxXferCount = 0;
\r
1634 /* Wait for QSPI TC Flag */
\r
1635 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
\r
1637 /* Time out Occurred */
\r
1638 HAL_QSPI_ErrorCallback(hqspi);
\r
1642 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
\r
1643 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
\r
1645 /* Disable the DMA channel */
\r
1646 HAL_DMA_Abort(hdma);
\r
1648 /* Clear Transfer Complete bit */
\r
1649 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
\r
1651 /* Workaround - Extra data written in the FIFO at the end of a read transfer */
\r
1652 HAL_QSPI_Abort(hqspi);
\r
1654 /* Update state */
\r
1655 hqspi->State = HAL_QSPI_STATE_READY;
\r
1657 HAL_QSPI_RxCpltCallback(hqspi);
\r
1662 * @brief DMA QSPI transmit process complete callback.
\r
1663 * @param hdma: DMA handle
\r
1666 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
\r
1668 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
1669 hqspi->TxXferCount = 0;
\r
1671 /* Wait for QSPI TC Flag */
\r
1672 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
\r
1674 /* Time out Occurred */
\r
1675 HAL_QSPI_ErrorCallback(hqspi);
\r
1679 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
\r
1680 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
\r
1682 /* Disable the DMA channel */
\r
1683 HAL_DMA_Abort(hdma);
\r
1685 /* Clear Transfer Complete bit */
\r
1686 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
\r
1688 /* Clear Busy bit */
\r
1689 HAL_QSPI_Abort(hqspi);
\r
1691 /* Update state */
\r
1692 hqspi->State = HAL_QSPI_STATE_READY;
\r
1694 HAL_QSPI_TxCpltCallback(hqspi);
\r
1699 * @brief DMA QSPI receive process half complete callback
\r
1700 * @param hdma : DMA handle
\r
1703 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
\r
1705 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
\r
1707 HAL_QSPI_RxHalfCpltCallback(hqspi);
\r
1711 * @brief DMA QSPI transmit process half complete callback
\r
1712 * @param hdma : DMA handle
\r
1715 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
\r
1717 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
\r
1719 HAL_QSPI_TxHalfCpltCallback(hqspi);
\r
1723 * @brief DMA QSPI communication error callback.
\r
1724 * @param hdma: DMA handle
\r
1727 static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
\r
1729 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
1731 hqspi->RxXferCount = 0;
\r
1732 hqspi->TxXferCount = 0;
\r
1733 hqspi->State = HAL_QSPI_STATE_ERROR;
\r
1734 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
\r
1736 HAL_QSPI_ErrorCallback(hqspi);
\r
1740 * @brief This function wait a flag state until time out.
\r
1741 * @param hqspi: QSPI handle
\r
1742 * @param Flag: Flag checked
\r
1743 * @param State: Value of the flag expected
\r
1744 * @param Timeout: Duration of the time out
\r
1745 * @retval HAL status
\r
1747 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
\r
1748 FlagStatus State, uint32_t Timeout)
\r
1750 uint32_t tickstart = HAL_GetTick();
\r
1752 /* Wait until flag is in expected state */
\r
1753 while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
\r
1755 /* Check for the Timeout */
\r
1756 if (Timeout != HAL_MAX_DELAY)
\r
1758 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
\r
1760 hqspi->State = HAL_QSPI_STATE_ERROR;
\r
1761 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
\r
1763 return HAL_TIMEOUT;
\r
1771 * @brief This function configures the communication registers
\r
1772 * @param hqspi: QSPI handle
\r
1773 * @param cmd: structure that contains the command configuration information
\r
1774 * @param FunctionalMode: functional mode to configured
\r
1775 * This parameter can be a value of @ref QSPI_FunctionalMode
\r
1776 * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
\r
1777 * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
\r
1778 * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
\r
1779 * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
\r
1782 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
\r
1784 assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
\r
1786 if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
\r
1788 /* Configure QSPI: DLR register with the number of data to read or write */
\r
1789 WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
\r
1792 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
\r
1794 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
\r
1796 /* Configure QSPI: ABR register with alternate bytes value */
\r
1797 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
\r
1799 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
\r
1801 /*---- Command with instruction, address and alternate bytes ----*/
\r
1802 /* Configure QSPI: CCR register with all communications parameters */
\r
1803 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
\r
1804 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
\r
1805 cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
\r
1806 cmd->InstructionMode | cmd->Instruction | FunctionalMode));
\r
1808 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
\r
1810 /* Configure QSPI: AR register with address value */
\r
1811 WRITE_REG(hqspi->Instance->AR, cmd->Address);
\r
1816 /*---- Command with instruction and alternate bytes ----*/
\r
1817 /* Configure QSPI: CCR register with all communications parameters */
\r
1818 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
\r
1819 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
\r
1820 cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
\r
1821 cmd->Instruction | FunctionalMode));
\r
1826 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
\r
1828 /*---- Command with instruction and address ----*/
\r
1829 /* Configure QSPI: CCR register with all communications parameters */
\r
1830 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
\r
1831 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
\r
1832 cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
\r
1833 cmd->Instruction | FunctionalMode));
\r
1835 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
\r
1837 /* Configure QSPI: AR register with address value */
\r
1838 WRITE_REG(hqspi->Instance->AR, cmd->Address);
\r
1843 /*---- Command with only instruction ----*/
\r
1844 /* Configure QSPI: CCR register with all communications parameters */
\r
1845 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
\r
1846 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
\r
1847 cmd->AddressMode | cmd->InstructionMode | cmd->Instruction |
\r
1854 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
\r
1856 /* Configure QSPI: ABR register with alternate bytes value */
\r
1857 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
\r
1859 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
\r
1861 /*---- Command with address and alternate bytes ----*/
\r
1862 /* Configure QSPI: CCR register with all communications parameters */
\r
1863 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
\r
1864 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
\r
1865 cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
\r
1866 cmd->InstructionMode | FunctionalMode));
\r
1868 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
\r
1870 /* Configure QSPI: AR register with address value */
\r
1871 WRITE_REG(hqspi->Instance->AR, cmd->Address);
\r
1876 /*---- Command with only alternate bytes ----*/
\r
1877 /* Configure QSPI: CCR register with all communications parameters */
\r
1878 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
\r
1879 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
\r
1880 cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
\r
1886 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
\r
1888 /*---- Command with only address ----*/
\r
1889 /* Configure QSPI: CCR register with all communications parameters */
\r
1890 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
\r
1891 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
\r
1892 cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
\r
1895 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
\r
1897 /* Configure QSPI: AR register with address value */
\r
1898 WRITE_REG(hqspi->Instance->AR, cmd->Address);
\r
1903 /*---- Command with only data phase ----*/
\r
1904 if (cmd->DataMode != QSPI_DATA_NONE)
\r
1906 /* Configure QSPI: CCR register with all communications parameters */
\r
1907 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
\r
1908 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
\r
1909 cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
\r
1919 #endif /* HAL_QSPI_MODULE_ENABLED */
\r
1928 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r