2 ******************************************************************************
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3 * @file stm32f7xx_hal_qspi.c
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4 * @author MCD Application Team
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7 * @brief QSPI HAL module driver.
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9 * This file provides firmware functions to manage the following
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10 * functionalities of the QuadSPI interface (QSPI).
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11 * + Initialization and de-initialization functions
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12 * + Indirect functional mode management
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13 * + Memory-mapped functional mode management
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14 * + Auto-polling functional mode management
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15 * + Interrupts and flags management
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16 * + DMA channel configuration for indirect functional mode
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17 * + Errors management and abort functionality
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21 ===============================================================================
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22 ##### How to use this driver #####
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23 ===============================================================================
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25 *** Initialization ***
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26 ======================
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28 (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
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29 (+) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
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30 (+) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
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31 (+) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
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32 (+) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
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33 (+) If interrupt mode is used, enable and configure QuadSPI global
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34 interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
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35 (+) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
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36 with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
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37 link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
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38 DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
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39 (#) Configure the flash size, the clock prescaler, the fifo threshold, the
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40 clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
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42 *** Indirect functional mode ***
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43 ================================
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45 (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
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47 (+) Instruction phase : the mode used and if present the instruction opcode.
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48 (+) Address phase : the mode used and if present the size and the address value.
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49 (+) Alternate-bytes phase : the mode used and if present the size and the alternate
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51 (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
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52 (+) Data phase : the mode used and if present the number of bytes.
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53 (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
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55 (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
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56 (#) If no data is required for the command, it is sent directly to the memory :
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57 (+) In polling mode, the output of the function is done when the transfer is complete.
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58 (+) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
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59 (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
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60 HAL_QSPI_Transmit_IT() after the command configuration :
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61 (+) In polling mode, the output of the function is done when the transfer is complete.
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62 (+) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
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63 is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
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64 (+) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
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65 HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
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66 (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
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67 HAL_QSPI_Receive_IT() after the command configuration :
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68 (+) In polling mode, the output of the function is done when the transfer is complete.
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69 (+) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
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70 is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
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71 (+) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
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72 HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
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74 *** Auto-polling functional mode ***
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75 ====================================
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77 (#) Configure the command sequence and the auto-polling functional mode using the
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78 HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
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79 (+) Instruction phase : the mode used and if present the instruction opcode.
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80 (+) Address phase : the mode used and if present the size and the address value.
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81 (+) Alternate-bytes phase : the mode used and if present the size and the alternate
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83 (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
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84 (+) Data phase : the mode used.
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85 (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
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87 (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
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88 (+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
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89 the polling interval and the automatic stop activation.
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90 (#) After the configuration :
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91 (+) In polling mode, the output of the function is done when the status match is reached. The
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92 automatic stop is activated to avoid an infinite loop.
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93 (+) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
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95 *** Memory-mapped functional mode ***
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96 =====================================
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98 (#) Configure the command sequence and the memory-mapped functional mode using the
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99 HAL_QSPI_MemoryMapped() functions :
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100 (+) Instruction phase : the mode used and if present the instruction opcode.
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101 (+) Address phase : the mode used and the size.
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102 (+) Alternate-bytes phase : the mode used and if present the size and the alternate
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104 (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
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105 (+) Data phase : the mode used.
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106 (+) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
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108 (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
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109 (+) The timeout activation and the timeout period.
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110 (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
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111 the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
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113 *** Errors management and abort functionality ***
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114 ==================================================
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116 (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
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117 (#) HAL_QSPI_Abort() function aborts any on-going operation and flushes the fifo.
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118 (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
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120 *** Workarounds linked to Silicon Limitation ***
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121 ====================================================
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123 (#) Workarounds Implemented inside HAL Driver
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124 (+) Extra data written in the FIFO at the end of a read transfer
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127 ******************************************************************************
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130 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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132 * Redistribution and use in source and binary forms, with or without modification,
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133 * are permitted provided that the following conditions are met:
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134 * 1. Redistributions of source code must retain the above copyright notice,
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135 * this list of conditions and the following disclaimer.
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136 * 2. Redistributions in binary form must reproduce the above copyright notice,
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137 * this list of conditions and the following disclaimer in the documentation
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138 * and/or other materials provided with the distribution.
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139 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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140 * may be used to endorse or promote products derived from this software
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141 * without specific prior written permission.
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143 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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144 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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145 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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146 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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147 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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148 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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149 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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150 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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151 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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152 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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154 ******************************************************************************
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157 /* Includes ------------------------------------------------------------------*/
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158 #include "stm32f7xx_hal.h"
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160 /** @addtogroup STM32F7xx_HAL_Driver
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164 /** @defgroup QSPI QSPI
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165 * @brief HAL QSPI module driver
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168 #ifdef HAL_QSPI_MODULE_ENABLED
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170 /* Private typedef -----------------------------------------------------------*/
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171 /* Private define ------------------------------------------------------------*/
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172 /** @addtogroup QSPI_Private_Constants
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175 #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!<Indirect write mode*/
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176 #define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
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177 #define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
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178 #define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/
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183 /* Private macro -------------------------------------------------------------*/
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184 /** @addtogroup QSPI_Private_Macros QSPI Private Macros
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187 #define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
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188 ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \
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189 ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \
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190 ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
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195 /* Private variables ---------------------------------------------------------*/
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196 /* Private function prototypes -----------------------------------------------*/
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197 /** @addtogroup QSPI_Private_Functions QSPI Private Functions
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200 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
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201 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
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202 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
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203 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
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204 static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
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205 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);
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206 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
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211 /* Exported functions ---------------------------------------------------------*/
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213 /** @defgroup QSPI_Exported_Functions QSPI Exported Functions
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217 /** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
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218 * @brief Initialization and Configuration functions
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221 ===============================================================================
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222 ##### Initialization and Configuration functions #####
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223 ===============================================================================
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225 This subsection provides a set of functions allowing to :
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226 (+) Initialize the QuadSPI.
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227 (+) De-initialize the QuadSPI.
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234 * @brief Initializes the QSPI mode according to the specified parameters
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235 * in the QSPI_InitTypeDef and creates the associated handle.
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236 * @param hqspi: qspi handle
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237 * @retval HAL status
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239 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
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241 HAL_StatusTypeDef status = HAL_ERROR;
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243 /* Check the QSPI handle allocation */
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249 /* Check the parameters */
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250 assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
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251 assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
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252 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
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253 assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
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254 assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
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255 assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
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256 assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
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257 assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
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259 if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
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261 assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
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264 /* Process locked */
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267 if(hqspi->State == HAL_QSPI_STATE_RESET)
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269 /* Allocate lock resource and initialize it */
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270 hqspi->Lock = HAL_UNLOCKED;
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272 /* Init the low level hardware : GPIO, CLOCK */
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273 HAL_QSPI_MspInit(hqspi);
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275 /* Configure the default timeout for the QSPI memory access */
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276 HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
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279 /* Configure QSPI FIFO Threshold */
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280 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));
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282 /* Wait till BUSY flag reset */
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283 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
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285 if(status == HAL_OK)
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288 /* Configure QSPI Clock Prescaler and Sample Shift */
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289 MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));
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291 /* Configure QSPI Flash Size, CS High Time and Clock Mode */
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292 MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
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293 ((hqspi->Init.FlashSize << 16) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
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295 /* Enable the QSPI peripheral */
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296 __HAL_QSPI_ENABLE(hqspi);
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298 /* Set QSPI error code to none */
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299 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
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301 /* Initialize the QSPI state */
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302 hqspi->State = HAL_QSPI_STATE_READY;
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306 __HAL_UNLOCK(hqspi);
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308 /* Return function status */
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313 * @brief DeInitializes the QSPI peripheral
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314 * @param hqspi: qspi handle
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315 * @retval HAL status
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317 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
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319 /* Check the QSPI handle allocation */
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325 /* Process locked */
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328 /* Disable the QSPI Peripheral Clock */
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329 __HAL_QSPI_DISABLE(hqspi);
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331 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
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332 HAL_QSPI_MspDeInit(hqspi);
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334 /* Set QSPI error code to none */
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335 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
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337 /* Initialize the QSPI state */
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338 hqspi->State = HAL_QSPI_STATE_RESET;
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341 __HAL_UNLOCK(hqspi);
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347 * @brief QSPI MSP Init
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348 * @param hqspi: QSPI handle
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351 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
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353 /* NOTE : This function should not be modified, when the callback is needed,
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354 the HAL_QSPI_MspInit can be implemented in the user file
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359 * @brief QSPI MSP DeInit
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360 * @param hqspi: QSPI handle
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363 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
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365 /* NOTE : This function should not be modified, when the callback is needed,
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366 the HAL_QSPI_MspDeInit can be implemented in the user file
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374 /** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
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375 * @brief QSPI Transmit/Receive functions
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378 ===============================================================================
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379 ##### I/O operation functions #####
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380 ===============================================================================
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382 This subsection provides a set of functions allowing to :
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383 (+) Handle the interrupts.
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384 (+) Handle the command sequence.
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385 (+) Transmit data in blocking, interrupt or DMA mode.
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386 (+) Receive data in blocking, interrupt or DMA mode.
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387 (+) Manage the auto-polling functional mode.
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388 (+) Manage the memory-mapped functional mode.
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395 * @brief This function handles QSPI interrupt request.
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396 * @param hqspi: QSPI handle
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399 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
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401 __IO uint32_t *data_reg;
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402 uint32_t flag = 0, itsource = 0;
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404 /* QSPI FIFO Threshold interrupt occurred ----------------------------------*/
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405 flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT);
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406 itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_FT);
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408 if((flag != RESET) && (itsource != RESET))
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410 data_reg = &hqspi->Instance->DR;
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412 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
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414 /* Transmission process */
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415 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
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417 if (hqspi->TxXferCount > 0)
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419 /* Fill the FIFO until it is full */
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420 *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
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421 hqspi->TxXferCount--;
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425 /* No more data available for the transfer */
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430 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
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432 /* Receiving Process */
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433 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
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435 if (hqspi->RxXferCount > 0)
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437 /* Read the FIFO until it is empty */
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438 *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
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439 hqspi->RxXferCount--;
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443 /* All data have been received for the transfer */
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449 /* FIFO Threshold callback */
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450 HAL_QSPI_FifoThresholdCallback(hqspi);
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453 /* QSPI Transfer Complete interrupt occurred -------------------------------*/
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454 flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TC);
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455 itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TC);
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457 if((flag != RESET) && (itsource != RESET))
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459 /* Clear interrupt */
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460 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
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462 /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
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463 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
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465 /* Transfer complete callback */
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466 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
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468 /* Clear Busy bit */
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469 HAL_QSPI_Abort(hqspi);
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471 /* TX Complete callback */
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472 HAL_QSPI_TxCpltCallback(hqspi);
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474 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
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476 data_reg = &hqspi->Instance->DR;
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477 while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
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479 if (hqspi->RxXferCount > 0)
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481 /* Read the last data received in the FIFO until it is empty */
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482 *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
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483 hqspi->RxXferCount--;
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487 /* All data have been received for the transfer */
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492 /* Workaround - Extra data written in the FIFO at the end of a read transfer */
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493 HAL_QSPI_Abort(hqspi);
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495 /* RX Complete callback */
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496 HAL_QSPI_RxCpltCallback(hqspi);
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498 else if(hqspi->State == HAL_QSPI_STATE_BUSY)
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500 /* Command Complete callback */
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501 HAL_QSPI_CmdCpltCallback(hqspi);
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504 /* Change state of QSPI */
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505 hqspi->State = HAL_QSPI_STATE_READY;
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508 /* QSPI Status Match interrupt occurred ------------------------------------*/
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509 flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_SM);
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510 itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_SM);
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512 if((flag != RESET) && (itsource != RESET))
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514 /* Clear interrupt */
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515 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
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517 /* Check if the automatic poll mode stop is activated */
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518 if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
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520 /* Disable the QSPI FIFO Threshold, Transfer Error and Status Match Interrupts */
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521 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TE);
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523 /* Change state of QSPI */
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524 hqspi->State = HAL_QSPI_STATE_READY;
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527 /* Status match callback */
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528 HAL_QSPI_StatusMatchCallback(hqspi);
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531 /* QSPI Transfer Error interrupt occurred ----------------------------------*/
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532 flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TE);
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533 itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TE);
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535 if((flag != RESET) && (itsource != RESET))
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537 /* Clear interrupt */
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538 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE);
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540 /* Disable all the QSPI Interrupts */
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541 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
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543 /* Set error code */
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544 hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
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546 /* Change state of QSPI */
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547 hqspi->State = HAL_QSPI_STATE_ERROR;
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549 /* Error callback */
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550 HAL_QSPI_ErrorCallback(hqspi);
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553 /* QSPI Time out interrupt occurred -----------------------------------------*/
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554 flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TO);
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555 itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TO);
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557 if((flag != RESET) && (itsource != RESET))
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559 /* Clear interrupt */
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560 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
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562 /* Time out callback */
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563 HAL_QSPI_TimeOutCallback(hqspi);
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568 * @brief Sets the command configuration.
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569 * @param hqspi: QSPI handle
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570 * @param cmd : structure that contains the command configuration information
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571 * @param Timeout : Time out duration
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572 * @note This function is used only in Indirect Read or Write Modes
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573 * @retval HAL status
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575 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
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577 HAL_StatusTypeDef status = HAL_ERROR;
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579 /* Check the parameters */
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580 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
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581 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
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583 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
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586 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
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587 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
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589 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
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592 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
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593 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
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595 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
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598 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
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599 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
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601 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
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602 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
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603 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
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605 /* Process locked */
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608 if(hqspi->State == HAL_QSPI_STATE_READY)
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610 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
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612 /* Update QSPI state */
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613 hqspi->State = HAL_QSPI_STATE_BUSY;
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615 /* Wait till BUSY flag reset */
\r
616 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
\r
618 if (status == HAL_OK)
\r
620 /* Call the configuration function */
\r
621 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
\r
623 if (cmd->DataMode == QSPI_DATA_NONE)
\r
625 /* When there is no data phase, the transfer start as soon as the configuration is done
\r
626 so wait until TC flag is set to go back in idle state */
\r
627 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
\r
629 status = HAL_TIMEOUT;
\r
633 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
\r
635 /* Update QSPI state */
\r
636 hqspi->State = HAL_QSPI_STATE_READY;
\r
642 /* Update QSPI state */
\r
643 hqspi->State = HAL_QSPI_STATE_READY;
\r
649 status = HAL_BUSY;
\r
652 /* Process unlocked */
\r
653 __HAL_UNLOCK(hqspi);
\r
655 /* Return function status */
\r
660 * @brief Sets the command configuration in interrupt mode.
\r
661 * @param hqspi: QSPI handle
\r
662 * @param cmd : structure that contains the command configuration information
\r
663 * @note This function is used only in Indirect Read or Write Modes
\r
664 * @retval HAL status
\r
666 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
\r
668 HAL_StatusTypeDef status = HAL_ERROR;
\r
670 /* Check the parameters */
\r
671 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
\r
672 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
\r
674 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
\r
677 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
\r
678 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
\r
680 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
\r
683 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
\r
684 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
\r
686 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
\r
689 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
\r
690 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
\r
692 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
\r
693 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
\r
694 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
\r
696 /* Process locked */
\r
699 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
701 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
703 /* Update QSPI state */
\r
704 hqspi->State = HAL_QSPI_STATE_BUSY;
\r
706 /* Wait till BUSY flag reset */
\r
707 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
\r
709 if (status == HAL_OK)
\r
711 if (cmd->DataMode == QSPI_DATA_NONE)
\r
713 /* When there is no data phase, the transfer start as soon as the configuration is done
\r
714 so activate TC and TE interrupts */
\r
715 /* Enable the QSPI Transfer Error Interrupt */
\r
716 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
\r
719 /* Call the configuration function */
\r
720 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
\r
722 if (cmd->DataMode != QSPI_DATA_NONE)
\r
724 /* Update QSPI state */
\r
725 hqspi->State = HAL_QSPI_STATE_READY;
\r
731 status = HAL_BUSY;
\r
734 /* Process unlocked */
\r
735 __HAL_UNLOCK(hqspi);
\r
737 /* Return function status */
\r
742 * @brief Transmit an amount of data in blocking mode.
\r
743 * @param hqspi: QSPI handle
\r
744 * @param pData: pointer to data buffer
\r
745 * @param Timeout : Time out duration
\r
746 * @note This function is used only in Indirect Write Mode
\r
747 * @retval HAL status
\r
749 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
\r
751 HAL_StatusTypeDef status = HAL_OK;
\r
752 __IO uint32_t *data_reg = &hqspi->Instance->DR;
\r
754 /* Process locked */
\r
757 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
761 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
764 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
\r
766 /* Configure counters and size of the handle */
\r
767 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
\r
768 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
\r
769 hqspi->pTxBuffPtr = pData;
\r
771 /* Configure QSPI: CCR register with functional as indirect write */
\r
772 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
\r
774 while(hqspi->TxXferCount > 0)
\r
776 /* Wait until FT flag is set to send data */
\r
777 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, Timeout) != HAL_OK)
\r
779 status = HAL_TIMEOUT;
\r
783 *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
\r
784 hqspi->TxXferCount--;
\r
787 if (status == HAL_OK)
\r
789 /* Wait until TC flag is set to go back in idle state */
\r
790 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
\r
792 status = HAL_TIMEOUT;
\r
796 /* Clear Transfer Complete bit */
\r
797 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
\r
799 /* Clear Busy bit */
\r
800 status = HAL_QSPI_Abort(hqspi);
\r
804 /* Update QSPI state */
\r
805 hqspi->State = HAL_QSPI_STATE_READY;
\r
809 status = HAL_ERROR;
\r
817 /* Process unlocked */
\r
818 __HAL_UNLOCK(hqspi);
\r
825 * @brief Receive an amount of data in blocking mode
\r
826 * @param hqspi: QSPI handle
\r
827 * @param pData: pointer to data buffer
\r
828 * @param Timeout : Time out duration
\r
829 * @note This function is used only in Indirect Read Mode
\r
830 * @retval HAL status
\r
832 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
\r
834 HAL_StatusTypeDef status = HAL_OK;
\r
835 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
\r
836 __IO uint32_t *data_reg = &hqspi->Instance->DR;
\r
838 /* Process locked */
\r
841 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
845 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
848 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
\r
850 /* Configure counters and size of the handle */
\r
851 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
\r
852 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
\r
853 hqspi->pRxBuffPtr = pData;
\r
855 /* Configure QSPI: CCR register with functional as indirect read */
\r
856 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
\r
858 /* Start the transfer by re-writing the address in AR register */
\r
859 WRITE_REG(hqspi->Instance->AR, addr_reg);
\r
861 while(hqspi->RxXferCount > 0)
\r
863 /* Wait until FT or TC flag is set to read received data */
\r
864 if(QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, Timeout) != HAL_OK)
\r
866 status = HAL_TIMEOUT;
\r
870 *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
\r
871 hqspi->RxXferCount--;
\r
874 if (status == HAL_OK)
\r
876 /* Wait until TC flag is set to go back in idle state */
\r
877 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
\r
879 status = HAL_TIMEOUT;
\r
883 /* Clear Transfer Complete bit */
\r
884 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
\r
886 /* Workaround - Extra data written in the FIFO at the end of a read transfer */
\r
887 status = HAL_QSPI_Abort(hqspi);
\r
891 /* Update QSPI state */
\r
892 hqspi->State = HAL_QSPI_STATE_READY;
\r
896 status = HAL_ERROR;
\r
904 /* Process unlocked */
\r
905 __HAL_UNLOCK(hqspi);
\r
911 * @brief Send an amount of data in interrupt mode
\r
912 * @param hqspi: QSPI handle
\r
913 * @param pData: pointer to data buffer
\r
914 * @note This function is used only in Indirect Write Mode
\r
915 * @retval HAL status
\r
917 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
\r
919 HAL_StatusTypeDef status = HAL_OK;
\r
921 /* Process locked */
\r
924 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
928 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
931 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
\r
933 /* Configure counters and size of the handle */
\r
934 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
\r
935 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
\r
936 hqspi->pTxBuffPtr = pData;
\r
938 /* Configure QSPI: CCR register with functional as indirect write */
\r
939 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
\r
941 /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
\r
942 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
\r
947 status = HAL_ERROR;
\r
955 /* Process unlocked */
\r
956 __HAL_UNLOCK(hqspi);
\r
962 * @brief Receive an amount of data in no-blocking mode with Interrupt
\r
963 * @param hqspi: QSPI handle
\r
964 * @param pData: pointer to data buffer
\r
965 * @note This function is used only in Indirect Read Mode
\r
966 * @retval HAL status
\r
968 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
\r
970 HAL_StatusTypeDef status = HAL_OK;
\r
971 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
\r
973 /* Process locked */
\r
976 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
980 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
983 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
\r
985 /* Configure counters and size of the handle */
\r
986 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
\r
987 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
\r
988 hqspi->pRxBuffPtr = pData;
\r
990 /* Configure QSPI: CCR register with functional as indirect read */
\r
991 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
\r
993 /* Start the transfer by re-writing the address in AR register */
\r
994 WRITE_REG(hqspi->Instance->AR, addr_reg);
\r
996 /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
\r
997 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
\r
1001 status = HAL_ERROR;
\r
1006 status = HAL_BUSY;
\r
1009 /* Process unlocked */
\r
1010 __HAL_UNLOCK(hqspi);
\r
1016 * @brief Sends an amount of data in non blocking mode with DMA.
\r
1017 * @param hqspi: QSPI handle
\r
1018 * @param pData: pointer to data buffer
\r
1019 * @note This function is used only in Indirect Write Mode
\r
1020 * @retval HAL status
\r
1022 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
\r
1024 HAL_StatusTypeDef status = HAL_OK;
\r
1027 /* Process locked */
\r
1028 __HAL_LOCK(hqspi);
\r
1030 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
1032 if(pData != NULL )
\r
1034 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
1036 /* Update state */
\r
1037 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
\r
1039 /* Configure counters and size of the handle */
\r
1040 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
\r
1041 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
\r
1042 hqspi->pTxBuffPtr = pData;
\r
1044 /* Configure QSPI: CCR register with functional mode as indirect write */
\r
1045 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
\r
1047 /* Set the QSPI DMA transfer complete callback */
\r
1048 hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
\r
1050 /* Set the QSPI DMA Half transfer complete callback */
\r
1051 hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
\r
1053 /* Set the DMA error callback */
\r
1054 hqspi->hdma->XferErrorCallback = QSPI_DMAError;
\r
1056 /* Configure the direction of the DMA */
\r
1057 hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
\r
1058 MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
\r
1060 /* Enable the QSPI transmit DMA Channel */
\r
1061 tmp = (uint32_t*)&pData;
\r
1062 HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
\r
1064 /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
\r
1065 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
\r
1074 status = HAL_BUSY;
\r
1077 /* Process unlocked */
\r
1078 __HAL_UNLOCK(hqspi);
\r
1084 * @brief Receives an amount of data in non blocking mode with DMA.
\r
1085 * @param hqspi: QSPI handle
\r
1086 * @param pData: pointer to data buffer.
\r
1087 * @note This function is used only in Indirect Read Mode
\r
1088 * @retval HAL status
\r
1090 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
\r
1092 HAL_StatusTypeDef status = HAL_OK;
\r
1094 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
\r
1096 /* Process locked */
\r
1097 __HAL_LOCK(hqspi);
\r
1099 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
1101 if(pData != NULL )
\r
1103 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
1105 /* Update state */
\r
1106 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
\r
1108 /* Configure counters and size of the handle */
\r
1109 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
\r
1110 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
\r
1111 hqspi->pRxBuffPtr = pData;
\r
1113 /* Set the QSPI DMA transfer complete callback */
\r
1114 hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
\r
1116 /* Set the QSPI DMA Half transfer complete callback */
\r
1117 hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
\r
1119 /* Set the DMA error callback */
\r
1120 hqspi->hdma->XferErrorCallback = QSPI_DMAError;
\r
1122 /* Configure the direction of the DMA */
\r
1123 hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
\r
1124 MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
\r
1126 /* Enable the DMA Channel */
\r
1127 tmp = (uint32_t*)&pData;
\r
1128 HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
\r
1130 /* Configure QSPI: CCR register with functional as indirect read */
\r
1131 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
\r
1133 /* Start the transfer by re-writing the address in AR register */
\r
1134 WRITE_REG(hqspi->Instance->AR, addr_reg);
\r
1136 /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
\r
1137 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
\r
1141 status = HAL_ERROR;
\r
1146 status = HAL_BUSY;
\r
1149 /* Process unlocked */
\r
1150 __HAL_UNLOCK(hqspi);
\r
1156 * @brief Configure the QSPI Automatic Polling Mode in blocking mode.
\r
1157 * @param hqspi: QSPI handle
\r
1158 * @param cmd: structure that contains the command configuration information.
\r
1159 * @param cfg: structure that contains the polling configuration information.
\r
1160 * @param Timeout : Time out duration
\r
1161 * @note This function is used only in Automatic Polling Mode
\r
1162 * @retval HAL status
\r
1164 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
\r
1166 HAL_StatusTypeDef status = HAL_ERROR;
\r
1168 /* Check the parameters */
\r
1169 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
\r
1170 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
\r
1172 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
\r
1175 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
\r
1176 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
\r
1178 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
\r
1181 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
\r
1182 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
\r
1184 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
\r
1187 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
\r
1188 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
\r
1190 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
\r
1191 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
\r
1192 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
\r
1194 assert_param(IS_QSPI_INTERVAL(cfg->Interval));
\r
1195 assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
\r
1196 assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
\r
1198 /* Process locked */
\r
1199 __HAL_LOCK(hqspi);
\r
1201 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
1204 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
1206 /* Update state */
\r
1207 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
\r
1209 /* Wait till BUSY flag reset */
\r
1210 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
\r
1212 if (status == HAL_OK)
\r
1214 /* Configure QSPI: PSMAR register with the status match value */
\r
1215 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
\r
1217 /* Configure QSPI: PSMKR register with the status mask value */
\r
1218 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
\r
1220 /* Configure QSPI: PIR register with the interval value */
\r
1221 WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
\r
1223 /* Configure QSPI: CR register with Match mode and Automatic stop enabled
\r
1224 (otherwise there will be an infinite loop in blocking mode) */
\r
1225 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
\r
1226 (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
\r
1228 /* Call the configuration function */
\r
1229 cmd->NbData = cfg->StatusBytesSize;
\r
1230 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
\r
1232 /* Wait until SM flag is set to go back in idle state */
\r
1233 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, Timeout) != HAL_OK)
\r
1235 status = HAL_TIMEOUT;
\r
1239 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
\r
1241 /* Update state */
\r
1242 hqspi->State = HAL_QSPI_STATE_READY;
\r
1248 status = HAL_BUSY;
\r
1250 /* Process unlocked */
\r
1251 __HAL_UNLOCK(hqspi);
\r
1253 /* Return function status */
\r
1258 * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
\r
1259 * @param hqspi: QSPI handle
\r
1260 * @param cmd: structure that contains the command configuration information.
\r
1261 * @param cfg: structure that contains the polling configuration information.
\r
1262 * @note This function is used only in Automatic Polling Mode
\r
1263 * @retval HAL status
\r
1265 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
\r
1267 HAL_StatusTypeDef status = HAL_ERROR;
\r
1269 /* Check the parameters */
\r
1270 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
\r
1271 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
\r
1273 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
\r
1276 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
\r
1277 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
\r
1279 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
\r
1282 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
\r
1283 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
\r
1285 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
\r
1288 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
\r
1289 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
\r
1291 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
\r
1292 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
\r
1293 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
\r
1295 assert_param(IS_QSPI_INTERVAL(cfg->Interval));
\r
1296 assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
\r
1297 assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
\r
1298 assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
\r
1300 /* Process locked */
\r
1301 __HAL_LOCK(hqspi);
\r
1303 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
1305 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
1307 /* Update state */
\r
1308 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
\r
1310 /* Wait till BUSY flag reset */
\r
1311 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
\r
1313 if (status == HAL_OK)
\r
1315 /* Configure QSPI: PSMAR register with the status match value */
\r
1316 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
\r
1318 /* Configure QSPI: PSMKR register with the status mask value */
\r
1319 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
\r
1321 /* Configure QSPI: PIR register with the interval value */
\r
1322 WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
\r
1324 /* Configure QSPI: CR register with Match mode and Automatic stop mode */
\r
1325 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
\r
1326 (cfg->MatchMode | cfg->AutomaticStop));
\r
1328 /* Call the configuration function */
\r
1329 cmd->NbData = cfg->StatusBytesSize;
\r
1330 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
\r
1332 /* Enable the QSPI Transfer Error, FIFO threshold and status match Interrupt */
\r
1333 __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_FT | QSPI_IT_SM | QSPI_IT_TE));
\r
1338 status = HAL_BUSY;
\r
1341 /* Process unlocked */
\r
1342 __HAL_UNLOCK(hqspi);
\r
1344 /* Return function status */
\r
1349 * @brief Configure the Memory Mapped mode.
\r
1350 * @param hqspi: QSPI handle
\r
1351 * @param cmd: structure that contains the command configuration information.
\r
1352 * @param cfg: structure that contains the memory mapped configuration information.
\r
1353 * @note This function is used only in Memory mapped Mode
\r
1354 * @retval HAL status
\r
1356 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
\r
1358 HAL_StatusTypeDef status = HAL_ERROR;
\r
1360 /* Check the parameters */
\r
1361 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
\r
1362 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
\r
1364 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
\r
1367 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
\r
1368 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
\r
1370 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
\r
1373 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
\r
1374 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
\r
1376 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
\r
1379 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
\r
1380 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
\r
1382 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
\r
1383 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
\r
1384 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
\r
1386 assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
\r
1388 /* Process locked */
\r
1389 __HAL_LOCK(hqspi);
\r
1391 if(hqspi->State == HAL_QSPI_STATE_READY)
\r
1393 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
\r
1395 /* Update state */
\r
1396 hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
\r
1398 /* Wait till BUSY flag reset */
\r
1399 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
\r
1401 if (status == HAL_OK)
\r
1403 /* Configure QSPI: CR register with time out counter enable */
\r
1404 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
\r
1406 if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
\r
1408 assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
\r
1410 /* Configure QSPI: LPTR register with the low-power time out value */
\r
1411 WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
\r
1413 /* Enable the QSPI TimeOut Interrupt */
\r
1414 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
\r
1417 /* Call the configuration function */
\r
1418 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
\r
1424 status = HAL_BUSY;
\r
1428 /* Process unlocked */
\r
1429 __HAL_UNLOCK(hqspi);
\r
1431 /* Return function status */
\r
1436 * @brief Transfer Error callbacks
\r
1437 * @param hqspi: QSPI handle
\r
1440 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
\r
1442 /* NOTE : This function Should not be modified, when the callback is needed,
\r
1443 the HAL_QSPI_ErrorCallback could be implemented in the user file
\r
1448 * @brief Command completed callbacks.
\r
1449 * @param hqspi: QSPI handle
\r
1452 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
\r
1454 /* NOTE: This function Should not be modified, when the callback is needed,
\r
1455 the HAL_QSPI_CmdCpltCallback could be implemented in the user file
\r
1460 * @brief Rx Transfer completed callbacks.
\r
1461 * @param hqspi: QSPI handle
\r
1464 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
\r
1466 /* NOTE: This function Should not be modified, when the callback is needed,
\r
1467 the HAL_QSPI_RxCpltCallback could be implemented in the user file
\r
1472 * @brief Tx Transfer completed callbacks.
\r
1473 * @param hqspi: QSPI handle
\r
1476 __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
\r
1478 /* NOTE: This function Should not be modified, when the callback is needed,
\r
1479 the HAL_QSPI_TxCpltCallback could be implemented in the user file
\r
1484 * @brief Rx Half Transfer completed callbacks.
\r
1485 * @param hqspi: QSPI handle
\r
1488 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
\r
1490 /* NOTE: This function Should not be modified, when the callback is needed,
\r
1491 the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
\r
1496 * @brief Tx Half Transfer completed callbacks.
\r
1497 * @param hqspi: QSPI handle
\r
1500 __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
\r
1502 /* NOTE: This function Should not be modified, when the callback is needed,
\r
1503 the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
\r
1508 * @brief FIFO Threshold callbacks
\r
1509 * @param hqspi: QSPI handle
\r
1512 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
\r
1514 /* NOTE : This function Should not be modified, when the callback is needed,
\r
1515 the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
\r
1520 * @brief Status Match callbacks
\r
1521 * @param hqspi: QSPI handle
\r
1524 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
\r
1526 /* NOTE : This function Should not be modified, when the callback is needed,
\r
1527 the HAL_QSPI_StatusMatchCallback could be implemented in the user file
\r
1532 * @brief Timeout callbacks
\r
1533 * @param hqspi: QSPI handle
\r
1536 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
\r
1538 /* NOTE : This function Should not be modified, when the callback is needed,
\r
1539 the HAL_QSPI_TimeOutCallback could be implemented in the user file
\r
1547 /** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
\r
1548 * @brief QSPI control and State functions
\r
1551 ===============================================================================
\r
1552 ##### Peripheral Control and State functions #####
\r
1553 ===============================================================================
\r
1555 This subsection provides a set of functions allowing to :
\r
1556 (+) Check in run-time the state of the driver.
\r
1557 (+) Check the error code set during last operation.
\r
1558 (+) Abort any operation.
\r
1565 * @brief Return the QSPI state.
\r
1566 * @param hqspi: QSPI handle
\r
1567 * @retval HAL state
\r
1569 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
\r
1571 return hqspi->State;
\r
1575 * @brief Return the QSPI error code
\r
1576 * @param hqspi: QSPI handle
\r
1577 * @retval QSPI Error Code
\r
1579 uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
\r
1581 return hqspi->ErrorCode;
\r
1585 * @brief Abort the current transmission
\r
1586 * @param hqspi: QSPI handle
\r
1587 * @retval HAL status
\r
1589 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
\r
1591 HAL_StatusTypeDef status = HAL_ERROR;
\r
1593 /* Configure QSPI: CR register with Abort request */
\r
1594 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
\r
1596 /* Wait until TC flag is set to go back in idle state */
\r
1597 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
\r
1599 status = HAL_TIMEOUT;
\r
1603 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
\r
1605 /* Wait until BUSY flag is reset */
\r
1606 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
\r
1608 /* Update state */
\r
1609 hqspi->State = HAL_QSPI_STATE_READY;
\r
1615 /** @brief Set QSPI timeout
\r
1616 * @param hqspi: QSPI handle.
\r
1617 * @param Timeout: Timeout for the QSPI memory access.
\r
1620 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
\r
1622 hqspi->Timeout = Timeout;
\r
1629 /* Private functions ---------------------------------------------------------*/
\r
1632 * @brief DMA QSPI receive process complete callback.
\r
1633 * @param hdma: DMA handle
\r
1636 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
\r
1638 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
1639 hqspi->RxXferCount = 0;
\r
1641 /* Wait for QSPI TC Flag */
\r
1642 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
\r
1644 /* Time out Occurred */
\r
1645 HAL_QSPI_ErrorCallback(hqspi);
\r
1649 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
\r
1650 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
\r
1652 /* Disable the DMA channel */
\r
1653 HAL_DMA_Abort(hdma);
\r
1655 /* Clear Transfer Complete bit */
\r
1656 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
\r
1658 /* Workaround - Extra data written in the FIFO at the end of a read transfer */
\r
1659 HAL_QSPI_Abort(hqspi);
\r
1661 /* Update state */
\r
1662 hqspi->State = HAL_QSPI_STATE_READY;
\r
1664 HAL_QSPI_RxCpltCallback(hqspi);
\r
1669 * @brief DMA QSPI transmit process complete callback.
\r
1670 * @param hdma: DMA handle
\r
1673 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
\r
1675 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
1676 hqspi->TxXferCount = 0;
\r
1678 /* Wait for QSPI TC Flag */
\r
1679 if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
\r
1681 /* Time out Occurred */
\r
1682 HAL_QSPI_ErrorCallback(hqspi);
\r
1686 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
\r
1687 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
\r
1689 /* Disable the DMA channel */
\r
1690 HAL_DMA_Abort(hdma);
\r
1692 /* Clear Transfer Complete bit */
\r
1693 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
\r
1695 /* Clear Busy bit */
\r
1696 HAL_QSPI_Abort(hqspi);
\r
1698 /* Update state */
\r
1699 hqspi->State = HAL_QSPI_STATE_READY;
\r
1701 HAL_QSPI_TxCpltCallback(hqspi);
\r
1706 * @brief DMA QSPI receive process half complete callback
\r
1707 * @param hdma : DMA handle
\r
1710 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
\r
1712 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
\r
1714 HAL_QSPI_RxHalfCpltCallback(hqspi);
\r
1718 * @brief DMA QSPI transmit process half complete callback
\r
1719 * @param hdma : DMA handle
\r
1722 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
\r
1724 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
\r
1726 HAL_QSPI_TxHalfCpltCallback(hqspi);
\r
1730 * @brief DMA QSPI communication error callback.
\r
1731 * @param hdma: DMA handle
\r
1734 static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
\r
1736 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
\r
1738 hqspi->RxXferCount = 0;
\r
1739 hqspi->TxXferCount = 0;
\r
1740 hqspi->State = HAL_QSPI_STATE_ERROR;
\r
1741 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
\r
1743 HAL_QSPI_ErrorCallback(hqspi);
\r
1747 * @brief This function wait a flag state until time out.
\r
1748 * @param hqspi: QSPI handle
\r
1749 * @param Flag: Flag checked
\r
1750 * @param State: Value of the flag expected
\r
1751 * @param Timeout: Duration of the time out
\r
1752 * @retval HAL status
\r
1754 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
\r
1755 FlagStatus State, uint32_t Timeout)
\r
1757 uint32_t tickstart = HAL_GetTick();
\r
1759 /* Wait until flag is in expected state */
\r
1760 while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
\r
1762 /* Check for the Timeout */
\r
1763 if (Timeout != HAL_MAX_DELAY)
\r
1765 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
\r
1767 hqspi->State = HAL_QSPI_STATE_ERROR;
\r
1768 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
\r
1770 return HAL_TIMEOUT;
\r
1778 * @brief This function configures the communication registers
\r
1779 * @param hqspi: QSPI handle
\r
1780 * @param cmd: structure that contains the command configuration information
\r
1781 * @param FunctionalMode: functional mode to configured
\r
1782 * This parameter can be one of the following values:
\r
1783 * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
\r
1784 * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
\r
1785 * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
\r
1786 * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
\r
1789 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
\r
1791 assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
\r
1793 if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
\r
1795 /* Configure QSPI: DLR register with the number of data to read or write */
\r
1796 WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
\r
1799 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
\r
1801 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
\r
1803 /* Configure QSPI: ABR register with alternate bytes value */
\r
1804 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
\r
1806 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
\r
1808 /*---- Command with instruction, address and alternate bytes ----*/
\r
1809 /* Configure QSPI: CCR register with all communications parameters */
\r
1810 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
\r
1811 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
\r
1812 cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
\r
1813 cmd->InstructionMode | cmd->Instruction | FunctionalMode));
\r
1815 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
\r
1817 /* Configure QSPI: AR register with address value */
\r
1818 WRITE_REG(hqspi->Instance->AR, cmd->Address);
\r
1823 /*---- Command with instruction and alternate bytes ----*/
\r
1824 /* Configure QSPI: CCR register with all communications parameters */
\r
1825 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
\r
1826 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
\r
1827 cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
\r
1828 cmd->Instruction | FunctionalMode));
\r
1833 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
\r
1835 /*---- Command with instruction and address ----*/
\r
1836 /* Configure QSPI: CCR register with all communications parameters */
\r
1837 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
\r
1838 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
\r
1839 cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
\r
1840 cmd->Instruction | FunctionalMode));
\r
1842 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
\r
1844 /* Configure QSPI: AR register with address value */
\r
1845 WRITE_REG(hqspi->Instance->AR, cmd->Address);
\r
1850 /*---- Command with only instruction ----*/
\r
1851 /* Configure QSPI: CCR register with all communications parameters */
\r
1852 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
\r
1853 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
\r
1854 cmd->AddressMode | cmd->InstructionMode | cmd->Instruction |
\r
1861 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
\r
1863 /* Configure QSPI: ABR register with alternate bytes value */
\r
1864 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
\r
1866 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
\r
1868 /*---- Command with address and alternate bytes ----*/
\r
1869 /* Configure QSPI: CCR register with all communications parameters */
\r
1870 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
\r
1871 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
\r
1872 cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
\r
1873 cmd->InstructionMode | FunctionalMode));
\r
1875 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
\r
1877 /* Configure QSPI: AR register with address value */
\r
1878 WRITE_REG(hqspi->Instance->AR, cmd->Address);
\r
1883 /*---- Command with only alternate bytes ----*/
\r
1884 /* Configure QSPI: CCR register with all communications parameters */
\r
1885 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
\r
1886 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
\r
1887 cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
\r
1893 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
\r
1895 /*---- Command with only address ----*/
\r
1896 /* Configure QSPI: CCR register with all communications parameters */
\r
1897 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
\r
1898 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
\r
1899 cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
\r
1902 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
\r
1904 /* Configure QSPI: AR register with address value */
\r
1905 WRITE_REG(hqspi->Instance->AR, cmd->Address);
\r
1910 /*---- Command with only data phase ----*/
\r
1911 if (cmd->DataMode != QSPI_DATA_NONE)
\r
1913 /* Configure QSPI: CCR register with all communications parameters */
\r
1914 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
\r
1915 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
\r
1916 cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
\r
1926 #endif /* HAL_QSPI_MODULE_ENABLED */
\r
1935 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r