2 ******************************************************************************
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3 * @file stm32f7xx_ll_fmc.c
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4 * @author MCD Application Team
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7 * @brief FMC Low Layer HAL module driver.
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9 * This file provides firmware functions to manage the following
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10 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
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11 * + Initialization/de-initialization functions
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12 * + Peripheral Control functions
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13 * + Peripheral State functions
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16 ==============================================================================
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17 ##### FMC peripheral features #####
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18 ==============================================================================
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19 [..] The Flexible memory controller (FMC) includes three memory controllers:
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20 (+) The NOR/PSRAM memory controller
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21 (+) The NAND memory controller
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22 (+) The Synchronous DRAM (SDRAM) controller
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24 [..] The FMC functional block makes the interface with synchronous and asynchronous static
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25 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
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26 (+) to translate AHB transactions into the appropriate external device protocol
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27 (+) to meet the access time requirements of the external memory devices
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29 [..] All external memories share the addresses, data and control signals with the controller.
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30 Each external device is accessed by means of a unique Chip Select. The FMC performs
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31 only one access at a time to an external device.
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32 The main features of the FMC controller are the following:
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33 (+) Interface with static-memory mapped devices including:
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34 (++) Static random access memory (SRAM)
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35 (++) Read-only memory (ROM)
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36 (++) NOR Flash memory/OneNAND Flash memory
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37 (++) PSRAM (4 memory banks)
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38 (++) 16-bit PC Card compatible devices
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39 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
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41 (+) Interface with synchronous DRAM (SDRAM) memories
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42 (+) Independent Chip Select control for each memory bank
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43 (+) Independent configuration for each memory bank
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46 ******************************************************************************
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49 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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51 * Redistribution and use in source and binary forms, with or without modification,
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52 * are permitted provided that the following conditions are met:
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53 * 1. Redistributions of source code must retain the above copyright notice,
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54 * this list of conditions and the following disclaimer.
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55 * 2. Redistributions in binary form must reproduce the above copyright notice,
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56 * this list of conditions and the following disclaimer in the documentation
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57 * and/or other materials provided with the distribution.
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58 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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59 * may be used to endorse or promote products derived from this software
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60 * without specific prior written permission.
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62 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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63 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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64 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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65 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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66 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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67 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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68 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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69 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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70 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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71 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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73 ******************************************************************************
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76 /* Includes ------------------------------------------------------------------*/
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77 #include "stm32f7xx_hal.h"
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79 /** @addtogroup STM32F7xx_HAL_Driver
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83 /** @defgroup FMC_LL FMC Low Layer
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84 * @brief FMC driver modules
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88 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
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90 /* Private typedef -----------------------------------------------------------*/
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91 /* Private define ------------------------------------------------------------*/
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92 /* Private macro -------------------------------------------------------------*/
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93 /* Private variables ---------------------------------------------------------*/
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94 /* Private function prototypes -----------------------------------------------*/
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95 /* Exported functions --------------------------------------------------------*/
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97 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
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101 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
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102 * @brief NORSRAM Controller functions
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105 ==============================================================================
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106 ##### How to use NORSRAM device driver #####
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107 ==============================================================================
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110 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
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111 to run the NORSRAM external devices.
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113 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
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114 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
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115 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
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116 (+) FMC NORSRAM bank extended timing configuration using the function
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117 FMC_NORSRAM_Extended_Timing_Init()
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118 (+) FMC NORSRAM bank enable/disable write operation using the functions
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119 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
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126 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
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127 * @brief Initialization and Configuration functions
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130 ==============================================================================
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131 ##### Initialization and de_initialization functions #####
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132 ==============================================================================
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134 This section provides functions allowing to:
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135 (+) Initialize and configure the FMC NORSRAM interface
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136 (+) De-initialize the FMC NORSRAM interface
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137 (+) Configure the FMC clock and associated GPIOs
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144 * @brief Initialize the FMC_NORSRAM device according to the specified
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145 * control parameters in the FMC_NORSRAM_InitTypeDef
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146 * @param Device: Pointer to NORSRAM device instance
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147 * @param Init: Pointer to NORSRAM Initialization structure
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148 * @retval HAL status
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150 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
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154 /* Check the parameters */
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155 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
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156 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
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157 assert_param(IS_FMC_MUX(Init->DataAddressMux));
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158 assert_param(IS_FMC_MEMORY(Init->MemoryType));
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159 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
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160 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
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161 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
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162 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
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163 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
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164 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
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165 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
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166 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
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167 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
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168 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
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169 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
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170 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
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172 /* Get the BTCR register value */
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173 tmpr = Device->BTCR[Init->NSBank];
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175 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,
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176 WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
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177 tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
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178 FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
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179 FMC_BCR1_WAITPOL | FMC_BCR1_CPSIZE | FMC_BCR1_WAITCFG | \
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180 FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
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181 FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS));
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183 /* Set NORSRAM device control parameters */
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184 tmpr |= (uint32_t)(Init->DataAddressMux |\
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185 Init->MemoryType |\
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186 Init->MemoryDataWidth |\
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187 Init->BurstAccessMode |\
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188 Init->WaitSignalPolarity |\
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189 Init->WaitSignalActive |\
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190 Init->WriteOperation |\
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191 Init->WaitSignal |\
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192 Init->ExtendedMode |\
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193 Init->AsynchronousWait |\
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194 Init->WriteBurst |\
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195 Init->ContinuousClock |\
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199 if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
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201 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
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204 Device->BTCR[Init->NSBank] = tmpr;
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206 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
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207 if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
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209 Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE;
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210 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\
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211 Init->ContinuousClock);
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213 if(Init->NSBank != FMC_NORSRAM_BANK1)
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215 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
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223 * @brief DeInitialize the FMC_NORSRAM peripheral
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224 * @param Device: Pointer to NORSRAM device instance
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225 * @param ExDevice: Pointer to NORSRAM extended mode device instance
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226 * @param Bank: NORSRAM bank number
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227 * @retval HAL status
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229 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
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231 /* Check the parameters */
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232 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
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233 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
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234 assert_param(IS_FMC_NORSRAM_BANK(Bank));
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236 /* Disable the FMC_NORSRAM device */
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237 __FMC_NORSRAM_DISABLE(Device, Bank);
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239 /* De-initialize the FMC_NORSRAM device */
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240 /* FMC_NORSRAM_BANK1 */
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241 if(Bank == FMC_NORSRAM_BANK1)
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243 Device->BTCR[Bank] = 0x000030DB;
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245 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
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248 Device->BTCR[Bank] = 0x000030D2;
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251 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
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252 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
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259 * @brief Initialize the FMC_NORSRAM Timing according to the specified
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260 * parameters in the FMC_NORSRAM_TimingTypeDef
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261 * @param Device: Pointer to NORSRAM device instance
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262 * @param Timing: Pointer to NORSRAM Timing structure
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263 * @param Bank: NORSRAM bank number
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264 * @retval HAL status
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266 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
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270 /* Check the parameters */
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271 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
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272 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
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273 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
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274 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
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275 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
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276 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
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277 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
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278 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
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279 assert_param(IS_FMC_NORSRAM_BANK(Bank));
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281 /* Get the BTCR register value */
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282 tmpr = Device->BTCR[Bank + 1];
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284 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
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285 tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \
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286 FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \
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289 /* Set FMC_NORSRAM device timing parameters */
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290 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
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291 ((Timing->AddressHoldTime) << 4) |\
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292 ((Timing->DataSetupTime) << 8) |\
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293 ((Timing->BusTurnAroundDuration) << 16) |\
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294 (((Timing->CLKDivision)-1) << 20) |\
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295 (((Timing->DataLatency)-2) << 24) |\
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296 (Timing->AccessMode)
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299 Device->BTCR[Bank + 1] = tmpr;
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301 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
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302 if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
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304 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20));
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305 tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);
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306 Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
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313 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
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314 * parameters in the FMC_NORSRAM_TimingTypeDef
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315 * @param Device: Pointer to NORSRAM device instance
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316 * @param Timing: Pointer to NORSRAM Timing structure
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317 * @param Bank: NORSRAM bank number
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318 * @retval HAL status
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320 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
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324 /* Check the parameters */
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325 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
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327 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
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328 if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
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330 /* Check the parameters */
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331 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
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332 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
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333 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
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334 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
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335 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
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336 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
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337 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
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338 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
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339 assert_param(IS_FMC_NORSRAM_BANK(Bank));
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341 /* Get the BWTR register value */
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342 tmpr = Device->BWTR[Bank];
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344 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
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345 tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \
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346 FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));
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348 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
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349 ((Timing->AddressHoldTime) << 4) |\
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350 ((Timing->DataSetupTime) << 8) |\
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351 ((Timing->BusTurnAroundDuration) << 16) |\
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352 (Timing->AccessMode));
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354 Device->BWTR[Bank] = tmpr;
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358 Device->BWTR[Bank] = 0x0FFFFFFF;
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367 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
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368 * @brief management functions
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371 ==============================================================================
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372 ##### FMC_NORSRAM Control functions #####
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373 ==============================================================================
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375 This subsection provides a set of functions allowing to control dynamically
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376 the FMC NORSRAM interface.
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383 * @brief Enables dynamically FMC_NORSRAM write operation.
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384 * @param Device: Pointer to NORSRAM device instance
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385 * @param Bank: NORSRAM bank number
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386 * @retval HAL status
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388 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
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390 /* Check the parameters */
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391 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
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392 assert_param(IS_FMC_NORSRAM_BANK(Bank));
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394 /* Enable write operation */
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395 Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
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401 * @brief Disables dynamically FMC_NORSRAM write operation.
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402 * @param Device: Pointer to NORSRAM device instance
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403 * @param Bank: NORSRAM bank number
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404 * @retval HAL status
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406 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
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408 /* Check the parameters */
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409 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
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410 assert_param(IS_FMC_NORSRAM_BANK(Bank));
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412 /* Disable write operation */
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413 Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
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426 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
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427 * @brief NAND Controller functions
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430 ==============================================================================
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431 ##### How to use NAND device driver #####
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432 ==============================================================================
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434 This driver contains a set of APIs to interface with the FMC NAND banks in order
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435 to run the NAND external devices.
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437 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
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438 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
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439 (+) FMC NAND bank common space timing configuration using the function
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440 FMC_NAND_CommonSpace_Timing_Init()
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441 (+) FMC NAND bank attribute space timing configuration using the function
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442 FMC_NAND_AttributeSpace_Timing_Init()
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443 (+) FMC NAND bank enable/disable ECC correction feature using the functions
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444 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
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445 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
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451 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
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452 * @brief Initialization and Configuration functions
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455 ==============================================================================
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456 ##### Initialization and de_initialization functions #####
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457 ==============================================================================
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459 This section provides functions allowing to:
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460 (+) Initialize and configure the FMC NAND interface
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461 (+) De-initialize the FMC NAND interface
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462 (+) Configure the FMC clock and associated GPIOs
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469 * @brief Initializes the FMC_NAND device according to the specified
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470 * control parameters in the FMC_NAND_HandleTypeDef
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471 * @param Device: Pointer to NAND device instance
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472 * @param Init: Pointer to NAND Initialization structure
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473 * @retval HAL status
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475 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
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477 uint32_t tmpr = 0;
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479 /* Check the parameters */
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480 assert_param(IS_FMC_NAND_DEVICE(Device));
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481 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
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482 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
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483 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
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484 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
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485 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
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486 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
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487 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
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489 /* Get the NAND bank 3 register value */
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490 tmpr = Device->PCR;
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492 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
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493 tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \
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494 FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \
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495 FMC_PCR_TAR | FMC_PCR_ECCPS));
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496 /* Set NAND device control parameters */
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497 tmpr |= (uint32_t)(Init->Waitfeature |\
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498 FMC_PCR_MEMORY_TYPE_NAND |\
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499 Init->MemoryDataWidth |\
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500 Init->EccComputation |\
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501 Init->ECCPageSize |\
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502 ((Init->TCLRSetupTime) << 9) |\
\r
503 ((Init->TARSetupTime) << 13));
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505 /* NAND bank 3 registers configuration */
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506 Device->PCR = tmpr;
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513 * @brief Initializes the FMC_NAND Common space Timing according to the specified
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514 * parameters in the FMC_NAND_PCC_TimingTypeDef
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515 * @param Device: Pointer to NAND device instance
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516 * @param Timing: Pointer to NAND timing structure
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517 * @param Bank: NAND bank number
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518 * @retval HAL status
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520 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
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522 uint32_t tmpr = 0;
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524 /* Check the parameters */
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525 assert_param(IS_FMC_NAND_DEVICE(Device));
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526 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
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527 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
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528 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
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529 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
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530 assert_param(IS_FMC_NAND_BANK(Bank));
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532 /* Get the NAND bank 3 register value */
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533 tmpr = Device->PMEM;
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535 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
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536 tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET3 | FMC_PMEM_MEMWAIT3 | FMC_PMEM_MEMHOLD3 | \
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537 FMC_PMEM_MEMHIZ3));
\r
538 /* Set FMC_NAND device timing parameters */
\r
539 tmpr |= (uint32_t)(Timing->SetupTime |\
\r
540 ((Timing->WaitSetupTime) << 8) |\
\r
541 ((Timing->HoldSetupTime) << 16) |\
\r
542 ((Timing->HiZSetupTime) << 24)
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545 /* NAND bank 3 registers configuration */
\r
546 Device->PMEM = tmpr;
\r
552 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
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553 * parameters in the FMC_NAND_PCC_TimingTypeDef
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554 * @param Device: Pointer to NAND device instance
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555 * @param Timing: Pointer to NAND timing structure
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556 * @param Bank: NAND bank number
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557 * @retval HAL status
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559 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
\r
561 uint32_t tmpr = 0;
\r
563 /* Check the parameters */
\r
564 assert_param(IS_FMC_NAND_DEVICE(Device));
\r
565 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
\r
566 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
\r
567 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
\r
568 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
\r
569 assert_param(IS_FMC_NAND_BANK(Bank));
\r
571 /* Get the NAND bank 3 register value */
\r
572 tmpr = Device->PATT;
\r
574 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
\r
575 tmpr &= ((uint32_t)~(FMC_PATT_ATTSET3 | FMC_PATT_ATTWAIT3 | FMC_PATT_ATTHOLD3 | \
\r
576 FMC_PATT_ATTHIZ3));
\r
577 /* Set FMC_NAND device timing parameters */
\r
578 tmpr |= (uint32_t)(Timing->SetupTime |\
\r
579 ((Timing->WaitSetupTime) << 8) |\
\r
580 ((Timing->HoldSetupTime) << 16) |\
\r
581 ((Timing->HiZSetupTime) << 24));
\r
583 /* NAND bank 3 registers configuration */
\r
584 Device->PATT = tmpr;
\r
590 * @brief DeInitializes the FMC_NAND device
\r
591 * @param Device: Pointer to NAND device instance
\r
592 * @param Bank: NAND bank number
\r
593 * @retval HAL status
\r
595 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
\r
597 /* Check the parameters */
\r
598 assert_param(IS_FMC_NAND_DEVICE(Device));
\r
599 assert_param(IS_FMC_NAND_BANK(Bank));
\r
601 /* Disable the NAND Bank */
\r
602 __FMC_NAND_DISABLE(Device);
\r
604 /* Set the FMC_NAND_BANK3 registers to their reset values */
\r
605 Device->PCR = 0x00000018;
\r
606 Device->SR = 0x00000040;
\r
607 Device->PMEM = 0xFCFCFCFC;
\r
608 Device->PATT = 0xFCFCFCFC;
\r
617 /** @defgroup HAL_FMC_NAND_Group3 Control functions
\r
618 * @brief management functions
\r
621 ==============================================================================
\r
622 ##### FMC_NAND Control functions #####
\r
623 ==============================================================================
\r
625 This subsection provides a set of functions allowing to control dynamically
\r
626 the FMC NAND interface.
\r
634 * @brief Enables dynamically FMC_NAND ECC feature.
\r
635 * @param Device: Pointer to NAND device instance
\r
636 * @param Bank: NAND bank number
\r
637 * @retval HAL status
\r
639 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
\r
641 /* Check the parameters */
\r
642 assert_param(IS_FMC_NAND_DEVICE(Device));
\r
643 assert_param(IS_FMC_NAND_BANK(Bank));
\r
645 /* Enable ECC feature */
\r
646 Device->PCR |= FMC_PCR_ECCEN;
\r
653 * @brief Disables dynamically FMC_NAND ECC feature.
\r
654 * @param Device: Pointer to NAND device instance
\r
655 * @param Bank: NAND bank number
\r
656 * @retval HAL status
\r
658 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
\r
660 /* Check the parameters */
\r
661 assert_param(IS_FMC_NAND_DEVICE(Device));
\r
662 assert_param(IS_FMC_NAND_BANK(Bank));
\r
664 /* Disable ECC feature */
\r
665 Device->PCR &= ~FMC_PCR_ECCEN;
\r
671 * @brief Disables dynamically FMC_NAND ECC feature.
\r
672 * @param Device: Pointer to NAND device instance
\r
673 * @param ECCval: Pointer to ECC value
\r
674 * @param Bank: NAND bank number
\r
675 * @param Timeout: Timeout wait value
\r
676 * @retval HAL status
\r
678 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
\r
680 uint32_t tickstart = 0;
\r
682 /* Check the parameters */
\r
683 assert_param(IS_FMC_NAND_DEVICE(Device));
\r
684 assert_param(IS_FMC_NAND_BANK(Bank));
\r
687 tickstart = HAL_GetTick();
\r
689 /* Wait until FIFO is empty */
\r
690 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
\r
692 /* Check for the Timeout */
\r
693 if(Timeout != HAL_MAX_DELAY)
\r
695 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
\r
697 return HAL_TIMEOUT;
\r
702 /* Get the ECCR register value */
\r
703 *ECCval = (uint32_t)Device->ECCR;
\r
716 /** @defgroup FMC_LL_SDRAM
\r
717 * @brief SDRAM Controller functions
\r
720 ==============================================================================
\r
721 ##### How to use SDRAM device driver #####
\r
722 ==============================================================================
\r
724 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
\r
725 to run the SDRAM external devices.
\r
727 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
\r
728 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
\r
729 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
\r
730 (+) FMC SDRAM bank enable/disable write operation using the functions
\r
731 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
\r
732 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
\r
738 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
\r
739 * @brief Initialization and Configuration functions
\r
742 ==============================================================================
\r
743 ##### Initialization and de_initialization functions #####
\r
744 ==============================================================================
\r
746 This section provides functions allowing to:
\r
747 (+) Initialize and configure the FMC SDRAM interface
\r
748 (+) De-initialize the FMC SDRAM interface
\r
749 (+) Configure the FMC clock and associated GPIOs
\r
756 * @brief Initializes the FMC_SDRAM device according to the specified
\r
757 * control parameters in the FMC_SDRAM_InitTypeDef
\r
758 * @param Device: Pointer to SDRAM device instance
\r
759 * @param Init: Pointer to SDRAM Initialization structure
\r
760 * @retval HAL status
\r
762 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
\r
764 uint32_t tmpr1 = 0;
\r
765 uint32_t tmpr2 = 0;
\r
767 /* Check the parameters */
\r
768 assert_param(IS_FMC_SDRAM_DEVICE(Device));
\r
769 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
\r
770 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
\r
771 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
\r
772 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
\r
773 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
\r
774 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
\r
775 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
\r
776 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
\r
777 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
\r
778 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
\r
780 /* Set SDRAM bank configuration parameters */
\r
781 if (Init->SDBank != FMC_SDRAM_BANK2)
\r
783 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
\r
785 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
\r
786 tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
\r
787 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
\r
788 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
\r
790 tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
\r
791 Init->RowBitsNumber |\
\r
792 Init->MemoryDataWidth |\
\r
793 Init->InternalBankNumber |\
\r
794 Init->CASLatency |\
\r
795 Init->WriteProtection |\
\r
796 Init->SDClockPeriod |\
\r
798 Init->ReadPipeDelay
\r
800 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
\r
802 else /* FMC_Bank2_SDRAM */
\r
804 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
\r
806 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
\r
807 tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
\r
808 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
\r
809 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
\r
811 tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
\r
813 Init->ReadPipeDelay);
\r
815 tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
\r
817 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
\r
818 tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
\r
819 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
\r
820 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
\r
822 tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
\r
823 Init->RowBitsNumber |\
\r
824 Init->MemoryDataWidth |\
\r
825 Init->InternalBankNumber |\
\r
826 Init->CASLatency |\
\r
827 Init->WriteProtection);
\r
829 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
\r
830 Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
\r
837 * @brief Initializes the FMC_SDRAM device timing according to the specified
\r
838 * parameters in the FMC_SDRAM_TimingTypeDef
\r
839 * @param Device: Pointer to SDRAM device instance
\r
840 * @param Timing: Pointer to SDRAM Timing structure
\r
841 * @param Bank: SDRAM bank number
\r
842 * @retval HAL status
\r
844 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
\r
846 uint32_t tmpr1 = 0;
\r
847 uint32_t tmpr2 = 0;
\r
849 /* Check the parameters */
\r
850 assert_param(IS_FMC_SDRAM_DEVICE(Device));
\r
851 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
\r
852 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
\r
853 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
\r
854 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
\r
855 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
\r
856 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
\r
857 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
\r
858 assert_param(IS_FMC_SDRAM_BANK(Bank));
\r
860 /* Set SDRAM device timing parameters */
\r
861 if (Bank != FMC_SDRAM_BANK2)
\r
863 tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
\r
865 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
\r
866 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
\r
867 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
\r
870 tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
\r
871 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
\r
872 (((Timing->SelfRefreshTime)-1) << 8) |\
\r
873 (((Timing->RowCycleDelay)-1) << 12) |\
\r
874 (((Timing->WriteRecoveryTime)-1) <<16) |\
\r
875 (((Timing->RPDelay)-1) << 20) |\
\r
876 (((Timing->RCDDelay)-1) << 24));
\r
877 Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
\r
879 else /* FMC_Bank2_SDRAM */
\r
881 tmpr1 = Device->SDTR[FMC_SDRAM_BANK2];
\r
883 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
\r
884 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
\r
885 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
\r
888 tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
\r
889 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
\r
890 (((Timing->SelfRefreshTime)-1) << 8) |\
\r
891 (((Timing->WriteRecoveryTime)-1) <<16) |\
\r
892 (((Timing->RCDDelay)-1) << 24));
\r
894 tmpr2 = Device->SDTR[FMC_SDRAM_BANK1];
\r
896 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
\r
897 tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
\r
898 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
\r
900 tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
\r
901 (((Timing->RPDelay)-1) << 20));
\r
903 Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
\r
904 Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;
\r
911 * @brief DeInitializes the FMC_SDRAM peripheral
\r
912 * @param Device: Pointer to SDRAM device instance
\r
913 * @retval HAL status
\r
915 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
\r
917 /* Check the parameters */
\r
918 assert_param(IS_FMC_SDRAM_DEVICE(Device));
\r
919 assert_param(IS_FMC_SDRAM_BANK(Bank));
\r
921 /* De-initialize the SDRAM device */
\r
922 Device->SDCR[Bank] = 0x000002D0;
\r
923 Device->SDTR[Bank] = 0x0FFFFFFF;
\r
924 Device->SDCMR = 0x00000000;
\r
925 Device->SDRTR = 0x00000000;
\r
926 Device->SDSR = 0x00000000;
\r
935 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
\r
936 * @brief management functions
\r
939 ==============================================================================
\r
940 ##### FMC_SDRAM Control functions #####
\r
941 ==============================================================================
\r
943 This subsection provides a set of functions allowing to control dynamically
\r
944 the FMC SDRAM interface.
\r
951 * @brief Enables dynamically FMC_SDRAM write protection.
\r
952 * @param Device: Pointer to SDRAM device instance
\r
953 * @param Bank: SDRAM bank number
\r
954 * @retval HAL status
\r
956 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
\r
958 /* Check the parameters */
\r
959 assert_param(IS_FMC_SDRAM_DEVICE(Device));
\r
960 assert_param(IS_FMC_SDRAM_BANK(Bank));
\r
962 /* Enable write protection */
\r
963 Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
\r
969 * @brief Disables dynamically FMC_SDRAM write protection.
\r
970 * @param hsdram: FMC_SDRAM handle
\r
971 * @retval HAL status
\r
973 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
\r
975 /* Check the parameters */
\r
976 assert_param(IS_FMC_SDRAM_DEVICE(Device));
\r
977 assert_param(IS_FMC_SDRAM_BANK(Bank));
\r
979 /* Disable write protection */
\r
980 Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
\r
986 * @brief Send Command to the FMC SDRAM bank
\r
987 * @param Device: Pointer to SDRAM device instance
\r
988 * @param Command: Pointer to SDRAM command structure
\r
989 * @param Timing: Pointer to SDRAM Timing structure
\r
990 * @param Timeout: Timeout wait value
\r
991 * @retval HAL state
\r
993 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
\r
995 __IO uint32_t tmpr = 0;
\r
996 uint32_t tickstart = 0;
\r
998 /* Check the parameters */
\r
999 assert_param(IS_FMC_SDRAM_DEVICE(Device));
\r
1000 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
\r
1001 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
\r
1002 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
\r
1003 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
\r
1005 /* Set command register */
\r
1006 tmpr = (uint32_t)((Command->CommandMode) |\
\r
1007 (Command->CommandTarget) |\
\r
1008 (((Command->AutoRefreshNumber)-1) << 5) |\
\r
1009 ((Command->ModeRegisterDefinition) << 9)
\r
1012 Device->SDCMR = tmpr;
\r
1015 tickstart = HAL_GetTick();
\r
1017 /* wait until command is send */
\r
1018 while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
\r
1020 /* Check for the Timeout */
\r
1021 if(Timeout != HAL_MAX_DELAY)
\r
1023 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
\r
1025 return HAL_TIMEOUT;
\r
1036 * @brief Program the SDRAM Memory Refresh rate.
\r
1037 * @param Device: Pointer to SDRAM device instance
\r
1038 * @param RefreshRate: The SDRAM refresh rate value.
\r
1039 * @retval HAL state
\r
1041 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
\r
1043 /* Check the parameters */
\r
1044 assert_param(IS_FMC_SDRAM_DEVICE(Device));
\r
1045 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
\r
1047 /* Set the refresh rate in command register */
\r
1048 Device->SDRTR |= (RefreshRate<<1);
\r
1054 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
\r
1055 * @param Device: Pointer to SDRAM device instance
\r
1056 * @param AutoRefreshNumber: Specifies the auto Refresh number.
\r
1059 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
\r
1061 /* Check the parameters */
\r
1062 assert_param(IS_FMC_SDRAM_DEVICE(Device));
\r
1063 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
\r
1065 /* Set the Auto-refresh number in command register */
\r
1066 Device->SDCMR |= (AutoRefreshNumber << 5);
\r
1072 * @brief Returns the indicated FMC SDRAM bank mode status.
\r
1073 * @param Device: Pointer to SDRAM device instance
\r
1074 * @param Bank: Defines the FMC SDRAM bank. This parameter can be
\r
1075 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
\r
1076 * @retval The FMC SDRAM bank mode status, could be on of the following values:
\r
1077 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
\r
1078 * FMC_SDRAM_POWER_DOWN_MODE.
\r
1080 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
\r
1082 uint32_t tmpreg = 0;
\r
1084 /* Check the parameters */
\r
1085 assert_param(IS_FMC_SDRAM_DEVICE(Device));
\r
1086 assert_param(IS_FMC_SDRAM_BANK(Bank));
\r
1088 /* Get the corresponding bank mode */
\r
1089 if(Bank == FMC_SDRAM_BANK1)
\r
1091 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
\r
1095 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);
\r
1098 /* Return the mode status */
\r
1113 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */
\r
1123 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r