2 ******************************************************************************
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3 * @file stm32f7xx_ll_usb.c
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4 * @author MCD Application Team
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6 * @date 24-March-2015
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7 * @brief USB Low Layer HAL module driver.
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9 * This file provides firmware functions to manage the following
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10 * functionalities of the USB Peripheral Controller:
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11 * + Initialization/de-initialization functions
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12 * + I/O operation functions
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13 * + Peripheral Control functions
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14 * + Peripheral State functions
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17 ==============================================================================
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18 ##### How to use this driver #####
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19 ==============================================================================
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21 (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
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23 (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
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25 (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
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28 ******************************************************************************
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31 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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33 * Redistribution and use in source and binary forms, with or without modification,
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34 * are permitted provided that the following conditions are met:
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35 * 1. Redistributions of source code must retain the above copyright notice,
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36 * this list of conditions and the following disclaimer.
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37 * 2. Redistributions in binary form must reproduce the above copyright notice,
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38 * this list of conditions and the following disclaimer in the documentation
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39 * and/or other materials provided with the distribution.
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40 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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41 * may be used to endorse or promote products derived from this software
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42 * without specific prior written permission.
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44 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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45 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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47 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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50 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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51 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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55 ******************************************************************************
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58 /* Includes ------------------------------------------------------------------*/
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59 #include "stm32f7xx_hal.h"
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61 /** @addtogroup STM32F7xx_LL_USB_DRIVER
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65 #if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
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67 /* Private typedef -----------------------------------------------------------*/
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68 /* Private define ------------------------------------------------------------*/
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69 /* Private macro -------------------------------------------------------------*/
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70 /* Private variables ---------------------------------------------------------*/
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71 /* Private function prototypes -----------------------------------------------*/
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72 /* Private functions ---------------------------------------------------------*/
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73 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
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75 /** @defgroup PCD_Private_Functions
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79 /** @defgroup LL_USB_Group1 Initialization/de-initialization functions
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80 * @brief Initialization and Configuration functions
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83 ===============================================================================
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84 ##### Initialization/de-initialization functions #####
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85 ===============================================================================
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86 [..] This section provides functions allowing to:
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93 * @brief Initializes the USB Core
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94 * @param USBx: USB Instance
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95 * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
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96 * the configuration information for the specified USBx peripheral.
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97 * @retval HAL status
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99 HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
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101 if (cfg.phy_itface == USB_OTG_ULPI_PHY)
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104 USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
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106 /* Init The ULPI Interface */
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107 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
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109 /* Select vbus source */
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110 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
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111 if(cfg.use_external_vbus == 1)
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113 USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
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115 /* Reset after a PHY select */
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116 USB_CoreReset(USBx);
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118 else /* FS interface (embedded Phy) */
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121 /* Select FS Embedded PHY */
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122 USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
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124 /* Reset after a PHY select and set Host mode */
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125 USB_CoreReset(USBx);
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127 /* Deactivate the power down*/
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128 USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
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131 if(cfg.dma_enable == ENABLE)
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133 USBx->GAHBCFG |= (USB_OTG_GAHBCFG_HBSTLEN_1 | USB_OTG_GAHBCFG_HBSTLEN_2);
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134 USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
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141 * @brief USB_EnableGlobalInt
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142 * Enables the controller's Global Int in the AHB Config reg
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143 * @param USBx : Selected device
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144 * @retval HAL status
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146 HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
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148 USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
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154 * @brief USB_DisableGlobalInt
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155 * Disable the controller's Global Int in the AHB Config reg
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156 * @param USBx : Selected device
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157 * @retval HAL status
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159 HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
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161 USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
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166 * @brief USB_SetCurrentMode : Set functional mode
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167 * @param USBx : Selected device
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168 * @param mode : current core mode
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169 * This parameter can be one of the these values:
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170 * @arg USB_OTG_DEVICE_MODE: Peripheral mode
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171 * @arg USB_OTG_HOST_MODE: Host mode
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172 * @arg USB_OTG_DRD_MODE: Dual Role Device mode
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173 * @retval HAL status
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175 HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)
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177 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
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179 if ( mode == USB_OTG_HOST_MODE)
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181 USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
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183 else if ( mode == USB_OTG_DEVICE_MODE)
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185 USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
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193 * @brief USB_DevInit : Initializes the USB_OTG controller registers
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195 * @param USBx : Selected device
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196 * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
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197 * the configuration information for the specified USBx peripheral.
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198 * @retval HAL status
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200 HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
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204 /*Activate VBUS Sensing B */
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205 USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
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207 if (cfg.vbus_sensing_enable == 0)
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209 /*Desactivate VBUS Sensing B */
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210 USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN;
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212 /* B-peripheral session valid override enable*/
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213 USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
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214 USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
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217 /* Restart the Phy Clock */
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220 /* Device mode configuration */
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221 USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
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223 if(cfg.phy_itface == USB_OTG_ULPI_PHY)
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225 if(cfg.speed == USB_OTG_SPEED_HIGH)
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227 /* Set High speed phy */
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228 USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);
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232 /* set High speed phy in Full speed mode */
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233 USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);
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238 /* Set Full speed phy */
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239 USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);
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242 /* Flush the FIFOs */
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243 USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */
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244 USB_FlushRxFifo(USBx);
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247 /* Clear all pending Device Interrupts */
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248 USBx_DEVICE->DIEPMSK = 0;
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249 USBx_DEVICE->DOEPMSK = 0;
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250 USBx_DEVICE->DAINT = 0xFFFFFFFF;
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251 USBx_DEVICE->DAINTMSK = 0;
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253 for (i = 0; i < cfg.dev_endpoints; i++)
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255 if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
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257 USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK);
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261 USBx_INEP(i)->DIEPCTL = 0;
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264 USBx_INEP(i)->DIEPTSIZ = 0;
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265 USBx_INEP(i)->DIEPINT = 0xFF;
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268 for (i = 0; i < cfg.dev_endpoints; i++)
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270 if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
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272 USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK);
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276 USBx_OUTEP(i)->DOEPCTL = 0;
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279 USBx_OUTEP(i)->DOEPTSIZ = 0;
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280 USBx_OUTEP(i)->DOEPINT = 0xFF;
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283 USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
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285 if (cfg.dma_enable == 1)
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287 /*Set threshold parameters */
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288 USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6);
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289 USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN);
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291 i= USBx_DEVICE->DTHRCTL;
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294 /* Disable all interrupts. */
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297 /* Clear any pending interrupts */
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298 USBx->GINTSTS = 0xBFFFFFFF;
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300 /* Enable the common interrupts */
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301 if (cfg.dma_enable == DISABLE)
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303 USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
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306 /* Enable interrupts matching to the Device mode ONLY */
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307 USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\
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308 USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\
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309 USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\
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310 USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
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314 USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
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317 if (cfg.vbus_sensing_enable == ENABLE)
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319 USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
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327 * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
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328 * @param USBx : Selected device
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329 * @param num : FIFO number
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330 * This parameter can be a value from 1 to 15
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331 15 means Flush all Tx FIFOs
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332 * @retval HAL status
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334 HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
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336 uint32_t count = 0;
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338 USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 5 ));
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342 if (++count > 200000)
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344 return HAL_TIMEOUT;
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347 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
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354 * @brief USB_FlushRxFifo : Flush Rx FIFO
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355 * @param USBx : Selected device
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356 * @retval HAL status
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358 HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
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360 uint32_t count = 0;
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362 USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
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366 if (++count > 200000)
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368 return HAL_TIMEOUT;
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371 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
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377 * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register
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378 * depending the PHY type and the enumeration speed of the device.
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379 * @param USBx : Selected device
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380 * @param speed : device speed
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381 * This parameter can be one of the these values:
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382 * @arg USB_OTG_SPEED_HIGH: High speed mode
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383 * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
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384 * @arg USB_OTG_SPEED_FULL: Full speed mode
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385 * @arg USB_OTG_SPEED_LOW: Low speed mode
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386 * @retval Hal status
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388 HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
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390 USBx_DEVICE->DCFG |= speed;
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395 * @brief USB_GetDevSpeed :Return the Dev Speed
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396 * @param USBx : Selected device
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397 * @retval speed : device speed
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398 * This parameter can be one of the these values:
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399 * @arg USB_OTG_SPEED_HIGH: High speed mode
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400 * @arg USB_OTG_SPEED_FULL: Full speed mode
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401 * @arg USB_OTG_SPEED_LOW: Low speed mode
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403 uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
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407 if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
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409 speed = USB_OTG_SPEED_HIGH;
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411 else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||
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412 ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))
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414 speed = USB_OTG_SPEED_FULL;
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416 else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
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418 speed = USB_OTG_SPEED_LOW;
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425 * @brief Activate and configure an endpoint
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426 * @param USBx : Selected device
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427 * @param ep: pointer to endpoint structure
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428 * @retval HAL status
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430 HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
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432 if (ep->is_in == 1)
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434 USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
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436 if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
\r
438 USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
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439 ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
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445 USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
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447 if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
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449 USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
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450 (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));
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456 * @brief Activate and configure a dedicated endpoint
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457 * @param USBx : Selected device
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458 * @param ep: pointer to endpoint structure
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459 * @retval HAL status
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461 HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
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463 static __IO uint32_t debug = 0;
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465 /* Read DEPCTLn register */
\r
466 if (ep->is_in == 1)
\r
468 if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
\r
470 USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
\r
471 ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
\r
475 debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
\r
476 ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
\r
478 USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
\r
482 if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
\r
484 USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
\r
485 ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));
\r
487 debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE);
\r
488 debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;
\r
489 debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
\r
490 ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));
\r
493 USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
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499 * @brief De-activate and de-initialize an endpoint
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500 * @param USBx : Selected device
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501 * @param ep: pointer to endpoint structure
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502 * @retval HAL status
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504 HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
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506 /* Read DEPCTLn register */
\r
507 if (ep->is_in == 1)
\r
509 USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
\r
510 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
\r
511 USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
\r
516 USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
\r
517 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
\r
518 USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
\r
524 * @brief De-activate and de-initialize a dedicated endpoint
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525 * @param USBx : Selected device
\r
526 * @param ep: pointer to endpoint structure
\r
527 * @retval HAL status
\r
529 HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
\r
531 /* Read DEPCTLn register */
\r
532 if (ep->is_in == 1)
\r
534 USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
\r
535 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
\r
539 USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
\r
540 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
\r
546 * @brief USB_EPStartXfer : setup and starts a transfer over an EP
\r
547 * @param USBx : Selected device
\r
548 * @param ep: pointer to endpoint structure
\r
549 * @param dma: USB dma enabled or disabled
\r
550 * This parameter can be one of the these values:
\r
551 * 0 : DMA feature not used
\r
552 * 1 : DMA feature used
\r
553 * @retval HAL status
\r
555 HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
\r
557 uint16_t pktcnt = 0;
\r
560 if (ep->is_in == 1)
\r
562 /* Zero Length Packet? */
\r
563 if (ep->xfer_len == 0)
\r
565 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
\r
566 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
\r
567 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
\r
571 /* Program the transfer size and packet count
\r
572 * as follows: xfersize = N * maxpacket +
\r
573 * short_packet pktcnt = N + (short_packet
\r
576 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
\r
577 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
\r
578 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ;
\r
579 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
\r
581 if (ep->type == EP_TYPE_ISOC)
\r
583 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
\r
584 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29));
\r
590 USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
\r
594 if (ep->type != EP_TYPE_ISOC)
\r
596 /* Enable the Tx FIFO Empty Interrupt for this EP */
\r
597 if (ep->xfer_len > 0)
\r
599 USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num;
\r
604 if (ep->type == EP_TYPE_ISOC)
\r
606 if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
\r
608 USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
\r
612 USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
\r
616 /* EP enable, IN data in FIFO */
\r
617 USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
\r
619 if (ep->type == EP_TYPE_ISOC)
\r
621 USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma);
\r
624 else /* OUT endpoint */
\r
626 /* Program the transfer size and packet count as follows:
\r
628 * xfersize = N * maxpacket
\r
630 USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
\r
631 USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
\r
633 if (ep->xfer_len == 0)
\r
635 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
\r
636 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
\r
640 pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket;
\r
641 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19));
\r
642 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt));
\r
647 USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;
\r
650 if (ep->type == EP_TYPE_ISOC)
\r
652 if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
\r
654 USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
\r
658 USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
\r
662 USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
\r
668 * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0
\r
669 * @param USBx : Selected device
\r
670 * @param ep: pointer to endpoint structure
\r
671 * @param dma: USB dma enabled or disabled
\r
672 * This parameter can be one of the these values:
\r
673 * 0 : DMA feature not used
\r
674 * 1 : DMA feature used
\r
675 * @retval HAL status
\r
677 HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
\r
680 if (ep->is_in == 1)
\r
682 /* Zero Length Packet? */
\r
683 if (ep->xfer_len == 0)
\r
685 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
\r
686 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
\r
687 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
\r
691 /* Program the transfer size and packet count
\r
692 * as follows: xfersize = N * maxpacket +
\r
693 * short_packet pktcnt = N + (short_packet
\r
696 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
\r
697 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
\r
699 if(ep->xfer_len > ep->maxpacket)
\r
701 ep->xfer_len = ep->maxpacket;
\r
703 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
\r
704 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
\r
710 USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
\r
714 /* Enable the Tx FIFO Empty Interrupt for this EP */
\r
715 if (ep->xfer_len > 0)
\r
717 USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num);
\r
721 /* EP enable, IN data in FIFO */
\r
722 USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
\r
724 else /* OUT endpoint */
\r
726 /* Program the transfer size and packet count as follows:
\r
728 * xfersize = N * maxpacket
\r
730 USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
\r
731 USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
\r
733 if (ep->xfer_len > 0)
\r
735 ep->xfer_len = ep->maxpacket;
\r
738 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));
\r
739 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
\r
744 USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);
\r
748 USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
\r
754 * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
\r
755 * with the EP/channel
\r
756 * @param USBx : Selected device
\r
757 * @param src : pointer to source buffer
\r
758 * @param ch_ep_num : endpoint or host channel number
\r
759 * @param len : Number of bytes to write
\r
760 * @param dma: USB dma enabled or disabled
\r
761 * This parameter can be one of the these values:
\r
762 * 0 : DMA feature not used
\r
763 * 1 : DMA feature used
\r
764 * @retval HAL status
\r
766 HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
\r
768 uint32_t count32b= 0 , i= 0;
\r
772 count32b = (len + 3) / 4;
\r
773 for (i = 0; i < count32b; i++, src += 4)
\r
775 USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src);
\r
782 * @brief USB_ReadPacket : read a packet from the Tx FIFO associated
\r
783 * with the EP/channel
\r
784 * @param USBx : Selected device
\r
785 * @param src : source pointer
\r
786 * @param ch_ep_num : endpoint or host channel number
\r
787 * @param len : Number of bytes to read
\r
788 * @param dma: USB dma enabled or disabled
\r
789 * This parameter can be one of the these values:
\r
790 * 0 : DMA feature not used
\r
791 * 1 : DMA feature used
\r
792 * @retval pointer to destination buffer
\r
794 void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
\r
797 uint32_t count32b = (len + 3) / 4;
\r
799 for ( i = 0; i < count32b; i++, dest += 4 )
\r
801 *(__packed uint32_t *)dest = USBx_DFIFO(0);
\r
804 return ((void *)dest);
\r
808 * @brief USB_EPSetStall : set a stall condition over an EP
\r
809 * @param USBx : Selected device
\r
810 * @param ep: pointer to endpoint structure
\r
811 * @retval HAL status
\r
813 HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
\r
815 if (ep->is_in == 1)
\r
817 if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0)
\r
819 USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
\r
821 USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
\r
825 if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0)
\r
827 USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
\r
829 USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
\r
836 * @brief USB_EPClearStall : Clear a stall condition over an EP
\r
837 * @param USBx : Selected device
\r
838 * @param ep: pointer to endpoint structure
\r
839 * @retval HAL status
\r
841 HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
\r
843 if (ep->is_in == 1)
\r
845 USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
\r
846 if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
\r
848 USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
\r
853 USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
\r
854 if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
\r
856 USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
\r
863 * @brief USB_StopDevice : Stop the usb device mode
\r
864 * @param USBx : Selected device
\r
865 * @retval HAL status
\r
867 HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
\r
871 /* Clear Pending interrupt */
\r
872 for (i = 0; i < 15 ; i++)
\r
874 USBx_INEP(i)->DIEPINT = 0xFF;
\r
875 USBx_OUTEP(i)->DOEPINT = 0xFF;
\r
877 USBx_DEVICE->DAINT = 0xFFFFFFFF;
\r
879 /* Clear interrupt masks */
\r
880 USBx_DEVICE->DIEPMSK = 0;
\r
881 USBx_DEVICE->DOEPMSK = 0;
\r
882 USBx_DEVICE->DAINTMSK = 0;
\r
884 /* Flush the FIFO */
\r
885 USB_FlushRxFifo(USBx);
\r
886 USB_FlushTxFifo(USBx , 0x10 );
\r
892 * @brief USB_SetDevAddress : Stop the usb device mode
\r
893 * @param USBx : Selected device
\r
894 * @param address : new device address to be assigned
\r
895 * This parameter can be a value from 0 to 255
\r
896 * @retval HAL status
\r
898 HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)
\r
900 USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
\r
901 USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ;
\r
907 * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
\r
908 * @param USBx : Selected device
\r
909 * @retval HAL status
\r
911 HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
\r
913 USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;
\r
920 * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
\r
921 * @param USBx : Selected device
\r
922 * @retval HAL status
\r
924 HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
\r
926 USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ;
\r
933 * @brief USB_ReadInterrupts: return the global USB interrupt status
\r
934 * @param USBx : Selected device
\r
935 * @retval HAL status
\r
937 uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
\r
942 v &= USBx->GINTMSK;
\r
947 * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
\r
948 * @param USBx : Selected device
\r
949 * @retval HAL status
\r
951 uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
\r
954 v = USBx_DEVICE->DAINT;
\r
955 v &= USBx_DEVICE->DAINTMSK;
\r
956 return ((v & 0xffff0000) >> 16);
\r
960 * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
\r
961 * @param USBx : Selected device
\r
962 * @retval HAL status
\r
964 uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
\r
967 v = USBx_DEVICE->DAINT;
\r
968 v &= USBx_DEVICE->DAINTMSK;
\r
969 return ((v & 0xFFFF));
\r
973 * @brief Returns Device OUT EP Interrupt register
\r
974 * @param USBx : Selected device
\r
975 * @param epnum : endpoint number
\r
976 * This parameter can be a value from 0 to 15
\r
977 * @retval Device OUT EP Interrupt register
\r
979 uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
\r
982 v = USBx_OUTEP(epnum)->DOEPINT;
\r
983 v &= USBx_DEVICE->DOEPMSK;
\r
988 * @brief Returns Device IN EP Interrupt register
\r
989 * @param USBx : Selected device
\r
990 * @param epnum : endpoint number
\r
991 * This parameter can be a value from 0 to 15
\r
992 * @retval Device IN EP Interrupt register
\r
994 uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
\r
996 uint32_t v, msk, emp;
\r
998 msk = USBx_DEVICE->DIEPMSK;
\r
999 emp = USBx_DEVICE->DIEPEMPMSK;
\r
1000 msk |= ((emp >> epnum) & 0x1) << 7;
\r
1001 v = USBx_INEP(epnum)->DIEPINT & msk;
\r
1006 * @brief USB_ClearInterrupts: clear a USB interrupt
\r
1007 * @param USBx : Selected device
\r
1008 * @param interrupt : interrupt flag
\r
1011 void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
\r
1013 USBx->GINTSTS |= interrupt;
\r
1017 * @brief Returns USB core mode
\r
1018 * @param USBx : Selected device
\r
1019 * @retval return core mode : Host or Device
\r
1020 * This parameter can be one of the these values:
\r
1024 uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
\r
1026 return ((USBx->GINTSTS ) & 0x1);
\r
1031 * @brief Activate EP0 for Setup transactions
\r
1032 * @param USBx : Selected device
\r
1033 * @retval HAL status
\r
1035 HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
\r
1037 /* Set the MPS of the IN EP based on the enumeration speed */
\r
1038 USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
\r
1040 if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
\r
1042 USBx_INEP(0)->DIEPCTL |= 3;
\r
1044 USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
\r
1051 * @brief Prepare the EP0 to start the first control setup
\r
1052 * @param USBx : Selected device
\r
1053 * @param dma: USB dma enabled or disabled
\r
1054 * This parameter can be one of the these values:
\r
1055 * 0 : DMA feature not used
\r
1056 * 1 : DMA feature used
\r
1057 * @param psetup : pointer to setup packet
\r
1058 * @retval HAL status
\r
1060 HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
\r
1062 USBx_OUTEP(0)->DOEPTSIZ = 0;
\r
1063 USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
\r
1064 USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8);
\r
1065 USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
\r
1069 USBx_OUTEP(0)->DOEPDMA = (uint32_t)psetup;
\r
1071 USBx_OUTEP(0)->DOEPCTL = 0x80008000;
\r
1079 * @brief Reset the USB Core (needed after USB clock settings change)
\r
1080 * @param USBx : Selected device
\r
1081 * @retval HAL status
\r
1083 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
\r
1085 uint32_t count = 0;
\r
1087 /* Wait for AHB master IDLE state. */
\r
1090 if (++count > 200000)
\r
1092 return HAL_TIMEOUT;
\r
1095 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);
\r
1097 /* Core Soft Reset */
\r
1099 USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
\r
1103 if (++count > 200000)
\r
1105 return HAL_TIMEOUT;
\r
1108 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
\r
1115 * @brief USB_HostInit : Initializes the USB OTG controller registers
\r
1117 * @param USBx : Selected device
\r
1118 * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
\r
1119 * the configuration information for the specified USBx peripheral.
\r
1120 * @retval HAL status
\r
1122 HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
\r
1126 /* Restart the Phy Clock */
\r
1129 /*Activate VBUS Sensing B */
\r
1130 USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
\r
1132 /* Disable the FS/LS support mode only */
\r
1133 if((cfg.speed == USB_OTG_SPEED_FULL)&&
\r
1134 (USBx != USB_OTG_FS))
\r
1136 USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
\r
1140 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
\r
1143 /* Make sure the FIFOs are flushed. */
\r
1144 USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */
\r
1145 USB_FlushRxFifo(USBx);
\r
1147 /* Clear all pending HC Interrupts */
\r
1148 for (i = 0; i < cfg.Host_channels; i++)
\r
1150 USBx_HC(i)->HCINT = 0xFFFFFFFF;
\r
1151 USBx_HC(i)->HCINTMSK = 0;
\r
1154 /* Enable VBUS driving */
\r
1155 USB_DriveVbus(USBx, 1);
\r
1159 /* Disable all interrupts. */
\r
1160 USBx->GINTMSK = 0;
\r
1162 /* Clear any pending interrupts */
\r
1163 USBx->GINTSTS = 0xFFFFFFFF;
\r
1166 if(USBx == USB_OTG_FS)
\r
1168 /* set Rx FIFO size */
\r
1169 USBx->GRXFSIZ = (uint32_t )0x80;
\r
1170 USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);
\r
1171 USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);
\r
1177 /* set Rx FIFO size */
\r
1178 USBx->GRXFSIZ = (uint32_t )0x200;
\r
1179 USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100 << 16)& USB_OTG_NPTXFD) | 0x200);
\r
1180 USBx->HPTXFSIZ = (uint32_t )(((0xE0 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300);
\r
1183 /* Enable the common interrupts */
\r
1184 if (cfg.dma_enable == DISABLE)
\r
1186 USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
\r
1189 /* Enable interrupts matching to the Host mode ONLY */
\r
1190 USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\
\r
1191 USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\
\r
1192 USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
\r
1198 * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
\r
1199 * HCFG register on the PHY type and set the right frame interval
\r
1200 * @param USBx : Selected device
\r
1201 * @param freq : clock frequency
\r
1202 * This parameter can be one of the these values:
\r
1203 * HCFG_48_MHZ : Full Speed 48 MHz Clock
\r
1204 * HCFG_6_MHZ : Low Speed 6 MHz Clock
\r
1205 * @retval HAL status
\r
1207 HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
\r
1209 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
\r
1210 USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);
\r
1212 if (freq == HCFG_48_MHZ)
\r
1214 USBx_HOST->HFIR = (uint32_t)48000;
\r
1216 else if (freq == HCFG_6_MHZ)
\r
1218 USBx_HOST->HFIR = (uint32_t)6000;
\r
1224 * @brief USB_OTG_ResetPort : Reset Host Port
\r
1225 * @param USBx : Selected device
\r
1226 * @retval HAL status
\r
1227 * @note : (1)The application must wait at least 10 ms
\r
1228 * before clearing the reset bit.
\r
1230 HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
\r
1232 __IO uint32_t hprt0;
\r
1234 hprt0 = USBx_HPRT0;
\r
1236 hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
\r
1237 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
\r
1239 USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
\r
1240 HAL_Delay (10); /* See Note #1 */
\r
1241 USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
\r
1246 * @brief USB_DriveVbus : activate or de-activate vbus
\r
1247 * @param state : VBUS state
\r
1248 * This parameter can be one of the these values:
\r
1249 * 0 : VBUS Active
\r
1250 * 1 : VBUS Inactive
\r
1251 * @retval HAL status
\r
1253 HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
\r
1255 __IO uint32_t hprt0;
\r
1257 hprt0 = USBx_HPRT0;
\r
1258 hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
\r
1259 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
\r
1261 if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))
\r
1263 USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
\r
1265 if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 ))
\r
1267 USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
\r
1273 * @brief Return Host Core speed
\r
1274 * @param USBx : Selected device
\r
1275 * @retval speed : Host speed
\r
1276 * This parameter can be one of the these values:
\r
1277 * @arg USB_OTG_SPEED_HIGH: High speed mode
\r
1278 * @arg USB_OTG_SPEED_FULL: Full speed mode
\r
1279 * @arg USB_OTG_SPEED_LOW: Low speed mode
\r
1281 uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
\r
1283 __IO uint32_t hprt0;
\r
1285 hprt0 = USBx_HPRT0;
\r
1286 return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
\r
1290 * @brief Return Host Current Frame number
\r
1291 * @param USBx : Selected device
\r
1292 * @retval current frame number
\r
1294 uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
\r
1296 return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
\r
1300 * @brief Initialize a host channel
\r
1301 * @param USBx : Selected device
\r
1302 * @param ch_num : Channel number
\r
1303 * This parameter can be a value from 1 to 15
\r
1304 * @param epnum : Endpoint number
\r
1305 * This parameter can be a value from 1 to 15
\r
1306 * @param dev_address : Current device address
\r
1307 * This parameter can be a value from 0 to 255
\r
1308 * @param speed : Current device speed
\r
1309 * This parameter can be one of the these values:
\r
1310 * @arg USB_OTG_SPEED_HIGH: High speed mode
\r
1311 * @arg USB_OTG_SPEED_FULL: Full speed mode
\r
1312 * @arg USB_OTG_SPEED_LOW: Low speed mode
\r
1313 * @param ep_type : Endpoint Type
\r
1314 * This parameter can be one of the these values:
\r
1315 * @arg EP_TYPE_CTRL: Control type
\r
1316 * @arg EP_TYPE_ISOC: Isochronous type
\r
1317 * @arg EP_TYPE_BULK: Bulk type
\r
1318 * @arg EP_TYPE_INTR: Interrupt type
\r
1319 * @param mps : Max Packet Size
\r
1320 * This parameter can be a value from 0 to32K
\r
1321 * @retval HAL state
\r
1323 HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
\r
1326 uint8_t dev_address,
\r
1332 /* Clear old interrupt conditions for this host channel. */
\r
1333 USBx_HC(ch_num)->HCINT = 0xFFFFFFFF;
\r
1335 /* Enable channel interrupts required for this transfer. */
\r
1338 case EP_TYPE_CTRL:
\r
1339 case EP_TYPE_BULK:
\r
1341 USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
\r
1342 USB_OTG_HCINTMSK_STALLM |\
\r
1343 USB_OTG_HCINTMSK_TXERRM |\
\r
1344 USB_OTG_HCINTMSK_DTERRM |\
\r
1345 USB_OTG_HCINTMSK_AHBERR |\
\r
1346 USB_OTG_HCINTMSK_NAKM ;
\r
1348 if (epnum & 0x80)
\r
1350 USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
\r
1354 if(USBx != USB_OTG_FS)
\r
1356 USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
\r
1360 case EP_TYPE_INTR:
\r
1362 USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
\r
1363 USB_OTG_HCINTMSK_STALLM |\
\r
1364 USB_OTG_HCINTMSK_TXERRM |\
\r
1365 USB_OTG_HCINTMSK_DTERRM |\
\r
1366 USB_OTG_HCINTMSK_NAKM |\
\r
1367 USB_OTG_HCINTMSK_AHBERR |\
\r
1368 USB_OTG_HCINTMSK_FRMORM ;
\r
1370 if (epnum & 0x80)
\r
1372 USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
\r
1376 case EP_TYPE_ISOC:
\r
1378 USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
\r
1379 USB_OTG_HCINTMSK_ACKM |\
\r
1380 USB_OTG_HCINTMSK_AHBERR |\
\r
1381 USB_OTG_HCINTMSK_FRMORM ;
\r
1383 if (epnum & 0x80)
\r
1385 USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
\r
1390 /* Enable the top level host channel interrupt. */
\r
1391 USBx_HOST->HAINTMSK |= (1 << ch_num);
\r
1393 /* Make sure host channel interrupts are enabled. */
\r
1394 USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
\r
1396 /* Program the HCCHAR register */
\r
1397 USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\
\r
1398 (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\
\r
1399 ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\
\r
1400 (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\
\r
1401 ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\
\r
1402 (mps & USB_OTG_HCCHAR_MPSIZ));
\r
1404 if (ep_type == EP_TYPE_INTR)
\r
1406 USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
\r
1413 * @brief Start a transfer over a host channel
\r
1414 * @param USBx : Selected device
\r
1415 * @param hc : pointer to host channel structure
\r
1416 * @param dma: USB dma enabled or disabled
\r
1417 * This parameter can be one of the these values:
\r
1418 * 0 : DMA feature not used
\r
1419 * 1 : DMA feature used
\r
1420 * @retval HAL state
\r
1422 #if defined (__CC_ARM) /*!< ARM Compiler */
\r
1424 #elif defined (__GNUC__) /*!< GNU Compiler */
\r
1425 #pragma GCC optimize ("O0")
\r
1426 #endif /* __CC_ARM */
\r
1427 HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
\r
1429 uint8_t is_oddframe = 0;
\r
1430 uint16_t len_words = 0;
\r
1431 uint16_t num_packets = 0;
\r
1432 uint16_t max_hc_pkt_count = 256;
\r
1434 if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))
\r
1436 if((dma == 0) && (hc->do_ping == 1))
\r
1438 USB_DoPing(USBx, hc->ch_num);
\r
1443 USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
\r
1448 /* Compute the expected number of packets associated to the transfer */
\r
1449 if (hc->xfer_len > 0)
\r
1451 num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;
\r
1453 if (num_packets > max_hc_pkt_count)
\r
1455 num_packets = max_hc_pkt_count;
\r
1456 hc->xfer_len = num_packets * hc->max_packet;
\r
1465 hc->xfer_len = num_packets * hc->max_packet;
\r
1470 /* Initialize the HCTSIZn register */
\r
1471 USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
\r
1472 ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
\r
1473 (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);
\r
1477 /* xfer_buff MUST be 32-bits aligned */
\r
1478 USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
\r
1481 is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;
\r
1482 USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
\r
1483 USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);
\r
1485 /* Set host channel enable */
\r
1486 USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
\r
1487 USBx_HC(hc->ch_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
\r
1489 if (dma == 0) /* Slave mode */
\r
1491 if((hc->ep_is_in == 0) && (hc->xfer_len > 0))
\r
1493 switch(hc->ep_type)
\r
1495 /* Non periodic transfer */
\r
1496 case EP_TYPE_CTRL:
\r
1497 case EP_TYPE_BULK:
\r
1499 len_words = (hc->xfer_len + 3) / 4;
\r
1501 /* check if there is enough space in FIFO space */
\r
1502 if(len_words > (USBx->HNPTXSTS & 0xFFFF))
\r
1504 /* need to process data in nptxfempty interrupt */
\r
1505 USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
\r
1508 /* Periodic transfer */
\r
1509 case EP_TYPE_INTR:
\r
1510 case EP_TYPE_ISOC:
\r
1511 len_words = (hc->xfer_len + 3) / 4;
\r
1512 /* check if there is enough space in FIFO space */
\r
1513 if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */
\r
1515 /* need to process data in ptxfempty interrupt */
\r
1516 USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
\r
1524 /* Write packet into the Tx FIFO. */
\r
1525 USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);
\r
1533 * @brief Read all host channel interrupts status
\r
1534 * @param USBx : Selected device
\r
1535 * @retval HAL state
\r
1537 uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
\r
1539 return ((USBx_HOST->HAINT) & 0xFFFF);
\r
1543 * @brief Halt a host channel
\r
1544 * @param USBx : Selected device
\r
1545 * @param hc_num : Host Channel number
\r
1546 * This parameter can be a value from 1 to 15
\r
1547 * @retval HAL state
\r
1549 HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
\r
1551 uint32_t count = 0;
\r
1553 /* Check for space in the request queue to issue the halt. */
\r
1554 if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18)))
\r
1556 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
\r
1558 if ((USBx->HNPTXSTS & 0xFFFF) == 0)
\r
1560 USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
\r
1561 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
\r
1562 USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
\r
1565 if (++count > 1000)
\r
1570 while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
\r
1574 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
\r
1579 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
\r
1581 if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0)
\r
1583 USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
\r
1584 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
\r
1585 USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
\r
1588 if (++count > 1000)
\r
1593 while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
\r
1597 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
\r
1605 * @brief Initiate Do Ping protocol
\r
1606 * @param USBx : Selected device
\r
1607 * @param hc_num : Host Channel number
\r
1608 * This parameter can be a value from 1 to 15
\r
1609 * @retval HAL state
\r
1611 HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
\r
1613 uint8_t num_packets = 1;
\r
1615 USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
\r
1616 USB_OTG_HCTSIZ_DOPING;
\r
1618 /* Set host channel enable */
\r
1619 USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
\r
1620 USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
\r
1626 * @brief Stop Host Core
\r
1627 * @param USBx : Selected device
\r
1628 * @retval HAL state
\r
1630 HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
\r
1633 uint32_t count = 0;
\r
1636 USB_DisableGlobalInt(USBx);
\r
1639 USB_FlushTxFifo(USBx, 0x10);
\r
1640 USB_FlushRxFifo(USBx);
\r
1642 /* Flush out any leftover queued requests. */
\r
1643 for (i = 0; i <= 15; i++)
\r
1646 value = USBx_HC(i)->HCCHAR ;
\r
1647 value |= USB_OTG_HCCHAR_CHDIS;
\r
1648 value &= ~USB_OTG_HCCHAR_CHENA;
\r
1649 value &= ~USB_OTG_HCCHAR_EPDIR;
\r
1650 USBx_HC(i)->HCCHAR = value;
\r
1653 /* Halt all channels to put them into a known state. */
\r
1654 for (i = 0; i <= 15; i++)
\r
1657 value = USBx_HC(i)->HCCHAR ;
\r
1659 value |= USB_OTG_HCCHAR_CHDIS;
\r
1660 value |= USB_OTG_HCCHAR_CHENA;
\r
1661 value &= ~USB_OTG_HCCHAR_EPDIR;
\r
1663 USBx_HC(i)->HCCHAR = value;
\r
1666 if (++count > 1000)
\r
1671 while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
\r
1674 /* Clear any pending Host interrupts */
\r
1675 USBx_HOST->HAINT = 0xFFFFFFFF;
\r
1676 USBx->GINTSTS = 0xFFFFFFFF;
\r
1677 USB_EnableGlobalInt(USBx);
\r
1684 #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
\r
1690 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r