2 ******************************************************************************
\r
3 * @file system_stm32f7xx.c
\r
4 * @author MCD Application Team
\r
6 * @date 24-March-2015
\r
7 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
\r
9 * This file provides two functions and one global variable to be called from
\r
11 * - SystemInit(): This function is called at startup just after reset and
\r
12 * before branch to main program. This call is made inside
\r
13 * the "startup_stm32f7xx.s" file.
\r
15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
\r
16 * by the user application to setup the SysTick
\r
17 * timer or configure other parameters.
\r
19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
\r
20 * be called whenever the core clock is changed
\r
21 * during program execution.
\r
24 ******************************************************************************
\r
27 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
\r
29 * Redistribution and use in source and binary forms, with or without modification,
\r
30 * are permitted provided that the following conditions are met:
\r
31 * 1. Redistributions of source code must retain the above copyright notice,
\r
32 * this list of conditions and the following disclaimer.
\r
33 * 2. Redistributions in binary form must reproduce the above copyright notice,
\r
34 * this list of conditions and the following disclaimer in the documentation
\r
35 * and/or other materials provided with the distribution.
\r
36 * 3. Neither the name of STMicroelectronics nor the names of its contributors
\r
37 * may be used to endorse or promote products derived from this software
\r
38 * without specific prior written permission.
\r
40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
\r
41 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
\r
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
\r
43 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
\r
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
\r
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
\r
46 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
\r
47 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
\r
48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
\r
49 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\r
51 ******************************************************************************
\r
54 /** @addtogroup CMSIS
\r
58 /** @addtogroup stm32f7xx_system
\r
62 /** @addtogroup STM32F7xx_System_Private_Includes
\r
66 #include "stm32f7xx.h"
\r
68 #if !defined (HSE_VALUE)
\r
69 #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
\r
70 #endif /* HSE_VALUE */
\r
72 #if !defined (HSI_VALUE)
\r
73 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
\r
74 #endif /* HSI_VALUE */
\r
80 /** @addtogroup STM32F7xx_System_Private_TypesDefinitions
\r
88 /** @addtogroup STM32F7xx_System_Private_Defines
\r
92 /************************* Miscellaneous Configuration ************************/
\r
93 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
\r
94 on EVAL board as data memory */
\r
95 /* #define DATA_IN_ExtSRAM */
\r
96 /* #define DATA_IN_ExtSDRAM */
\r
98 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
\r
99 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
\r
100 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
\r
102 /*!< Uncomment the following line if you need to relocate your vector Table in
\r
104 /* #define VECT_TAB_SRAM */
\r
105 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
\r
106 This value must be a multiple of 0x200. */
\r
107 /******************************************************************************/
\r
113 /** @addtogroup STM32F7xx_System_Private_Macros
\r
121 /** @addtogroup STM32F7xx_System_Private_Variables
\r
125 /* This variable is updated in three ways:
\r
126 1) by calling CMSIS function SystemCoreClockUpdate()
\r
127 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
\r
128 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
\r
129 Note: If you use this function to configure the system clock; then there
\r
130 is no need to call the 2 first functions listed above, since SystemCoreClock
\r
131 variable is updated automatically.
\r
133 uint32_t SystemCoreClock = 16000000;
\r
134 __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
\r
140 /** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
\r
143 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
\r
144 static void SystemInit_ExtMemCtl(void);
\r
145 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
\r
151 /** @addtogroup STM32F7xx_System_Private_Functions
\r
156 * @brief Setup the microcontroller system
\r
157 * Initialize the Embedded Flash Interface, the PLL and update the
\r
158 * SystemFrequency variable.
\r
162 void SystemInit(void)
\r
164 /* FPU settings ------------------------------------------------------------*/
\r
165 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
\r
166 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
\r
168 /* Reset the RCC clock configuration to the default reset state ------------*/
\r
169 /* Set HSION bit */
\r
170 RCC->CR |= (uint32_t)0x00000001;
\r
172 /* Reset CFGR register */
\r
173 RCC->CFGR = 0x00000000;
\r
175 /* Reset HSEON, CSSON and PLLON bits */
\r
176 RCC->CR &= (uint32_t)0xFEF6FFFF;
\r
178 /* Reset PLLCFGR register */
\r
179 RCC->PLLCFGR = 0x24003010;
\r
181 /* Reset HSEBYP bit */
\r
182 RCC->CR &= (uint32_t)0xFFFBFFFF;
\r
184 /* Disable all interrupts */
\r
185 RCC->CIR = 0x00000000;
\r
187 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
\r
188 SystemInit_ExtMemCtl();
\r
189 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
\r
191 /* Configure the Vector Table location add offset address ------------------*/
\r
192 #ifdef VECT_TAB_SRAM
\r
193 SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
\r
195 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
\r
200 * @brief Update SystemCoreClock variable according to Clock Register Values.
\r
201 * The SystemCoreClock variable contains the core clock (HCLK), it can
\r
202 * be used by the user application to setup the SysTick timer or configure
\r
203 * other parameters.
\r
205 * @note Each time the core clock (HCLK) changes, this function must be called
\r
206 * to update SystemCoreClock variable value. Otherwise, any configuration
\r
207 * based on this variable will be incorrect.
\r
209 * @note - The system frequency computed by this function is not the real
\r
210 * frequency in the chip. It is calculated based on the predefined
\r
211 * constant and the selected clock source:
\r
213 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
\r
215 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
\r
217 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
\r
218 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
\r
220 * (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value
\r
221 * 16 MHz) but the real value may vary depending on the variations
\r
222 * in voltage and temperature.
\r
224 * (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value
\r
225 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
\r
226 * frequency of the crystal used. Otherwise, this function may
\r
227 * have wrong result.
\r
229 * - The result of this function could be not correct when using fractional
\r
230 * value for HSE crystal.
\r
235 void SystemCoreClockUpdate(void)
\r
237 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
\r
239 /* Get SYSCLK source -------------------------------------------------------*/
\r
240 tmp = RCC->CFGR & RCC_CFGR_SWS;
\r
244 case 0x00: /* HSI used as system clock source */
\r
245 SystemCoreClock = HSI_VALUE;
\r
247 case 0x04: /* HSE used as system clock source */
\r
248 SystemCoreClock = HSE_VALUE;
\r
250 case 0x08: /* PLL used as system clock source */
\r
252 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
\r
253 SYSCLK = PLL_VCO / PLL_P
\r
255 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
\r
256 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
\r
258 if (pllsource != 0)
\r
260 /* HSE used as PLL clock source */
\r
261 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
\r
265 /* HSI used as PLL clock source */
\r
266 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
\r
269 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
\r
270 SystemCoreClock = pllvco/pllp;
\r
273 SystemCoreClock = HSI_VALUE;
\r
276 /* Compute HCLK frequency --------------------------------------------------*/
\r
277 /* Get HCLK prescaler */
\r
278 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
\r
279 /* HCLK frequency */
\r
280 SystemCoreClock >>= tmp;
\r
283 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
\r
285 * @brief Setup the external memory controller.
\r
286 * Called in startup_stm32f7xx.s before jump to main.
\r
287 * This function configures the external memories (SRAM/SDRAM)
\r
288 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
\r
292 void SystemInit_ExtMemCtl(void)
\r
294 #if defined (DATA_IN_ExtSDRAM)
\r
295 register uint32_t tmpreg = 0, timeout = 0xFFFF;
\r
296 register uint32_t index;
\r
298 /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
\r
300 RCC->AHB1ENR |= 0x000001F8;
\r
302 /* Connect PDx pins to FMC Alternate function */
\r
303 GPIOD->AFR[0] = 0x000000CC;
\r
304 GPIOD->AFR[1] = 0xCC000CCC;
\r
305 /* Configure PDx pins in Alternate function mode */
\r
306 GPIOD->MODER = 0xA02A000A;
\r
307 /* Configure PDx pins speed to 50 MHz */
\r
308 GPIOD->OSPEEDR = 0xA02A000A;
\r
309 /* Configure PDx pins Output type to push-pull */
\r
310 GPIOD->OTYPER = 0x00000000;
\r
311 /* No pull-up, pull-down for PDx pins */
\r
312 GPIOD->PUPDR = 0x50150005;
\r
314 /* Connect PEx pins to FMC Alternate function */
\r
315 GPIOE->AFR[0] = 0xC00000CC;
\r
316 GPIOE->AFR[1] = 0xCCCCCCCC;
\r
317 /* Configure PEx pins in Alternate function mode */
\r
318 GPIOE->MODER = 0xAAAA800A;
\r
319 /* Configure PEx pins speed to 50 MHz */
\r
320 GPIOE->OSPEEDR = 0xAAAA800A;
\r
321 /* Configure PEx pins Output type to push-pull */
\r
322 GPIOE->OTYPER = 0x00000000;
\r
323 /* No pull-up, pull-down for PEx pins */
\r
324 GPIOE->PUPDR = 0x55554005;
\r
326 /* Connect PFx pins to FMC Alternate function */
\r
327 GPIOF->AFR[0] = 0x00CCCCCC;
\r
328 GPIOF->AFR[1] = 0xCCCCC000;
\r
329 /* Configure PFx pins in Alternate function mode */
\r
330 GPIOF->MODER = 0xAA800AAA;
\r
331 /* Configure PFx pins speed to 50 MHz */
\r
332 GPIOF->OSPEEDR = 0xAA800AAA;
\r
333 /* Configure PFx pins Output type to push-pull */
\r
334 GPIOF->OTYPER = 0x00000000;
\r
335 /* No pull-up, pull-down for PFx pins */
\r
336 GPIOF->PUPDR = 0x55400555;
\r
338 /* Connect PGx pins to FMC Alternate function */
\r
339 GPIOG->AFR[0] = 0x00CC00CC;
\r
340 GPIOG->AFR[1] = 0xC000000C;
\r
341 /* Configure PGx pins in Alternate function mode */
\r
342 GPIOG->MODER = 0x80020A0A;
\r
343 /* Configure PGx pins speed to 50 MHz */
\r
344 GPIOG->OSPEEDR = 0x80020A0A;
\r
345 /* Configure PGx pins Output type to push-pull */
\r
346 GPIOG->OTYPER = 0x00000000;
\r
347 /* No pull-up, pull-down for PGx pins */
\r
348 GPIOG->PUPDR = 0x40010505;
\r
350 /* Connect PHx pins to FMC Alternate function */
\r
351 GPIOH->AFR[0] = 0x00C0CC00;
\r
352 GPIOH->AFR[1] = 0xCCCCCCCC;
\r
353 /* Configure PHx pins in Alternate function mode */
\r
354 GPIOH->MODER = 0xAAAA08A0;
\r
355 /* Configure PHx pins speed to 50 MHz */
\r
356 GPIOH->OSPEEDR = 0xAAAA08A0;
\r
357 /* Configure PHx pins Output type to push-pull */
\r
358 GPIOH->OTYPER = 0x00000000;
\r
359 /* No pull-up, pull-down for PHx pins */
\r
360 GPIOH->PUPDR = 0x55550450;
\r
362 /* Connect PIx pins to FMC Alternate function */
\r
363 GPIOI->AFR[0] = 0xCCCCCCCC;
\r
364 GPIOI->AFR[1] = 0x00000CC0;
\r
365 /* Configure PIx pins in Alternate function mode */
\r
366 GPIOI->MODER = 0x0028AAAA;
\r
367 /* Configure PIx pins speed to 50 MHz */
\r
368 GPIOI->OSPEEDR = 0x0028AAAA;
\r
369 /* Configure PIx pins Output type to push-pull */
\r
370 GPIOI->OTYPER = 0x00000000;
\r
371 /* No pull-up, pull-down for PIx pins */
\r
372 GPIOI->PUPDR = 0x00145555;
\r
374 /*-- FMC Configuration ------------------------------------------------------*/
\r
375 /* Enable the FMC interface clock */
\r
376 RCC->AHB3ENR |= 0x00000001;
\r
378 /* Configure and enable SDRAM bank1 */
\r
379 FMC_Bank5_6->SDCR[0] = 0x000019E5;
\r
380 FMC_Bank5_6->SDTR[0] = 0x01116361;
\r
382 /* SDRAM initialization sequence */
\r
383 /* Clock enable command */
\r
384 FMC_Bank5_6->SDCMR = 0x00000011;
\r
385 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
\r
386 while((tmpreg != 0) && (timeout-- > 0))
\r
388 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
\r
392 for (index = 0; index<1000; index++);
\r
395 FMC_Bank5_6->SDCMR = 0x00000012;
\r
397 while((tmpreg != 0) && (timeout-- > 0))
\r
399 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
\r
402 /* Auto refresh command */
\r
403 FMC_Bank5_6->SDCMR = 0x000000F3;
\r
405 while((tmpreg != 0) && (timeout-- > 0))
\r
407 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
\r
410 /* MRD register program */
\r
411 FMC_Bank5_6->SDCMR = 0x00046014;
\r
413 while((tmpreg != 0) && (timeout-- > 0))
\r
415 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
\r
418 /* Set refresh count */
\r
419 tmpreg = FMC_Bank5_6->SDRTR;
\r
420 FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
\r
422 /* Disable write protection */
\r
423 tmpreg = FMC_Bank5_6->SDCR[0];
\r
424 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
\r
425 #endif /* DATA_IN_ExtSDRAM */
\r
427 #if defined(DATA_IN_ExtSRAM)
\r
428 /*-- GPIOs Configuration -----------------------------------------------------*/
\r
429 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
\r
430 RCC->AHB1ENR |= 0x00000078;
\r
432 /* Connect PDx pins to FMC Alternate function */
\r
433 GPIOD->AFR[0] = 0x00CCC0CC;
\r
434 GPIOD->AFR[1] = 0xCCCCCCCC;
\r
435 /* Configure PDx pins in Alternate function mode */
\r
436 GPIOD->MODER = 0xAAAA0A8A;
\r
437 /* Configure PDx pins speed to 100 MHz */
\r
438 GPIOD->OSPEEDR = 0xFFFF0FCF;
\r
439 /* Configure PDx pins Output type to push-pull */
\r
440 GPIOD->OTYPER = 0x00000000;
\r
441 /* No pull-up, pull-down for PDx pins */
\r
442 GPIOD->PUPDR = 0x55550545;
\r
444 /* Connect PEx pins to FMC Alternate function */
\r
445 GPIOE->AFR[0] = 0xC00CC0CC;
\r
446 GPIOE->AFR[1] = 0xCCCCCCCC;
\r
447 /* Configure PEx pins in Alternate function mode */
\r
448 GPIOE->MODER = 0xAAAA828A;
\r
449 /* Configure PEx pins speed to 100 MHz */
\r
450 GPIOE->OSPEEDR = 0xFFFFC3CF;
\r
451 /* Configure PEx pins Output type to push-pull */
\r
452 GPIOE->OTYPER = 0x00000000;
\r
453 /* No pull-up, pull-down for PEx pins */
\r
454 GPIOE->PUPDR = 0x55554145;
\r
456 /* Connect PFx pins to FMC Alternate function */
\r
457 GPIOF->AFR[0] = 0x00CCCCCC;
\r
458 GPIOF->AFR[1] = 0xCCCC0000;
\r
459 /* Configure PFx pins in Alternate function mode */
\r
460 GPIOF->MODER = 0xAA000AAA;
\r
461 /* Configure PFx pins speed to 100 MHz */
\r
462 GPIOF->OSPEEDR = 0xFF000FFF;
\r
463 /* Configure PFx pins Output type to push-pull */
\r
464 GPIOF->OTYPER = 0x00000000;
\r
465 /* No pull-up, pull-down for PFx pins */
\r
466 GPIOF->PUPDR = 0x55000555;
\r
468 /* Connect PGx pins to FMC Alternate function */
\r
469 GPIOG->AFR[0] = 0x00CCCCCC;
\r
470 GPIOG->AFR[1] = 0x000000C0;
\r
471 /* Configure PGx pins in Alternate function mode */
\r
472 GPIOG->MODER = 0x00200AAA;
\r
473 /* Configure PGx pins speed to 100 MHz */
\r
474 GPIOG->OSPEEDR = 0x00300FFF;
\r
475 /* Configure PGx pins Output type to push-pull */
\r
476 GPIOG->OTYPER = 0x00000000;
\r
477 /* No pull-up, pull-down for PGx pins */
\r
478 GPIOG->PUPDR = 0x00100555;
\r
480 /*-- FMC/FSMC Configuration --------------------------------------------------*/
\r
481 /* Enable the FMC/FSMC interface clock */
\r
482 RCC->AHB3ENR |= 0x00000001;
\r
484 /* Configure and enable Bank1_SRAM2 */
\r
485 FMC_Bank1->BTCR[4] = 0x00001091;
\r
486 FMC_Bank1->BTCR[5] = 0x00110212;
\r
487 FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
\r
489 #endif /* DATA_IN_ExtSRAM */
\r
491 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
\r
504 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r