1 ;/*****************************************************************************
\r
2 ; * @file: startup_MPS_CM4.s
\r
3 ; * @purpose: CMSIS Cortex-M4 Core Device Startup File
\r
4 ; * for the ARM 'Microcontroller Prototyping System'
\r
6 ; * @date: 1. Jun. 2010
\r
7 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
\r
9 ; * Copyright (C) 2008-2010 ARM Limited. All rights reserved.
\r
10 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M4
\r
11 ; * processor based microcontrollers. This file can be freely distributed
\r
12 ; * within development tools that are supporting such ARM based processors.
\r
14 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
\r
15 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
\r
16 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
\r
17 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
\r
18 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
\r
20 ; ****************************************************************************/
\r
23 ; <h> Stack Configuration
\r
24 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
\r
26 Stack_Size EQU 0x00000800
\r
28 AREA STACK, NOINIT, READWRITE, ALIGN=3
\r
29 Stack_Mem SPACE Stack_Size
\r
33 ; <h> Heap Configuration
\r
34 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
\r
37 Heap_Size EQU 0x00000000
\r
39 AREA HEAP, NOINIT, READWRITE, ALIGN=3
\r
41 Heap_Mem SPACE Heap_Size
\r
49 ; Vector Table Mapped to Address 0 at Reset
\r
51 AREA RESET, DATA, READONLY
\r
54 __Vectors DCD __initial_sp ; Top of Stack
\r
55 DCD Reset_Handler ; Reset Handler
\r
56 DCD NMI_Handler ; NMI Handler
\r
57 DCD HardFault_Handler ; Hard Fault Handler
\r
58 DCD MemManage_Handler ; MPU Fault Handler
\r
59 DCD BusFault_Handler ; Bus Fault Handler
\r
60 DCD UsageFault_Handler ; Usage Fault Handler
\r
65 DCD SVC_Handler ; SVCall Handler
\r
66 DCD DebugMon_Handler ; Debug Monitor Handler
\r
68 DCD PendSV_Handler ; PendSV Handler
\r
69 DCD SysTick_Handler ; SysTick Handler
\r
71 ; External Interrupts
\r
72 DCD NVIC_Handler_GIRQ08 ; 40h: 0, GIRQ08
\r
73 DCD NVIC_Handler_GIRQ09 ; 44h: 1, GIRQ09
\r
74 DCD NVIC_Handler_GIRQ10 ; 48h: 2, GIRQ10
\r
75 DCD NVIC_Handler_GIRQ11 ; 4Ch: 3, GIRQ11
\r
76 DCD NVIC_Handler_GIRQ12 ; 50h: 4, GIRQ12
\r
77 DCD NVIC_Handler_GIRQ13 ; 54h: 5, GIRQ13
\r
78 DCD NVIC_Handler_GIRQ14 ; 58h: 6, GIRQ14
\r
79 DCD NVIC_Handler_GIRQ15 ; 5Ch: 7, GIRQ15
\r
80 DCD NVIC_Handler_GIRQ16 ; 60h: 8, GIRQ16
\r
81 DCD NVIC_Handler_GIRQ17 ; 64h: 9, GIRQ17
\r
82 DCD NVIC_Handler_GIRQ18 ; 68h: 10, GIRQ18
\r
83 DCD NVIC_Handler_GIRQ19 ; 6Ch: 11, GIRQ19
\r
84 DCD NVIC_Handler_GIRQ20 ; 70h: 12, GIRQ20
\r
85 DCD NVIC_Handler_GIRQ21 ; 74h: 13, GIRQ21
\r
86 DCD NVIC_Handler_GIRQ23 ; 78h: 14, GIRQ23
\r
87 DCD NVIC_Handler_GIRQ24 ; 7Ch: 15, GIRQ24
\r
88 DCD NVIC_Handler_GIRQ25 ; 80h: 16, GIRQ25
\r
89 DCD NVIC_Handler_GIRQ26 ; 84h: 17, GIRQ26
\r
90 DCD 0 ; 88h: 18, RSVD
\r
91 DCD 0 ; 8Ch: 19, RSVD
\r
92 DCD NVIC_Handler_I2C0 ; 90h: 20, I2C/SMBus 0
\r
93 DCD NVIC_Handler_I2C1 ; 94h: 21, I2C/SMBus 1
\r
94 DCD NVIC_Handler_I2C2 ; 98h: 22, I2C/SMBus 2
\r
95 DCD NVIC_Handler_I2C3 ; 9Ch: 23, I2C/SMBus 3
\r
96 DCD NVIC_Handler_DMA0 ; A0h: 24, DMA Channel 0
\r
97 DCD NVIC_Handler_DMA1 ; A4h: 25, DMA Channel 1
\r
98 DCD NVIC_Handler_DMA2 ; A8h: 26, DMA Channel 2
\r
99 DCD NVIC_Handler_DMA3 ; ACh: 27, DMA Channel 3
\r
100 DCD NVIC_Handler_DMA4 ; B0h: 28, DMA Channel 4
\r
101 DCD NVIC_Handler_DMA5 ; B4h: 29, DMA Channel 5
\r
102 DCD NVIC_Handler_DMA6 ; B8h: 30, DMA Channel 6
\r
103 DCD NVIC_Handler_DMA7 ; BCh: 31, DMA Channel 7
\r
104 DCD NVIC_Handler_DMA8 ; C0h: 32, DMA Channel 8
\r
105 DCD NVIC_Handler_DMA9 ; C4h: 33, DMA Channel 9
\r
106 DCD NVIC_Handler_DMA10 ; C8h: 34, DMA Channel 10
\r
107 DCD NVIC_Handler_DMA11 ; CCh: 35, DMA Channel 11
\r
108 DCD NVIC_Handler_DMA12 ; D0h: 36, DMA Channel 12
\r
109 DCD NVIC_Handler_DMA13 ; D4h: 37, DMA Channel 13
\r
110 DCD 0 ; D8h: 38, Unused
\r
111 DCD 0 ; DCh: 39, Unused
\r
112 DCD NVIC_Handler_UART0 ; E0h: 40, UART0
\r
113 DCD NVIC_Handler_UART1 ; E4h: 41, UART1
\r
114 DCD NVIC_Handler_EMI0 ; E8h: 42, EMI0
\r
115 DCD NVIC_Handler_EMI1 ; ECh: 43, EMI0
\r
116 DCD NVIC_Handler_EMI2 ; F0h: 44, EMI0
\r
117 DCD NVIC_Handler_ACPI_EC0_IBF ; F4h: 45, ACPI_EC0_IBF
\r
118 DCD NVIC_Handler_ACPI_EC0_OBF ; F8h: 46, ACPI_EC0_OBF
\r
119 DCD NVIC_Handler_ACPI_EC1_IBF ; FCh: 47, ACPI_EC1_IBF
\r
120 DCD NVIC_Handler_ACPI_EC1_OBF ; 100h: 48, ACPI_EC1_OBF
\r
121 DCD NVIC_Handler_ACPI_EC2_IBF ; 104h: 49, ACPI_EC0_IBF
\r
122 DCD NVIC_Handler_ACPI_EC2_OBF ; 108h: 50, ACPI_EC0_OBF
\r
123 DCD NVIC_Handler_ACPI_EC3_IBF ; 10Ch: 51, ACPI_EC1_IBF
\r
124 DCD NVIC_Handler_ACPI_EC3_OBF ; 110h: 52, ACPI_EC1_OBF
\r
125 DCD NVIC_Handler_ACPI_EC4_IBF ; 114h: 53, ACPI_EC0_IBF
\r
126 DCD NVIC_Handler_ACPI_EC4_OBF ; 118h: 54, ACPI_EC0_OBF
\r
127 DCD NVIC_Handler_PM1_CTL ; 11Ch: 55, ACPI_PM1_CTL
\r
128 DCD NVIC_Handler_PM1_EN ; 120h: 56, ACPI_PM1_EN
\r
129 DCD NVIC_Handler_PM1_STS ; 124h: 57, ACPI_PM1_STS
\r
130 DCD NVIC_Handler_MIF8042_OBF ; 128h: 58, MIF8042_OBF
\r
131 DCD NVIC_Handler_MIF8042_IBF ; 12Ch: 59, MIF8042_IBF
\r
132 DCD NVIC_Handler_MB_H2EC ; 130h: 60, Mailbox Host to EC
\r
133 DCD NVIC_Handler_MB_DATA ; 134h: 61, Mailbox Host Data
\r
134 DCD NVIC_Handler_P80A ; 138h: 62, Port 80h A
\r
135 DCD NVIC_Handler_P80B ; 13Ch: 63, Port 80h B
\r
136 DCD 0 ; 140h: 64, Reserved
\r
137 DCD NVIC_Handler_PKE_ERR ; 144h: 65, PKE Error
\r
138 DCD NVIC_Handler_PKE_END ; 148h: 66, PKE End
\r
139 DCD NVIC_Handler_TRNG ; 14Ch: 67, Random Num Gen
\r
140 DCD NVIC_Handler_AES ; 150h: 68, AES
\r
141 DCD NVIC_Handler_HASH ; 154h: 69, HASH
\r
142 DCD NVIC_Handler_PECI ; 158h: 70, PECI
\r
143 DCD NVIC_Handler_TACH0 ; 15Ch: 71, TACH0
\r
144 DCD NVIC_Handler_TACH1 ; 160h: 72, TACH1
\r
145 DCD NVIC_Handler_TACH2 ; 164h: 73, TACH2
\r
146 DCD NVIC_Handler_R2P0_FAIL ; 168h: 74, RPM2PWM 0 Fan Fail
\r
147 DCD NVIC_Handler_R2P0_STALL ; 16Ch: 75, RPM2PWM 0 Fan Stall
\r
148 DCD NVIC_Handler_R2P1_FAIL ; 170h: 76, RPM2PWM 1 Fan Fail
\r
149 DCD NVIC_Handler_R2P1_STALL ; 174h: 77, RPM2PWM 1 Fan Stall
\r
150 DCD NVIC_Handler_ADC_SNGL ; 178h: 78, ADC_SNGL
\r
151 DCD NVIC_Handler_ADC_RPT ; 17Ch: 79, ADC_RPT
\r
152 DCD NVIC_Handler_RCID0 ; 180h: 80, RCID 0
\r
153 DCD NVIC_Handler_RCID1 ; 184h: 81, RCID 1
\r
154 DCD NVIC_Handler_RCID2 ; 188h: 82, RCID 2
\r
155 DCD NVIC_Handler_LED0 ; 18Ch: 83, LED0
\r
156 DCD NVIC_Handler_LED1 ; 190h: 84, LED1
\r
157 DCD NVIC_Handler_LED2 ; 194h: 85, LED2
\r
158 DCD NVIC_Handler_LED3 ; 198h: 86, LED2
\r
159 DCD NVIC_Handler_PHOT ; 19Ch: 87, ProcHot Monitor
\r
160 DCD NVIC_Handler_PWRGD0 ; 1A0h: 88, PowerGuard 0 Status
\r
161 DCD NVIC_Handler_PWRGD1 ; 1A4h: 89, PowerGuard 1 Status
\r
162 DCD NVIC_Handler_LPCBERR ; 1A8h: 90, LPC Bus Error
\r
163 DCD NVIC_Handler_QMSPI0 ; 1ACh: 91, QMSPI 0
\r
164 DCD NVIC_Handler_GPSPI0_TX ; 1B0h: 92, GP-SPI0 TX
\r
165 DCD NVIC_Handler_GPSPI0_RX ; 1B4h: 93, GP-SPI0 RX
\r
166 DCD NVIC_Handler_GPSPI1_TX ; 1B8h: 94, GP-SPI1 TX
\r
167 DCD NVIC_Handler_GPSPI1_RX ; 1BCh: 95, GP-SPI1 RX
\r
168 DCD NVIC_Handler_BC0_BUSY ; 1C0h: 96, BC-Link0 Busy-Clear
\r
169 DCD NVIC_Handler_BC0_ERR ; 1C4h: 97, BC-Link0 Error
\r
170 DCD NVIC_Handler_BC1_BUSY ; 1C8h: 98, BC-Link1 Busy-Clear
\r
171 DCD NVIC_Handler_BC1_ERR ; 1CCh: 99, BC-Link1 Error
\r
172 DCD NVIC_Handler_PS2_0 ; 1D0h: 100, PS2_0
\r
173 DCD NVIC_Handler_PS2_1 ; 1D4h: 101, PS2_1
\r
174 DCD NVIC_Handler_PS2_2 ; 1D8h: 102, PS2_2
\r
175 DCD NVIC_Handler_ESPI_PC ; 1DCh: 103, eSPI Periph Chan
\r
176 DCD NVIC_Handler_ESPI_BM1 ; 1E0h: 104, eSPI Bus Master 1
\r
177 DCD NVIC_Handler_ESPI_BM2 ; 1E4h: 105, eSPI Bus Master 2
\r
178 DCD NVIC_Handler_ESPI_LTR ; 1E8h: 106, eSPI LTR
\r
179 DCD NVIC_Handler_ESPI_OOB_UP ; 1ECh: 107, eSPI Bus Master 1
\r
180 DCD NVIC_Handler_ESPI_OOB_DN ; 1F0h: 108, eSPI Bus Master 2
\r
181 DCD NVIC_Handler_ESPI_FLASH ; 1F4h: 109, eSPI Flash Chan
\r
182 DCD NVIC_Handler_ESPI_RESET ; 1F8h: 110, eSPI Reset
\r
183 DCD NVIC_Handler_RTMR ; 1FCh: 111, RTOS Timer
\r
184 DCD NVIC_Handler_HTMR0 ; 200h: 112, Hibernation Timer 0
\r
185 DCD NVIC_Handler_HTMR1 ; 204h: 113, Hibernation Timer 1
\r
186 DCD NVIC_Handler_WK ; 208h: 114, Week Alarm
\r
187 DCD NVIC_Handler_WKSUB ; 20Ch: 115, Week Alarm, sub week
\r
188 DCD NVIC_Handler_WKSEC ; 210h: 116, Week Alarm, one sec
\r
189 DCD NVIC_Handler_WKSUBSEC ; 214h: 117, Week Alarm, sub sec
\r
190 DCD NVIC_Handler_SYSPWR ; 218h: 118, System Power Present pin
\r
191 DCD NVIC_Handler_RTC ; 21Ch: 119, RTC
\r
192 DCD NVIC_Handler_RTC_ALARM ; 220h: 120, RTC_ALARM
\r
193 DCD NVIC_Handler_VCI_OVRD_IN ; 224h: 121, VCI Override Input
\r
194 DCD NVIC_Handler_VCI_IN0 ; 228h: 122, VCI Input 0
\r
195 DCD NVIC_Handler_VCI_IN1 ; 22Ch: 123, VCI Input 1
\r
196 DCD NVIC_Handler_VCI_IN2 ; 230h: 124, VCI Input 2
\r
197 DCD NVIC_Handler_VCI_IN3 ; 234h: 125, VCI Input 3
\r
198 DCD NVIC_Handler_VCI_IN4 ; 238h: 126, VCI Input 4
\r
199 DCD NVIC_Handler_VCI_IN5 ; 23Ch: 127, VCI Input 5
\r
200 DCD NVIC_Handler_VCI_IN6 ; 240h: 128, VCI Input 6
\r
201 DCD NVIC_Handler_PS20A_WAKE ; 244h: 129, PS2 Port 0A Wake
\r
202 DCD NVIC_Handler_PS20B_WAKE ; 248h: 130, PS2 Port 0B Wake
\r
203 DCD NVIC_Handler_PS21A_WAKE ; 24Ch: 131, PS2 Port 1A Wake
\r
204 DCD NVIC_Handler_PS21B_WAKE ; 250h: 132, PS2 Port 1B Wake
\r
205 DCD NVIC_Handler_PS21_WAKE ; 254h: 133, PS2 Port 1 Wake
\r
206 DCD NVIC_Handler_ENVMON ; 258h: 134, Thernal Monitor
\r
207 DCD NVIC_Handler_KEYSCAN ; 25Ch: 135, Key Scan
\r
208 DCD NVIC_Handler_BTMR16_0 ; 260h: 136, 16-bit Basic Timer 0
\r
209 DCD NVIC_Handler_BTMR16_1 ; 264h: 137, 16-bit Basic Timer 1
\r
210 DCD NVIC_Handler_BTMR16_2 ; 268h: 138, 16-bit Basic Timer 2
\r
211 DCD NVIC_Handler_BTMR16_3 ; 26Ch: 139, 16-bit Basic Timer 3
\r
212 DCD NVIC_Handler_BTMR32_0 ; 270h: 140, 32-bit Basic Timer 0
\r
213 DCD NVIC_Handler_BTMR32_1 ; 274h: 141, 32-bit Basic Timer 1
\r
214 DCD NVIC_Handler_EVTMR0 ; 278h: 142, Event Counter/Timer 0
\r
215 DCD NVIC_Handler_EVTMR1 ; 27Ch: 143, Event Counter/Timer 1
\r
216 DCD NVIC_Handler_EVTMR2 ; 280h: 144, Event Counter/Timer 2
\r
217 DCD NVIC_Handler_EVTMR3 ; 284h: 145, Event Counter/Timer 3
\r
218 DCD NVIC_Handler_CAPTMR ; 288h: 146, Capture Timer
\r
219 DCD NVIC_Handler_CAP0 ; 28Ch: 147, Capture 0 Event
\r
220 DCD NVIC_Handler_CAP1 ; 290h: 148, Capture 1 Event
\r
221 DCD NVIC_Handler_CAP2 ; 294h: 149, Capture 2 Event
\r
222 DCD NVIC_Handler_CAP3 ; 298h: 150, Capture 3 Event
\r
223 DCD NVIC_Handler_CAP4 ; 29Ch: 151, Capture 4 Event
\r
224 DCD NVIC_Handler_CAP5 ; 2A0h: 152, Capture 5 Event
\r
225 DCD NVIC_Handler_CMP0 ; 2A4h: 153, Compare 0 Event
\r
226 DCD NVIC_Handler_CMP1 ; 2A8h: 154, Compare 1 Event
\r
227 ; Project build information
\r
229 AREA |.text|, CODE, READONLY
\r
230 ; AREA RESET, CODE, READONLY
\r
235 EXPORT Reset_Handler [WEAK]
\r
239 ; Remap vector table
\r
241 LDR R1, =0xE000ED08
\r
245 IF {CPU} = "Cortex-M4.fp"
\r
246 LDR R0, =0xE000ED88 ; Enable CP10,CP11
\r
248 ORR R1,R1,#(0xF << 20)
\r
257 ; Dummy Exception Handlers (infinite loops which can be modified)
\r
260 EXPORT NMI_Handler [WEAK]
\r
265 EXPORT HardFault_Handler [WEAK]
\r
270 EXPORT MemManage_Handler [WEAK]
\r
275 EXPORT BusFault_Handler [WEAK]
\r
278 UsageFault_Handler\
\r
280 EXPORT UsageFault_Handler [WEAK]
\r
284 EXPORT SVC_Handler [WEAK]
\r
289 EXPORT DebugMon_Handler [WEAK]
\r
292 PendSV_Handler PROC
\r
293 EXPORT PendSV_Handler [WEAK]
\r
296 SysTick_Handler PROC
\r
297 EXPORT SysTick_Handler [WEAK]
\r
301 Default_Handler PROC
\r
303 EXPORT NVIC_Handler_GIRQ08 [WEAK]
\r
304 EXPORT NVIC_Handler_GIRQ09 [WEAK]
\r
305 EXPORT NVIC_Handler_GIRQ10 [WEAK]
\r
306 EXPORT NVIC_Handler_GIRQ11 [WEAK]
\r
307 EXPORT NVIC_Handler_GIRQ12 [WEAK]
\r
308 EXPORT NVIC_Handler_GIRQ13 [WEAK]
\r
309 EXPORT NVIC_Handler_GIRQ14 [WEAK]
\r
310 EXPORT NVIC_Handler_GIRQ15 [WEAK]
\r
311 EXPORT NVIC_Handler_GIRQ16 [WEAK]
\r
312 EXPORT NVIC_Handler_GIRQ17 [WEAK]
\r
313 EXPORT NVIC_Handler_GIRQ18 [WEAK]
\r
314 EXPORT NVIC_Handler_GIRQ19 [WEAK]
\r
315 EXPORT NVIC_Handler_GIRQ20 [WEAK]
\r
316 EXPORT NVIC_Handler_GIRQ21 [WEAK]
\r
317 EXPORT NVIC_Handler_GIRQ23 [WEAK]
\r
318 EXPORT NVIC_Handler_GIRQ24 [WEAK]
\r
319 EXPORT NVIC_Handler_GIRQ25 [WEAK]
\r
320 EXPORT NVIC_Handler_GIRQ26 [WEAK]
\r
322 EXPORT NVIC_Handler_I2C0 [WEAK]
\r
323 EXPORT NVIC_Handler_I2C1 [WEAK]
\r
324 EXPORT NVIC_Handler_I2C2 [WEAK]
\r
325 EXPORT NVIC_Handler_I2C3 [WEAK]
\r
326 EXPORT NVIC_Handler_DMA0 [WEAK]
\r
327 EXPORT NVIC_Handler_DMA1 [WEAK]
\r
328 EXPORT NVIC_Handler_DMA2 [WEAK]
\r
329 EXPORT NVIC_Handler_DMA3 [WEAK]
\r
330 EXPORT NVIC_Handler_DMA4 [WEAK]
\r
331 EXPORT NVIC_Handler_DMA5 [WEAK]
\r
332 EXPORT NVIC_Handler_DMA6 [WEAK]
\r
333 EXPORT NVIC_Handler_DMA7 [WEAK]
\r
334 EXPORT NVIC_Handler_DMA8 [WEAK]
\r
335 EXPORT NVIC_Handler_DMA9 [WEAK]
\r
336 EXPORT NVIC_Handler_DMA10 [WEAK]
\r
337 EXPORT NVIC_Handler_DMA11 [WEAK]
\r
338 EXPORT NVIC_Handler_DMA12 [WEAK]
\r
339 EXPORT NVIC_Handler_DMA13 [WEAK]
\r
341 EXPORT NVIC_Handler_UART0 [WEAK]
\r
342 EXPORT NVIC_Handler_UART1 [WEAK]
\r
343 EXPORT NVIC_Handler_EMI0 [WEAK]
\r
344 EXPORT NVIC_Handler_EMI1 [WEAK]
\r
345 EXPORT NVIC_Handler_EMI2 [WEAK]
\r
346 EXPORT NVIC_Handler_ACPI_EC0_IBF [WEAK]
\r
347 EXPORT NVIC_Handler_ACPI_EC0_OBF [WEAK]
\r
348 EXPORT NVIC_Handler_ACPI_EC1_IBF [WEAK]
\r
349 EXPORT NVIC_Handler_ACPI_EC1_OBF [WEAK]
\r
350 EXPORT NVIC_Handler_ACPI_EC2_IBF [WEAK]
\r
351 EXPORT NVIC_Handler_ACPI_EC2_OBF [WEAK]
\r
352 EXPORT NVIC_Handler_ACPI_EC3_IBF [WEAK]
\r
353 EXPORT NVIC_Handler_ACPI_EC3_OBF [WEAK]
\r
354 EXPORT NVIC_Handler_ACPI_EC4_IBF [WEAK]
\r
355 EXPORT NVIC_Handler_ACPI_EC4_OBF [WEAK]
\r
356 EXPORT NVIC_Handler_PM1_CTL [WEAK]
\r
357 EXPORT NVIC_Handler_PM1_EN [WEAK]
\r
358 EXPORT NVIC_Handler_PM1_STS [WEAK]
\r
359 EXPORT NVIC_Handler_MIF8042_OBF [WEAK]
\r
360 EXPORT NVIC_Handler_MIF8042_IBF [WEAK]
\r
361 EXPORT NVIC_Handler_MB_H2EC [WEAK]
\r
362 EXPORT NVIC_Handler_MB_DATA [WEAK]
\r
363 EXPORT NVIC_Handler_P80A [WEAK]
\r
364 EXPORT NVIC_Handler_P80B [WEAK]
\r
366 EXPORT NVIC_Handler_PKE_ERR [WEAK]
\r
367 EXPORT NVIC_Handler_PKE_END [WEAK]
\r
368 EXPORT NVIC_Handler_TRNG [WEAK]
\r
369 EXPORT NVIC_Handler_AES [WEAK]
\r
370 EXPORT NVIC_Handler_HASH [WEAK]
\r
371 EXPORT NVIC_Handler_PECI [WEAK]
\r
372 EXPORT NVIC_Handler_TACH0 [WEAK]
\r
373 EXPORT NVIC_Handler_TACH1 [WEAK]
\r
374 EXPORT NVIC_Handler_TACH2 [WEAK]
\r
375 EXPORT NVIC_Handler_R2P0_FAIL [WEAK]
\r
376 EXPORT NVIC_Handler_R2P0_STALL [WEAK]
\r
377 EXPORT NVIC_Handler_R2P1_FAIL [WEAK]
\r
378 EXPORT NVIC_Handler_R2P1_STALL [WEAK]
\r
379 EXPORT NVIC_Handler_ADC_SNGL [WEAK]
\r
380 EXPORT NVIC_Handler_ADC_RPT [WEAK]
\r
381 EXPORT NVIC_Handler_RCID0 [WEAK]
\r
382 EXPORT NVIC_Handler_RCID1 [WEAK]
\r
383 EXPORT NVIC_Handler_RCID2 [WEAK]
\r
384 EXPORT NVIC_Handler_LED0 [WEAK]
\r
385 EXPORT NVIC_Handler_LED1 [WEAK]
\r
386 EXPORT NVIC_Handler_LED2 [WEAK]
\r
387 EXPORT NVIC_Handler_LED3 [WEAK]
\r
388 EXPORT NVIC_Handler_PHOT [WEAK]
\r
389 EXPORT NVIC_Handler_PWRGD0 [WEAK]
\r
390 EXPORT NVIC_Handler_PWRGD1 [WEAK]
\r
391 EXPORT NVIC_Handler_LPCBERR [WEAK]
\r
392 EXPORT NVIC_Handler_QMSPI0 [WEAK]
\r
393 EXPORT NVIC_Handler_GPSPI0_TX [WEAK]
\r
394 EXPORT NVIC_Handler_GPSPI0_RX [WEAK]
\r
395 EXPORT NVIC_Handler_GPSPI1_TX [WEAK]
\r
396 EXPORT NVIC_Handler_GPSPI1_RX [WEAK]
\r
397 EXPORT NVIC_Handler_BC0_BUSY [WEAK]
\r
398 EXPORT NVIC_Handler_BC0_ERR [WEAK]
\r
399 EXPORT NVIC_Handler_BC1_BUSY [WEAK]
\r
400 EXPORT NVIC_Handler_BC1_ERR [WEAK]
\r
401 EXPORT NVIC_Handler_PS2_0 [WEAK]
\r
402 EXPORT NVIC_Handler_PS2_1 [WEAK]
\r
403 EXPORT NVIC_Handler_PS2_2 [WEAK]
\r
404 EXPORT NVIC_Handler_ESPI_PC [WEAK]
\r
405 EXPORT NVIC_Handler_ESPI_BM1 [WEAK]
\r
406 EXPORT NVIC_Handler_ESPI_BM2 [WEAK]
\r
407 EXPORT NVIC_Handler_ESPI_LTR [WEAK]
\r
408 EXPORT NVIC_Handler_ESPI_OOB_UP [WEAK]
\r
409 EXPORT NVIC_Handler_ESPI_OOB_DN [WEAK]
\r
410 EXPORT NVIC_Handler_ESPI_FLASH [WEAK]
\r
411 EXPORT NVIC_Handler_ESPI_RESET [WEAK]
\r
412 EXPORT NVIC_Handler_RTMR [WEAK]
\r
413 EXPORT NVIC_Handler_HTMR0 [WEAK]
\r
414 EXPORT NVIC_Handler_HTMR1 [WEAK]
\r
415 EXPORT NVIC_Handler_WK [WEAK]
\r
416 EXPORT NVIC_Handler_WKSUB [WEAK]
\r
417 EXPORT NVIC_Handler_WKSEC [WEAK]
\r
418 EXPORT NVIC_Handler_WKSUBSEC [WEAK]
\r
419 EXPORT NVIC_Handler_SYSPWR [WEAK]
\r
420 EXPORT NVIC_Handler_RTC [WEAK]
\r
421 EXPORT NVIC_Handler_RTC_ALARM [WEAK]
\r
422 EXPORT NVIC_Handler_VCI_OVRD_IN [WEAK]
\r
423 EXPORT NVIC_Handler_VCI_IN0 [WEAK]
\r
424 EXPORT NVIC_Handler_VCI_IN1 [WEAK]
\r
425 EXPORT NVIC_Handler_VCI_IN2 [WEAK]
\r
426 EXPORT NVIC_Handler_VCI_IN3 [WEAK]
\r
427 EXPORT NVIC_Handler_VCI_IN4 [WEAK]
\r
428 EXPORT NVIC_Handler_VCI_IN5 [WEAK]
\r
429 EXPORT NVIC_Handler_VCI_IN6 [WEAK]
\r
430 EXPORT NVIC_Handler_PS20A_WAKE [WEAK]
\r
431 EXPORT NVIC_Handler_PS20B_WAKE [WEAK]
\r
432 EXPORT NVIC_Handler_PS21A_WAKE [WEAK]
\r
433 EXPORT NVIC_Handler_PS21B_WAKE [WEAK]
\r
434 EXPORT NVIC_Handler_PS21_WAKE [WEAK]
\r
435 EXPORT NVIC_Handler_ENVMON [WEAK]
\r
436 EXPORT NVIC_Handler_KEYSCAN [WEAK]
\r
437 EXPORT NVIC_Handler_BTMR16_0 [WEAK]
\r
438 EXPORT NVIC_Handler_BTMR16_1 [WEAK]
\r
439 EXPORT NVIC_Handler_BTMR16_2 [WEAK]
\r
440 EXPORT NVIC_Handler_BTMR16_3 [WEAK]
\r
441 EXPORT NVIC_Handler_BTMR32_0 [WEAK]
\r
442 EXPORT NVIC_Handler_BTMR32_1 [WEAK]
\r
443 EXPORT NVIC_Handler_EVTMR0 [WEAK]
\r
444 EXPORT NVIC_Handler_EVTMR1 [WEAK]
\r
445 EXPORT NVIC_Handler_EVTMR2 [WEAK]
\r
446 EXPORT NVIC_Handler_EVTMR3 [WEAK]
\r
447 EXPORT NVIC_Handler_CAPTMR [WEAK]
\r
448 EXPORT NVIC_Handler_CAP0 [WEAK]
\r
449 EXPORT NVIC_Handler_CAP1 [WEAK]
\r
450 EXPORT NVIC_Handler_CAP2 [WEAK]
\r
451 EXPORT NVIC_Handler_CAP3 [WEAK]
\r
452 EXPORT NVIC_Handler_CAP4 [WEAK]
\r
453 EXPORT NVIC_Handler_CAP5 [WEAK]
\r
454 EXPORT NVIC_Handler_CMP0 [WEAK]
\r
455 EXPORT NVIC_Handler_CMP1 [WEAK]
\r
457 NVIC_Handler_GIRQ08
\r
458 NVIC_Handler_GIRQ09
\r
459 NVIC_Handler_GIRQ10
\r
460 NVIC_Handler_GIRQ11
\r
461 NVIC_Handler_GIRQ12
\r
462 NVIC_Handler_GIRQ13
\r
463 NVIC_Handler_GIRQ14
\r
464 NVIC_Handler_GIRQ15
\r
465 NVIC_Handler_GIRQ16
\r
466 NVIC_Handler_GIRQ17
\r
467 NVIC_Handler_GIRQ18
\r
468 NVIC_Handler_GIRQ19
\r
469 NVIC_Handler_GIRQ20
\r
470 NVIC_Handler_GIRQ21
\r
471 NVIC_Handler_GIRQ23
\r
472 NVIC_Handler_GIRQ24
\r
473 NVIC_Handler_GIRQ25
\r
474 NVIC_Handler_GIRQ26
\r
500 NVIC_Handler_ACPI_EC0_IBF
\r
501 NVIC_Handler_ACPI_EC0_OBF
\r
502 NVIC_Handler_ACPI_EC1_IBF
\r
503 NVIC_Handler_ACPI_EC1_OBF
\r
504 NVIC_Handler_ACPI_EC2_IBF
\r
505 NVIC_Handler_ACPI_EC2_OBF
\r
506 NVIC_Handler_ACPI_EC3_IBF
\r
507 NVIC_Handler_ACPI_EC3_OBF
\r
508 NVIC_Handler_ACPI_EC4_IBF
\r
509 NVIC_Handler_ACPI_EC4_OBF
\r
510 NVIC_Handler_PM1_CTL
\r
511 NVIC_Handler_PM1_EN
\r
512 NVIC_Handler_PM1_STS
\r
513 NVIC_Handler_MIF8042_OBF
\r
514 NVIC_Handler_MIF8042_IBF
\r
515 NVIC_Handler_MB_H2EC
\r
516 NVIC_Handler_MB_DATA
\r
520 NVIC_Handler_PKE_ERR
\r
521 NVIC_Handler_PKE_END
\r
529 NVIC_Handler_R2P0_FAIL
\r
530 NVIC_Handler_R2P0_STALL
\r
531 NVIC_Handler_R2P1_FAIL
\r
532 NVIC_Handler_R2P1_STALL
\r
533 NVIC_Handler_ADC_SNGL
\r
534 NVIC_Handler_ADC_RPT
\r
543 NVIC_Handler_PWRGD0
\r
544 NVIC_Handler_PWRGD1
\r
545 NVIC_Handler_LPCBERR
\r
546 NVIC_Handler_QMSPI0
\r
547 NVIC_Handler_GPSPI0_TX
\r
548 NVIC_Handler_GPSPI0_RX
\r
549 NVIC_Handler_GPSPI1_TX
\r
550 NVIC_Handler_GPSPI1_RX
\r
551 NVIC_Handler_BC0_BUSY
\r
552 NVIC_Handler_BC0_ERR
\r
553 NVIC_Handler_BC1_BUSY
\r
554 NVIC_Handler_BC1_ERR
\r
558 NVIC_Handler_ESPI_PC
\r
559 NVIC_Handler_ESPI_BM1
\r
560 NVIC_Handler_ESPI_BM2
\r
561 NVIC_Handler_ESPI_LTR
\r
562 NVIC_Handler_ESPI_OOB_UP
\r
563 NVIC_Handler_ESPI_OOB_DN
\r
564 NVIC_Handler_ESPI_FLASH
\r
565 NVIC_Handler_ESPI_RESET
\r
572 NVIC_Handler_WKSUBSEC
\r
573 NVIC_Handler_SYSPWR
\r
575 NVIC_Handler_RTC_ALARM
\r
576 NVIC_Handler_VCI_OVRD_IN
\r
577 NVIC_Handler_VCI_IN0
\r
578 NVIC_Handler_VCI_IN1
\r
579 NVIC_Handler_VCI_IN2
\r
580 NVIC_Handler_VCI_IN3
\r
581 NVIC_Handler_VCI_IN4
\r
582 NVIC_Handler_VCI_IN5
\r
583 NVIC_Handler_VCI_IN6
\r
584 NVIC_Handler_PS20A_WAKE
\r
585 NVIC_Handler_PS20B_WAKE
\r
586 NVIC_Handler_PS21A_WAKE
\r
587 NVIC_Handler_PS21B_WAKE
\r
588 NVIC_Handler_PS21_WAKE
\r
589 NVIC_Handler_ENVMON
\r
590 NVIC_Handler_KEYSCAN
\r
591 NVIC_Handler_BTMR16_0
\r
592 NVIC_Handler_BTMR16_1
\r
593 NVIC_Handler_BTMR16_2
\r
594 NVIC_Handler_BTMR16_3
\r
595 NVIC_Handler_BTMR32_0
\r
596 NVIC_Handler_BTMR32_1
\r
597 NVIC_Handler_EVTMR0
\r
598 NVIC_Handler_EVTMR1
\r
599 NVIC_Handler_EVTMR2
\r
600 NVIC_Handler_EVTMR3
\r
601 NVIC_Handler_CAPTMR
\r
618 ; User Initial Stack & Heap
\r
622 EXPORT __initial_sp
\r
624 EXPORT __heap_limit
\r
628 IMPORT __use_two_region_memory
\r
629 EXPORT __user_initial_stackheap
\r
630 __user_initial_stackheap
\r
633 LDR R1, =(Stack_Mem + Stack_Size)
\r
634 LDR R2, = (Heap_Mem + Heap_Size)
\r
635 LDR R3, = Stack_Mem
\r