1 /*****************************************************************************
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2 * © 2015 Microchip Technology Inc. and its subsidiaries.
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3 * You may use this software and any derivatives exclusively with
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4 * Microchip products.
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5 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
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6 * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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7 * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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8 * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
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9 * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
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10 * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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11 * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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12 * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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13 * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
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14 * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
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15 * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
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16 * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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17 * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
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19 ******************************************************************************
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21 Version Control Information (Perforce)
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22 ******************************************************************************
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24 $DateTime: 2016/09/22 08:03:49 $
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26 Last Change: Updated for tabs
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27 ******************************************************************************/
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29 * \brief Power, Clocks, and Resets Header file
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32 * This file is the PCR header file
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33 ******************************************************************************/
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43 /******************************************************************************/
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44 /** PCR Register IDS
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45 *******************************************************************************/
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46 enum _PCR_REGSET_ID_
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48 PCR_REG_SYSTEM_SLEEP_CTRL = 0,
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49 PCR_REG_PROCESSOR_CLK_CTRL,
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50 PCR_REG_SLOW_CLK_CTRL,
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51 PCR_REG_OSCILLATOR_ID,
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52 PCR_REG_PWR_RESET_STS,
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53 PCR_REG_PWR_RESET_CTRL,
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54 PCR_REG_SYSTEM_RESET,
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57 PCR_REG_EC_SLEEP_ENABLE_0 = 12,
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58 PCR_REG_EC_SLEEP_ENABLE_1,
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59 PCR_REG_EC_SLEEP_ENABLE_2,
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60 PCR_REG_EC_SLEEP_ENABLE_3,
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61 PCR_REG_EC_SLEEP_ENABLE_4,
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62 PCR_REG_EC_CLK_REQD_STS_0 = 20,
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63 PCR_REG_EC_CLK_REQD_STS_1,
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64 PCR_REG_EC_CLK_REQD_STS_2,
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65 PCR_REG_EC_CLK_REQD_STS_3,
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66 PCR_REG_EC_CLK_REQD_STS_4,
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67 PCR_REG_EC_RESET_ENABLE_0 = 28,
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68 PCR_REG_EC_RESET_ENABLE_1,
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69 PCR_REG_EC_RESET_ENABLE_2,
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70 PCR_REG_EC_RESET_ENABLE_3,
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71 PCR_REG_EC_RESET_ENABLE_4,
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74 /* ---------------------------------------------------------------------- */
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76 // Encode the Register ids for Sleep Enable, Clock Required, Reset Enable
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77 //PCR register group 0 - EC 0
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78 #define PCR0_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_0) & 0xFF) + \
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79 (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_0) & 0xFF)<<8u) + \
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80 (((uint32_t)(PCR_REG_EC_RESET_ENABLE_0) & 0xFF)<<16u))
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82 //PCR register group 1 - EC 1
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83 #define PCR1_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_1) & 0xFF) + \
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84 (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_1) & 0xFF)<<8u) + \
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85 (((uint32_t)(PCR_REG_EC_RESET_ENABLE_1) & 0xFF)<<16u))
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87 //PCR register group 2 - EC 2
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88 #define PCR2_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_2) & 0xFF) + \
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89 (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_2) & 0xFF)<<8u) + \
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90 (((uint32_t)(PCR_REG_EC_RESET_ENABLE_2) & 0xFF)<<16u))
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92 //PCR register group 3 - EC 3
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93 #define PCR3_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_3) & 0xFF) + \
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94 (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_3) & 0xFF)<<8u) + \
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95 (((uint32_t)(PCR_REG_EC_RESET_ENABLE_3) & 0xFF)<<16u))
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97 //PCR register group 4 - EC 4
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98 #define PCR4_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_4) & 0xFF) + \
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99 (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_4) & 0xFF)<<8u) + \
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100 (((uint32_t)(PCR_REG_EC_RESET_ENABLE_4) & 0xFF)<<16u))
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102 //PCR0_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
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103 #define PCR0_EC_JTAG_STAP_BITPOS (0u)
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104 #define PCR0_EC_EFUSE_BITPOS (1u)
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105 #define PCR0_EC_ISPI_BITPOS (2u)
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107 //PCR1_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
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108 #define PCR1_EC_INT_BITPOS (0u)
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109 #define PCR1_EC_PECI_BITPOS (1u)
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110 #define PCR1_EC_TACH0_BITPOS (2u)
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111 #define PCR1_EC_PWM0_BITPOS (4u)
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112 #define PCR1_EC_PMC_BITPOS (5u)
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113 #define PCR1_EC_DMA_BITPOS (6u)
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114 #define PCR1_EC_TFDP_BITPOS (7u)
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115 #define PCR1_EC_CPU_BITPOS (8u)
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116 #define PCR1_EC_WDT_BITPOS (9u)
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117 #define PCR1_EC_SMB0_BITPOS (10u)
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118 #define PCR1_EC_TACH1_BITPOS (11u)
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119 #define PCR1_EC_TACH2_BITPOS (12u)
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120 #define PCR1_EC_PWM1_BITPOS (20u)
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121 #define PCR1_EC_PWM2_BITPOS (21u)
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122 #define PCR1_EC_PWM3_BITPOS (22u)
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123 #define PCR1_EC_PWM4_BITPOS (23u)
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124 #define PCR1_EC_PWM5_BITPOS (24u)
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125 #define PCR1_EC_PWM6_BITPOS (25u)
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126 #define PCR1_EC_PWM7_BITPOS (26u)
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127 #define PCR1_EC_PWM8_BITPOS (27u)
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128 #define PCR1_EC_REG_BITPOS (29u)
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129 #define PCR1_EC_BTIMER0_BITPOS (30u)
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130 #define PCR1_EC_BTIMER1_BITPOS (31u)
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132 //PCR2_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
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133 #define PCR2_EC_LPC_BITPOS (0u)
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134 #define PCR2_EC_UART0_BITPOS (1u)
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135 #define PCR2_EC_UART1_BITPOS (2u)
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136 #define PCR2_EC_GLBL_CFG_BITPOS (12u)
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137 #define PCR2_EC_ACPI_EC0_BITPOS (13u)
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138 #define PCR2_EC_ACPI_EC1_BITPOS (14u)
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139 #define PCR2_EC_ACPI_PM1_BITPOS (15u)
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140 #define PCR2_EC_8042EM_BITPOS (16u)
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141 #define PCR2_EC_MBOX_BITPOS (17u)
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142 #define PCR2_EC_RTC_BITPOS (18u)
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143 #define PCR2_EC_ESPI_BITPOS (19u)
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144 #define PCR2_EC_ACPI_EC_2_BITPOS (21u)
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145 #define PCR2_EC_ACPI_EC_3_BITPOS (22u)
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146 #define PCR2_EC_ACPI_EC_BITPOS (23u)
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147 #define PCR2_EC_PORT80_0_BITPOS (25u)
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148 #define PCR2_EC_PORT80_1_BITPOS (26u)
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150 //PCR3_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
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151 #define PCR3_EC_ADC_BITPOS (3u)
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152 #define PCR3_EC_PS2_0_BITPOS (5u)
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153 #define PCR3_EC_PS2_1_BITPOS (6u)
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154 #define PCR3_EC_PS2_2_BITPOS (7u)
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155 #define PCR3_EC_SPI0_BITPOS (9u)
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156 #define PCR3_EC_HTIMER_BITPOS (10u)
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157 #define PCR3_EC_KEYSCAN_BITPOS (11u)
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158 #define PCR3_EC_RPM_PWM_BITPOS (12u)
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159 #define PCR3_EC_SMB1_BITPOS (13u)
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160 #define PCR3_EC_SMB2_BITPOS (14u)
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161 #define PCR3_EC_SMB3_BITPOS (15u)
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162 #define PCR3_EC_LED0_BITPOS (16u)
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163 #define PCR3_EC_LED1_BITPOS (17u)
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164 #define PCR3_EC_LED2_BITPOS (18u)
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165 #define PCR3_EC_BCM_BITPOS (19u)
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166 #define PCR3_EC_SPI1_BITPOS (20u)
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167 #define PCR3_EC_BTIMER2_BITPOS (21u)
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168 #define PCR3_EC_BTIMER3_BITPOS (22u)
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169 #define PCR3_EC_BTIMER4_BITPOS (23u)
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170 #define PCR3_EC_BTIMER5_BITPOS (24u)
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171 #define PCR3_EC_LED3_BITPOS (25u)
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172 #define PCR3_EC_PKE_BITPOS (26u)
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173 #define PCR3_EC_RNG_BITPOS (27u)
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174 #define PCR3_EC_AES_BITPOS (28u)
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175 #define PCR3_EC_HTIMER_1_BITPOS (29u)
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176 #define PCR3_EC_C_C_TIMER_BITPOS (30u)
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177 #define PCR3_EC_PWM9_BITPOS (31u)
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180 //PCR4_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
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181 #define PCR4_EC_PWM10_BITPOS (0u)
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182 #define PCR4_EC_PWM11_BITPOS (1u)
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183 #define PCR4_EC_CTIMER0_BITPOS (2u)
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184 #define PCR4_EC_CTIMER1_BITPOS (3u)
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185 #define PCR4_EC_CTIMER2_BITPOS (4u)
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186 #define PCR4_EC_CTIMER3_BITPOS (5u)
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187 #define PCR4_EC_RTOS_TIMER_BITPOS (6u)
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188 #define PCR4_EC_RPM2_PWM_BITPOS (7u)
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189 #define PCR4_EC_QMSPI_BITPOS (8u)
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190 #define PCR4_EC_BCM_1_BITPOS (9u)
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191 #define PCR4_EC_RC_ID0_BITPOS (10u)
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192 #define PCR4_EC_RC_ID1_BITPOS (11u)
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193 #define PCR4_EC_RC_ID2_BITPOS (12u)
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194 #define PCR4_EC_PROCHOT_BITPOS (13u)
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195 #define PCR4_EC_EEPROM_BITPOS (14u)
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196 #define PCR4_EC_CUST_LOG_BITPOS (15u)
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200 * n = b[7:0] = PCR Reg Bit Position
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201 * m = b[31:8] = PCRx Regs IDs
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203 //#define PCRx_REGS_BIT(m,n) ((((uint32_t)(m)&0xFFFFFFul)<<8u) + ((uint32_t)(n)&0xFFul))
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205 //PCRx_REGS_BIT positions
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206 #define PCRx_REGS_POS_SLEEP_ENABLE (8u)
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207 #define PCRx_REGS_POS_CLK_REQD_STS (16u)
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208 #define PCRx_REGS_POS_RESET_ENABLE (24u)
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211 /******************************************************************************/
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212 /** PCR Block IDS.
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213 * These IDs are used to directly refer to a block
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214 *******************************************************************************/
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216 PCR_JTAG = (((uint32_t)(PCR0_REGS_EC) << 8) + (uint32_t)(PCR0_EC_JTAG_STAP_BITPOS & 0xFFu)),
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217 PCR_EFUSE = (((uint32_t)(PCR0_REGS_EC) << 8) + (uint32_t)(PCR0_EC_EFUSE_BITPOS & 0xFFu)),
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218 PCR_ISPI = (((uint32_t)(PCR0_REGS_EC) << 8) + (uint32_t)(PCR0_EC_ISPI_BITPOS & 0xFFu)),
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220 PCR_INT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_INT_BITPOS & 0xFFu)),
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221 PCR_PECI = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PECI_BITPOS & 0xFFu)),
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222 PCR_TACH0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH0_BITPOS & 0xFFu)),
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223 PCR_PWM0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM0_BITPOS & 0xFFu)),
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224 PCR_PMC = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PMC_BITPOS & 0xFFu)),
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225 PCR_DMA = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_DMA_BITPOS & 0xFFu)),
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226 PCR_TFDP = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TFDP_BITPOS & 0xFFu)),
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227 PCR_CPU = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_CPU_BITPOS & 0xFFu)),
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228 PCR_WDT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_WDT_BITPOS & 0xFFu)),
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229 PCR_SMB0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_SMB0_BITPOS & 0xFFu)),
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230 PCR_TACH1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH1_BITPOS & 0xFFu)),
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231 PCR_TACH2 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH2_BITPOS & 0xFFu)),
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232 PCR_PWM1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM1_BITPOS & 0xFFu)),
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233 PCR_PWM2 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM2_BITPOS & 0xFFu)),
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234 PCR_PWM3 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM3_BITPOS & 0xFFu)),
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235 PCR_PWM4 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM4_BITPOS & 0xFFu)),
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236 PCR_PWM5 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM5_BITPOS & 0xFFu)),
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237 PCR_PWM6 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM6_BITPOS & 0xFFu)),
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238 PCR_PWM7 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM7_BITPOS & 0xFFu)),
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239 PCR_PWM8 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM8_BITPOS & 0xFFu)),
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240 PCR_REG = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_REG_BITPOS & 0xFFu)),
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241 PCR_BTIMER0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER0_BITPOS & 0xFFu)),
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242 PCR_BTIMER1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER1_BITPOS & 0xFFu)),
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244 PCR_LPC = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_LPC_BITPOS & 0xFFu)),
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245 PCR_UART0 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_UART0_BITPOS & 0xFFu)),
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246 PCR_UART1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_UART1_BITPOS & 0xFFu)),
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247 PCR_GLBL_CFG = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_GLBL_CFG_BITPOS & 0xFFu)),
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248 PCR_ACPI_EC0 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC0_BITPOS & 0xFFu)),
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249 PCR_ACPI_EC1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC1_BITPOS & 0xFFu)),
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250 PCR_ACPI_PM1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_PM1_BITPOS & 0xFFu)),
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251 PCR_8042EM = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_8042EM_BITPOS & 0xFFu)),
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252 PCR_MBOX = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_MBOX_BITPOS & 0xFFu)),
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253 PCR_RTC = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_RTC_BITPOS & 0xFFu)),
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254 PCR_ESPI = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ESPI_BITPOS & 0xFFu)),
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255 PCR_ACPI_EC2 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC_2_BITPOS & 0xFFu)),
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256 PCR_ACPI_EC3 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC_3_BITPOS & 0xFFu)),
\r
257 PCR_ACPI_EC = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC_BITPOS & 0xFFu)),
\r
258 PCR_PORT80_0 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_PORT80_0_BITPOS & 0xFFu)),
\r
259 PCR_PORT80_1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_PORT80_1_BITPOS & 0xFFu)),
\r
261 PCR_ADC = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_ADC_BITPOS & 0xFFu)),
\r
262 PCR_PS2_0 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PS2_0_BITPOS & 0xFFu)),
\r
263 PCR_PS2_1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PS2_1_BITPOS & 0xFFu)),
\r
264 PCR_PS2_2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PS2_2_BITPOS & 0xFFu)),
\r
265 PCR_SPI0 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SPI0_BITPOS & 0xFFu)),
\r
266 PCR_HTIMER = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_HTIMER_BITPOS & 0xFFu)),
\r
267 PCR_KEYSCAN = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_KEYSCAN_BITPOS & 0xFFu)),
\r
268 PCR_RPM_PWM = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_RPM_PWM_BITPOS & 0xFFu)),
\r
269 PCR_SMB1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SMB1_BITPOS & 0xFFu)),
\r
270 PCR_SMB2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SMB2_BITPOS & 0xFFu)),
\r
271 PCR_SMB3 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SMB3_BITPOS & 0xFFu)),
\r
272 PCR_LED0 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED0_BITPOS & 0xFFu)),
\r
273 PCR_LED1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED1_BITPOS & 0xFFu)),
\r
274 PCR_LED2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED2_BITPOS & 0xFFu)),
\r
275 PCR_BCM = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BCM_BITPOS & 0xFFu)),
\r
276 PCR_SPI1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SPI1_BITPOS & 0xFFu)),
\r
277 PCR_BTIMER2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER2_BITPOS & 0xFFu)),
\r
278 PCR_BTIMER3 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER3_BITPOS & 0xFFu)),
\r
279 PCR_BTIMER4 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER4_BITPOS & 0xFFu)),
\r
280 PCR_BTIMER5 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER5_BITPOS & 0xFFu)),
\r
281 PCR_LED3 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED3_BITPOS & 0xFFu)),
\r
282 PCR_PKE = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PKE_BITPOS & 0xFFu)),
\r
283 PCR_RNG = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_RNG_BITPOS & 0xFFu)),
\r
284 PCR_AES = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_AES_BITPOS & 0xFFu)),
\r
285 PCR_HTIMER_1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_HTIMER_1_BITPOS & 0xFFu)),
\r
286 PCR_C_C_TIMER = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_C_C_TIMER_BITPOS & 0xFFu)),
\r
287 PCR_PWM9 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PWM9_BITPOS & 0xFFu)),
\r
289 PCR_PWM10 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_PWM10_BITPOS & 0xFFu)),
\r
290 PCR_PWM11 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_PWM11_BITPOS & 0xFFu)),
\r
291 PCR_CTIMER0 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER0_BITPOS & 0xFFu)),
\r
292 PCR_CTIMER1 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER1_BITPOS & 0xFFu)),
\r
293 PCR_CTIMER2 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER2_BITPOS & 0xFFu)),
\r
294 PCR_CTIMER3 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER3_BITPOS & 0xFFu)),
\r
295 PCR_RTOS_TIMER = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RTOS_TIMER_BITPOS & 0xFFu)),
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296 PCR_RPM2_PWM = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RPM2_PWM_BITPOS & 0xFFu)),
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297 PCR_QMSPI = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_QMSPI_BITPOS & 0xFFu)),
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298 PCR_BCM1 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_BCM_1_BITPOS & 0xFFu)),
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299 PCR_RCID0 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RC_ID0_BITPOS & 0xFFu)),
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300 PCR_RCID1 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RC_ID1_BITPOS & 0xFFu)),
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301 PCR_RCID2 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RC_ID2_BITPOS & 0xFFu)),
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302 PCR_PROCHOT = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_PROCHOT_BITPOS & 0xFFu)),
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303 PCR_EEPROM = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_EEPROM_BITPOS & 0xFFu)),
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304 PCR_CUST_LOG = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CUST_LOG_BITPOS & 0xFFu)),
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308 /******************************************************************************/
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309 /** PCR Processor ClK Divide Values
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310 *******************************************************************************/
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311 enum PROCESSOR_CLK_DIVIDE_VALUE
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313 PCR_CPU_CLK_DIVIDE_1 = 1,
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314 PCR_CPU_CLK_DIVIDE_2 = 2,
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315 PCR_CPU_CLK_DIVIDE_3 = 3,
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316 PCR_CPU_CLK_DIVIDE_4 = 4,
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317 PCR_CPU_CLK_DIVIDE_16 = 16,
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318 PCR_CPU_CLK_DIVIDE_48 = 48
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321 /******************************************************************************/
\r
322 /** System Sleep Modes
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323 *******************************************************************************/
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324 enum SYSTEM_SLEEP_MODES
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326 SYSTEM_LIGHT_SLEEP = 0,
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327 SYSTEM_HEAVY_SLEEP = 1,
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328 SYSTEM_SLEEP_ALL = 4
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331 /* Bitmask for Power Reset Status Register */
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332 #define PCR_PWR_RESET_STS_VCC_PWRGD_RESET_STS_BITMASK (1UL<<2)
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333 #define PCR_PWR_RESET_STS_HOST_RESET_STS_BITMASK (1UL<<3)
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334 #define PCR_PWR_RESET_STS_VBAT_RESET_STS_BITMASK (1UL<<5)
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335 #define PCR_PWR_RESET_STS_VTR_RESET_STS_BITMASK (1UL<<6)
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336 #define PCR_PWR_RESET_STS_JTAG_RESET_STS_BITMASK (1UL<<7)
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337 #define PCR_PWR_RESET_STS_32K_ACTIVE_STS_BITMASK (1UL<<10)
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338 #define PCR_PWR_RESET_STS_PCICLK_ACTIVE_STS_BITMASK (1UL<<11)
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339 #define PCR_PWR_RESET_STS_ESPICLK_ACTIVE_STS_BITMASK (1UL<<12)
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341 /* Bitmask for Processor Clock Control Register */
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342 #define PCR_OSCILLATOR_LOCK_STATUS_BITMASK (1UL<<8)
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344 /* Bitmask for Power Reset Control Register */
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345 #define PCR_PWR_RESET_CTRL_PWR_INV_BITMASK (1UL<<0)
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346 #define PCR_PWR_RESET_CTRL_HOST_RST_SELECT_BITMASK (1UL<<8)
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348 /* Bitmask for OScillator ID register */
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349 #define PCR_OSCILLATOR_ID_FOUNDARY_BITMASK (3UL<<5)
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350 #define PCR_OSCILLATOR_ID_REVISION_BITMASK (0xFUL)
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352 #define PCR_OSCILLATOR_ID_FOUNDARY_CHART_TSMC (0UL)
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353 #define PCR_OSCILLATOR_ID_FOUNDARY_TSMC (0x10u)
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354 #define PCR_OSCILLATOR_ID_FOUNDARY_CHART (0x20u)
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355 #define PCR_OSCILLATOR_ID_FOUNDARY_GRACE (0x30u)
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357 /* Bitmask for PKE Clock register */
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358 #define PCR_PKE_CLOCK_REG_PKE_CLK_BITMASK (1UL<<1)
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359 #define PCR_PKE_CLOCK_REG_AUTO_SWITCH_BITMASK (1UL<<0)
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361 #define PCR_PKE_CLOCK_REG_PKE_CLK_48MHZ (1UL<<1)
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362 #define PCR_PKE_CLOCK_REG_PKE_CLK_96MHZ (0UL<<0)
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363 #define PCR_PKE_CLOCK_REG_AUTO_SWITCH_EN (1UL<<0)
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364 #define PCR_PKE_CLOCK_REG_AUTO_SWITCH_DIS (0UL<<0)
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366 /* ---------------------------------------------------------------------- */
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367 /* API - Functions to program Sleep Enable, CLK Reqd Status, *
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368 * Reset Enable for a block *
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369 * ---------------------------------------------------------------------- */
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370 /** Sets or Clears block specific bit in PCR Sleep Enable Register
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371 * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
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372 * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register
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374 void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);
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376 /** Get Clock Required Status for the block
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377 * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
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378 * @return uint8_t - 1 if Clock Required Status set, else 0
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380 uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id);
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382 /** Sets or Clears Reset Enable register bit for the block
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383 * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
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384 * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register
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386 void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);
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388 /* ---------------------------------------------------------------------- */
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389 /* API - Functions for entering low power modes */
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390 /* ---------------------------------------------------------------------- */
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391 /** Instructs all blocks to sleep by setting the Sleep Enable bits */
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392 void pcr_all_blocks_sleep(void);
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394 /** Clears the Sleep Enable bits for all blocks */
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395 void pcr_all_blocks_wake(void);
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397 /** Programs required sleep mode in System Sleep Control Register
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398 * @param sleep_mode - see enum SYSTEM_SLEEP_MODES
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400 void pcr_system_sleep(uint8_t sleep_mode);
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402 /** Reads the value of Power Reset status register
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404 * @return Power Status Reg value
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406 uint16_t pcr_power_reset_status_read(void);
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408 /** Reads the value of Power Reset control register
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410 * @return Power reset control Reg value
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412 uint16_t pcr_power_reset_ctrl_read(void);
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414 /** Sets the value of PWR_INV bit to 1 or 0
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415 * @param set_clr: 1 or 0
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418 void pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr);
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420 /** Sets the value of HOST_RESET bit to 1 or 0
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421 * @param set_clr: 1 or 0
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424 void pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr);
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426 /** Sets the SOFT SYS RESET bit to 1
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430 void pcr_system_reset_set(void);
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432 /** Writes to the PKE Clock register
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433 * @param clock value
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436 void pcr_pke_clock_write(uint8_t pke_clk_val);
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438 /** Reads the PKE clock register
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440 * @return clock value
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442 uint8_t pcr_pke_clock_read(void);
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444 /** Writes to the OSC cal register
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445 * @param calibration value: 1 or 0
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448 void pcr_osc_cal_write(uint8_t pke_clk_val);
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450 /** Reads the osc cal register
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452 * @return cal value
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454 uint8_t pcr_osc_cal_read(void);
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457 /* ---------------------------------------------------------------------- */
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458 /* Peripheral Function - Functions to program and read 32-bit values *
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459 * from PCR Registers *
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460 * ---------------------------------------------------------------------- */
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461 /** Write 32-bit value in the PCR Register
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462 * @param pcr_reg_id - pcr register id
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463 * @param value - 32-bit value
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465 void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value);
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467 /** Reads 32-bit value from the PCR Register
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468 * @param pcr_reg_id - pcr register id
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469 * @return value - 32-bit value
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471 uint32_t p_pcr_reg_read(uint8_t pcr_reg_id);
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473 /* ---------------------------------------------------------------------- */
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474 /* Peripheral Function - Functions to set, clr and get bits in *
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476 * ---------------------------------------------------------------------- */
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477 /** Sets bits in a PCR Register
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478 * @param pcr_reg_id - pcr register id
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479 * @param bit_mask - Bit mask of bits to set
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481 void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask);
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483 /** Clears bits in a PCR Register
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484 * @param pcr_reg_id - pcr register id
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485 * @param bit_mask - Bit mask of bits to clear
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487 void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask);
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489 /** Read bits in a PCR Register
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490 * @param pcr_reg_id - pcr register id
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491 * @param bit_mask - Bit mask of bits to read
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492 * @return value - 32-bit value
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494 uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask);
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496 /** Sets or Clears bits in a PCR Register - Helper Function
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497 * @param pcr_reg_id - pcr register id
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498 * @param bit_mask - Bit mask of bits to set or clear
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499 * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register
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501 void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag);
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503 //Functions to operate on System Sleep Control Register
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505 /* ---------------------------------------------------------------------- */
\r
506 /* Peripheral Function - Functions to operate on System Sleep Control *
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508 * ---------------------------------------------------------------------- */
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509 /** Writes required sleep mode in System Sleep Control Register
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510 * @param sleep_value - System Sleep control value - [D2, D1, D0]
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512 void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value);
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514 /** Reads the System Sleep Control PCR Register
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515 * @return value - byte 0 of the system sleep control PCR register
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517 uint8_t p_pcr_system_sleep_ctrl_read(void);
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519 /* ---------------------------------------------------------------------- */
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520 /* Peripheral Function - Function to program to CLK Divide Value *
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521 * ---------------------------------------------------------------------- */
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522 /** Writes the clock divide value in the Processor Clock Control Register
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523 * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE
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525 void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value);
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527 /* ---------------------------------------------------------------------- */
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528 /* Peripheral Function - Function to program the Slow Clock Control *
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530 * ---------------------------------------------------------------------- */
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531 /** Write the slow clock divide value in the Slow Clock Control Register
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532 * @param slow_clk_divide_value - slow clk divide value
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534 void p_pcr_slow_clk_ctrl_write(uint16_t slow_clk_divide_value);
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536 /* ---------------------------------------------------------------------- */
\r
537 /* Peripheral Function - Function to read the Oscillator Lock Status */
\r
538 /* ---------------------------------------------------------------------- */
\r
539 /** Reads the Oscillator Lock status bit in the Oscillator ID Register
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540 * @return 1 if Oscillator Lock Status bit is set, else 0
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542 uint8_t p_pcr_oscillator_lock_sts_get(void);
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544 /** Reads the Oscillator ID Register
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545 * @return oscillator ID value
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547 uint16_t p_pcr_oscillator_id_reg_read(void);
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549 /* ---------------------------------------------------------------------- */
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550 /* Peripheral Function - Functions to read various power status in *
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551 * Power Reset register *
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552 * ---------------------------------------------------------------------- */
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553 /** Reads the VCC Reset Status bit
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554 * in the Power Reset Status Register
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555 * @return 1 if VCC Reset Status bit is set, else 0
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557 uint8_t p_pcr_pwr_reset_vcc_reset_sts_get(void);
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559 /** Reads the Host Reset Status bit
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560 * in the Power Reset Status Register
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561 * @return 1 if Host Reset Status bit is set, else 0
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563 uint8_t p_pcr_pwr_reset_host_reset_sts_get(void);
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565 /** Reads the VBAT Reset Status bit
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566 * in the Power Reset Status Register
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567 * @return 1 if VBAT Reset Status bit is set, else 0
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569 uint8_t p_pcr_pwr_reset_vbat_reset_sts_get(void);
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571 /** Clears the VBAT Reset Status bit
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572 * in the Power Reset Status Register
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574 void p_pcr_pwr_reset_vbat_reset_sts_clr(void);
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576 /** Reads the VTR Reset Status bit
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577 * in the Power Reset Status Register
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578 * @return 1 if VCC1 Reset Status bit is set, else 0
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580 uint8_t p_pcr_pwr_reset_vtr_reset_sts_get(void);
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582 /** Clears the VTR Reset Status bit
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583 * in the Power Reset Status Register
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585 void p_pcr_chip_subsystem_vtr_reset_sts_clr(void);
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587 /** Reads the 32K_ACTIVE status bit
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588 * in the Chip Subsystem Power Reset Status Register
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589 * @return 1 if 32_ACTIVE bit is set, else 0
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591 uint8_t p_pcr_pwr_reset_32K_active_sts_get(void);
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593 /** Reads the PCICLK_ACTIVE status bit
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594 * in the Power Reset Status Register
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595 * @return 1 if CICLK_ACTIVE bit is set, else 0
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597 uint8_t p_pcr_pwr_reset_pciclk_active_sts_get(void);
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599 /** Reads the ESPICLK_ACTIVE status bit
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600 * in the Power Reset Status Register
\r
601 * @return 1 if ESPICLK_ACTIVE bit is set, else 0
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603 uint8_t p_pcr_pwr_reset_espiclk_active_sts_get(void);
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605 /** Reads the Power status reg
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606 * @return Power Status Reg value
\r
608 uint16_t p_pcr_pwr_reset_sts_get(void);
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610 /* ---------------------------------------------------------------------- */
\r
611 /* Peripheral Function - Functions for Power Reset Control Register */
\r
612 /* ---------------------------------------------------------------------- */
\r
614 /** Reads the Power Reset Control Register
\r
615 * @return Power Reset Control Register value
\r
617 uint16_t p_pcr_pwr_reset_ctrl_read(void);
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619 /** Set the PWR_INV bit in the Power Reset Control Register
\r
620 * @param set_clr value 1 or 0
\r
623 void p_pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr);
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625 /** Set the HOST RESET SELECT bit in the Power Reset Control Register
\r
626 * @param set_clr value 1 or 0
\r
629 void p_pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr);
\r
631 /* ---------------------------------------------------------------------- */
\r
632 /* Peripheral Function - Functions for System Reset Register */
\r
633 /* ---------------------------------------------------------------------- */
\r
634 /** Set the SOFT_SYS_RESET bit in the System Reset Register
\r
638 void p_pcr_system_reset_set(void);
\r
641 /** Set the value in PKE CLOCK Register
\r
642 * @param PKE Clock value
\r
645 void p_pcr_pke_clock_write(uint8_t pke_clk_val);
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647 /** Read the value in PKE CLOCK Register
\r
649 * @return PKE Clock value
\r
651 uint8_t p_pcr_pke_clock_read(void);
\r
653 /** Set the value in Oscillator calibration Register
\r
654 * @param Oscillator calibration value
\r
657 void p_pcr_osc_cal_write(uint8_t osc_cal_val);
\r
659 /** Read the value in Osc cal Register
\r
661 * @return Osc cal value
\r
663 uint8_t p_pcr_osc_cal_read(void);
\r
665 #endif // #ifndef _PCR_H
\r