2 * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
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3 * Copyright 2016-2018 NXP
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4 * All rights reserved.
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6 * SPDX-License-Identifier: BSD-3-Clause
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9 #ifndef _FSL_COMMON_H_
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10 #define _FSL_COMMON_H_
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13 #include <stdbool.h>
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18 #if defined(__ICCARM__)
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22 #include "fsl_device_registers.h"
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25 * @addtogroup ksdk_common
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29 /*******************************************************************************
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31 ******************************************************************************/
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33 /*! @brief Construct a status code value from a group and code number. */
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34 #define MAKE_STATUS(group, code) ((((group)*100) + (code)))
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36 /*! @brief Construct the version number for drivers. */
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37 #define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
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39 /*! @name Driver version */
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41 /*! @brief common driver version 2.0.1. */
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42 #define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
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45 /* Debug console type definition. */
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46 #define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
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47 #define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */
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48 #define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */
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49 #define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */
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50 #define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */
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51 #define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */
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52 #define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */
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53 #define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */
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54 #define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */
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55 #define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */
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57 /*! @brief Status group numbers. */
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60 kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
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61 kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
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62 kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
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63 kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
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64 kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
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65 kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
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66 kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
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67 kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
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68 kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
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69 kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
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70 kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
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71 kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
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72 kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
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73 kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
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74 kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
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75 kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
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76 kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
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77 kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
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78 kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
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79 kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
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80 kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
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81 kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
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82 kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
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83 kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
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84 kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
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85 kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
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86 kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
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87 kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
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88 kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */
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89 kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
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90 kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
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91 kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
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92 kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
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93 kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
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94 kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
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95 kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
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96 kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
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97 kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
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98 kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
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99 kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
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100 kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
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101 kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
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102 kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
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103 kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
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104 kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
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105 kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
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106 kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
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107 kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
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108 kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
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109 kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
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110 kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
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111 kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
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112 kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
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113 kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
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114 kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/
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115 kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/
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116 kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
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117 kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
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118 kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
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119 kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */
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120 kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
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121 kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
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122 kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
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123 kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */
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124 kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */
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125 kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */
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126 kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */
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127 kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
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128 kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
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129 kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
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130 kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
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131 kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */
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133 kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */
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134 kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */
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135 kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */
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136 kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */
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137 kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */
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138 kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */
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139 kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */
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140 kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */
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141 kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */
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142 kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */
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143 kStatusGroup_LED = 137, /*!< Group number for LED status codes. */
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144 kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */
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145 kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */
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146 kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */
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147 kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */
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148 kStatusGroup_LIST = 142, /*!< Group number for List status codes. */
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149 kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */
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150 kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */
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151 kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */
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154 /*! @brief Generic status return codes. */
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155 enum _generic_status
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157 kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
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158 kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
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159 kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
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160 kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
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161 kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
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162 kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
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163 kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
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166 /*! @brief Type used for all status and error return values. */
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167 typedef int32_t status_t;
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170 * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
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171 * defined in previous of this file.
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173 #include "fsl_clock.h"
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176 * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
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178 #if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
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179 (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
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180 #include "fsl_reset.h"
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184 * Macro guard for whether to use default weak IRQ implementation in drivers
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186 #ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
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187 #define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
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190 /*! @name Min/max macros */
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193 #define MIN(a, b) ((a) < (b) ? (a) : (b))
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197 #define MAX(a, b) ((a) > (b) ? (a) : (b))
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201 /*! @brief Computes the number of elements in an array. */
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202 #if !defined(ARRAY_SIZE)
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203 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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206 /*! @name UINT16_MAX/UINT32_MAX value */
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208 #if !defined(UINT16_MAX)
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209 #define UINT16_MAX ((uint16_t)-1)
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212 #if !defined(UINT32_MAX)
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213 #define UINT32_MAX ((uint32_t)-1)
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217 /*! @name Timer utilities */
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219 /*! Macro to convert a microsecond period to raw count value */
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220 #define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
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221 /*! Macro to convert a raw count value to microsecond */
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222 #define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
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224 /*! Macro to convert a millisecond period to raw count value */
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225 #define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
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226 /*! Macro to convert a raw count value to millisecond */
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227 #define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
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230 /*! @name Alignment variable definition macros */
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232 #if (defined(__ICCARM__))
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234 * Workaround to disable MISRA C message suppress warnings for IAR compiler.
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235 * http://supp.iar.com/Support/?note=24725
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237 _Pragma("diag_suppress=Pm120")
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238 #define SDK_PRAGMA(x) _Pragma(#x)
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239 _Pragma("diag_error=Pm120")
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240 /*! Macro to define a variable with alignbytes alignment */
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241 #define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
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242 /*! Macro to define a variable with L1 d-cache line size alignment */
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243 #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
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244 #define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
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246 /*! Macro to define a variable with L2 cache line size alignment */
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247 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
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248 #define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
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250 #elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
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251 /*! Macro to define a variable with alignbytes alignment */
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252 #define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
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253 /*! Macro to define a variable with L1 d-cache line size alignment */
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254 #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
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255 #define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var
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257 /*! Macro to define a variable with L2 cache line size alignment */
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258 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
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259 #define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var
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261 #elif defined(__GNUC__)
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262 /*! Macro to define a variable with alignbytes alignment */
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263 #define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
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264 /*! Macro to define a variable with L1 d-cache line size alignment */
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265 #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
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266 #define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
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268 /*! Macro to define a variable with L2 cache line size alignment */
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269 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
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270 #define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
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273 #error Toolchain not supported
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274 #define SDK_ALIGN(var, alignbytes) var
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275 #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
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276 #define SDK_L1DCACHE_ALIGN(var) var
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278 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
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279 #define SDK_L2CACHE_ALIGN(var) var
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283 /*! Macro to change a value to a given size aligned value */
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284 #define SDK_SIZEALIGN(var, alignbytes) \
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285 ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
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288 /*! @name Non-cacheable region definition macros */
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289 /* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
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290 * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
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291 * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
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292 * will be initialized to zero in system startup.
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295 #if (defined(__ICCARM__))
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296 #if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
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297 #define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
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298 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
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299 #define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
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300 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
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302 #define AT_NONCACHEABLE_SECTION(var) var
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303 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
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304 #define AT_NONCACHEABLE_SECTION_INIT(var) var
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305 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
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307 #elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
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308 #if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
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309 #define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
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310 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
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311 __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
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312 #define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
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313 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
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314 __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
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316 #define AT_NONCACHEABLE_SECTION(var) var
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317 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
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318 #define AT_NONCACHEABLE_SECTION_INIT(var) var
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319 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var
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321 #elif(defined(__GNUC__))
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322 /* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
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323 * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
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325 #if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
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326 #define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
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327 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
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328 __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
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329 #define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
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330 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
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331 __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
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333 #define AT_NONCACHEABLE_SECTION(var) var
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334 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
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335 #define AT_NONCACHEABLE_SECTION_INIT(var) var
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336 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))
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339 #error Toolchain not supported.
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340 #define AT_NONCACHEABLE_SECTION(var) var
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341 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
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342 #define AT_NONCACHEABLE_SECTION_INIT(var) var
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343 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var
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347 /*! @name Time sensitive region */
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349 #if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
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350 #if (defined(__ICCARM__))
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351 #define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
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352 #define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
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353 #elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
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354 #define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
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355 #define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
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356 #elif(defined(__GNUC__))
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357 #define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
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358 #define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
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360 #error Toolchain not supported.
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361 #endif /* defined(__ICCARM__) */
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363 #if (defined(__ICCARM__))
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364 #define AT_QUICKACCESS_SECTION_CODE(func) func
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365 #define AT_QUICKACCESS_SECTION_DATA(func) func
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366 #elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
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367 #define AT_QUICKACCESS_SECTION_CODE(func) func
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368 #define AT_QUICKACCESS_SECTION_DATA(func) func
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369 #elif(defined(__GNUC__))
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370 #define AT_QUICKACCESS_SECTION_CODE(func) func
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371 #define AT_QUICKACCESS_SECTION_DATA(func) func
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373 #error Toolchain not supported.
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375 #endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
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378 /*! @name Ram Function */
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379 #if (defined(__ICCARM__))
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380 #define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
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381 #elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
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382 #define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
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383 #elif(defined(__GNUC__))
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384 #define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
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386 #error Toolchain not supported.
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387 #endif /* defined(__ICCARM__) */
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389 /*******************************************************************************
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391 ******************************************************************************/
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393 #if defined(__cplusplus)
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399 * @brief Enable specific interrupt.
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401 * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
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402 * levels. For example, there are NVIC and intmux. Here the interrupts connected
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403 * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
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404 * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
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405 * to NVIC first then routed to core.
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407 * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
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408 * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
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410 * @param interrupt The IRQ number.
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411 * @retval kStatus_Success Interrupt enabled successfully
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412 * @retval kStatus_Fail Failed to enable the interrupt
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414 static inline status_t EnableIRQ(IRQn_Type interrupt)
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416 if (NotAvail_IRQn == interrupt)
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418 return kStatus_Fail;
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421 #if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
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422 if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
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424 return kStatus_Fail;
\r
428 #if defined(__GIC_PRIO_BITS)
\r
429 GIC_EnableIRQ(interrupt);
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431 NVIC_EnableIRQ(interrupt);
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433 return kStatus_Success;
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437 * @brief Disable specific interrupt.
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439 * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
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440 * levels. For example, there are NVIC and intmux. Here the interrupts connected
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441 * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
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442 * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
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443 * to NVIC first then routed to core.
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445 * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
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446 * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
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448 * @param interrupt The IRQ number.
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449 * @retval kStatus_Success Interrupt disabled successfully
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450 * @retval kStatus_Fail Failed to disable the interrupt
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452 static inline status_t DisableIRQ(IRQn_Type interrupt)
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454 if (NotAvail_IRQn == interrupt)
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456 return kStatus_Fail;
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459 #if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
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460 if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
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462 return kStatus_Fail;
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466 #if defined(__GIC_PRIO_BITS)
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467 GIC_DisableIRQ(interrupt);
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469 NVIC_DisableIRQ(interrupt);
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471 return kStatus_Success;
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475 * @brief Disable the global IRQ
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477 * Disable the global interrupt and return the current primask register. User is required to provided the primask
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478 * register for the EnableGlobalIRQ().
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480 * @return Current primask value.
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482 static inline uint32_t DisableGlobalIRQ(void)
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484 #if defined(CPSR_I_Msk)
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485 uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
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491 uint32_t regPrimask = __get_PRIMASK();
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500 * @brief Enable the global IRQ
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502 * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
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503 * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
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504 * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
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506 * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
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507 * DisableGlobalIRQ().
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509 static inline void EnableGlobalIRQ(uint32_t primask)
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511 #if defined(CPSR_I_Msk)
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512 __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
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514 __set_PRIMASK(primask);
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518 #if defined(ENABLE_RAM_VECTOR_TABLE)
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520 * @brief install IRQ handler
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522 * @param irq IRQ number
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523 * @param irqHandler IRQ handler address
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524 * @return The old IRQ handler address
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526 uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
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527 #endif /* ENABLE_RAM_VECTOR_TABLE. */
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529 #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
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531 * @brief Enable specific interrupt for wake-up from deep-sleep mode.
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533 * Enable the interrupt for wake-up from deep sleep mode.
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534 * Some interrupts are typically used in sleep mode only and will not occur during
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535 * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
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536 * those clocks (significantly increasing power consumption in the reduced power mode),
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537 * making these wake-ups possible.
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539 * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
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541 * @param interrupt The IRQ number.
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543 void EnableDeepSleepIRQ(IRQn_Type interrupt);
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546 * @brief Disable specific interrupt for wake-up from deep-sleep mode.
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548 * Disable the interrupt for wake-up from deep sleep mode.
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549 * Some interrupts are typically used in sleep mode only and will not occur during
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550 * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
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551 * those clocks (significantly increasing power consumption in the reduced power mode),
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552 * making these wake-ups possible.
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554 * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
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556 * @param interrupt The IRQ number.
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558 void DisableDeepSleepIRQ(IRQn_Type interrupt);
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559 #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
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562 * @brief Allocate memory with given alignment and aligned size.
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564 * This is provided to support the dynamically allocated memory
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565 * used in cache-able region.
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566 * @param size The length required to malloc.
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567 * @param alignbytes The alignment size.
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568 * @retval The allocated memory.
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570 void *SDK_Malloc(size_t size, size_t alignbytes);
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573 * @brief Free memory.
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575 * @param ptr The memory to be release.
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577 void SDK_Free(void *ptr);
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579 #if defined(__cplusplus)
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585 #endif /* _FSL_COMMON_H_ */
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