git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_MPU_M33F_Simulator_Keil_GCC/NonSecure/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s

   1 ;/**************************************************************************//**\r
   2 ; * @file     startup_ARMCM33.s\r
   3 ; * @brief    CMSIS Core Device Startup File for\r
   4 ; *           ARMCM33 Device Series\r
   5 ; * @version  V5.00\r
   6 ; * @date     21. October 2016\r
   7 ; ******************************************************************************/\r
   8 ;/*\r
   9 ; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.\r
  10 ; *\r
  11 ; * SPDX-License-Identifier: Apache-2.0\r
  12 ; *\r
  13 ; * Licensed under the Apache License, Version 2.0 (the License); you may\r
  14 ; * not use this file except in compliance with the License.\r
  15 ; * You may obtain a copy of the License at\r
  16 ; *\r
  17 ; * www.apache.org/licenses/LICENSE-2.0\r
  18 ; *\r
  19 ; * Unless required by applicable law or agreed to in writing, software\r
  20 ; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
  21 ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
  22 ; * See the License for the specific language governing permissions and\r
  23 ; * limitations under the License.\r
  24 ; */\r
  25 \r
  26 ;/*\r
  27 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
  28 ;*/\r
  29 \r
  30 \r
  31 ; <h> Stack Configuration\r
  32 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
  33 ; </h>\r
  34 \r
  35 Stack_Size      EQU     0x00000400\r
  36 \r
  37                 AREA    STACK, NOINIT, READWRITE, ALIGN=3\r
  38 Stack_Mem       SPACE   Stack_Size\r
  39 __initial_sp\r
  40 \r
  41 \r
  42 ; <h> Heap Configuration\r
  43 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
  44 ; </h>\r
  45 \r
  46 Heap_Size       EQU     0x00000C00\r
  47 \r
  48                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3\r
  49 __heap_base\r
  50 Heap_Mem        SPACE   Heap_Size\r
  51 __heap_limit\r
  52 \r
  53 \r
  54                 PRESERVE8\r
  55                 THUMB\r
  56 \r
  57 \r
  58 ; Vector Table Mapped to Address 0 at Reset\r
  59 \r
  60                 AREA    RESET, DATA, READONLY\r
  61                 EXPORT  __Vectors\r
  62                 EXPORT  __Vectors_End\r
  63                 EXPORT  __Vectors_Size\r
  64 \r
  65 __Vectors       DCD     __initial_sp              ; Top of Stack\r
  66                 DCD     Reset_Handler             ; Reset Handler\r
  67                 DCD     NMI_Handler               ; NMI Handler\r
  68                 DCD     HardFault_Handler         ; Hard Fault Handler\r
  69                 DCD     MemManage_Handler         ; MPU Fault Handler\r
  70                 DCD     BusFault_Handler          ; Bus Fault Handler\r
  71                 DCD     UsageFault_Handler        ; Usage Fault Handler\r
  72                 DCD     SecureFault_Handler       ; Secure Fault Handler\r
  73                 DCD     0                         ; Reserved\r
  74                 DCD     0                         ; Reserved\r
  75                 DCD     0                         ; Reserved\r
  76                 DCD     SVC_Handler               ; SVCall Handler\r
  77                 DCD     DebugMon_Handler          ; Debug Monitor Handler\r
  78                 DCD     0                         ; Reserved\r
  79                 DCD     PendSV_Handler            ; PendSV Handler\r
  80                 DCD     SysTick_Handler           ; SysTick Handler\r
  81 \r
  82                 ; External Interrupts\r
  83                 DCD     WDT_IRQHandler            ;  0:  Watchdog Timer\r
  84                 DCD     RTC_IRQHandler            ;  1:  Real Time Clock\r
  85                 DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1\r
  86                 DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3\r
  87                 DCD     MCIA_IRQHandler           ;  4:  MCIa\r
  88                 DCD     MCIB_IRQHandler           ;  5:  MCIb\r
  89                 DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA\r
  90                 DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA\r
  91                 DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA\r
  92                 DCD     UART4_IRQHandler          ;  9:  UART4 - not connected\r
  93                 DCD     AACI_IRQHandler           ; 10: AACI / AC97\r
  94                 DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt\r
  95                 DCD     ENET_IRQHandler           ; 12: Ethernet\r
  96                 DCD     USBDC_IRQHandler          ; 13: USB Device\r
  97                 DCD     USBHC_IRQHandler          ; 14: USB Host Controller\r
  98                 DCD     CHLCD_IRQHandler          ; 15: Character LCD\r
  99                 DCD     FLEXRAY_IRQHandler        ; 16: Flexray\r
 100                 DCD     CAN_IRQHandler            ; 17: CAN\r
 101                 DCD     LIN_IRQHandler            ; 18: LIN\r
 102                 DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC\r
 103                 DCD     0                         ; 20: Reserved\r
 104                 DCD     0                         ; 21: Reserved\r
 105                 DCD     0                         ; 22: Reserved\r
 106                 DCD     0                         ; 23: Reserved\r
 107                 DCD     0                         ; 24: Reserved\r
 108                 DCD     0                         ; 25: Reserved\r
 109                 DCD     0                         ; 26: Reserved\r
 110                 DCD     0                         ; 27: Reserved\r
 111                 DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD\r
 112                 DCD     0                         ; 29: Reserved - CPU FPGA\r
 113                 DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA\r
 114                 DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA\r
 115 __Vectors_End\r
 116 \r
 117 __Vectors_Size  EQU     __Vectors_End - __Vectors\r
 118 \r
 119                 AREA    |.text|, CODE, READONLY\r
 120 \r
 121 \r
 122 ; Reset Handler\r
 123 \r
 124 Reset_Handler   PROC\r
 125                 EXPORT  Reset_Handler             [WEAK]\r
 126                 IMPORT  SystemInit\r
 127                 IMPORT  __main\r
 128                 LDR     R0, =SystemInit\r
 129                 BLX     R0\r
 130                 LDR     R0, =__main\r
 131                 BX      R0\r
 132                 ENDP\r
 133 \r
 134 \r
 135 ; Dummy Exception Handlers (infinite loops which can be modified)\r
 136 \r
 137 NMI_Handler     PROC\r
 138                 EXPORT  NMI_Handler               [WEAK]\r
 139                 B       .\r
 140                 ENDP\r
 141 HardFault_Handler\\r
 142                 PROC\r
 143                 EXPORT  HardFault_Handler         [WEAK]\r
 144                 B       .\r
 145                 ENDP\r
 146 MemManage_Handler\\r
 147                 PROC\r
 148                 EXPORT  MemManage_Handler         [WEAK]\r
 149                 B       .\r
 150                 ENDP\r
 151 BusFault_Handler\\r
 152                 PROC\r
 153                 EXPORT  BusFault_Handler          [WEAK]\r
 154                 B       .\r
 155                 ENDP\r
 156 UsageFault_Handler\\r
 157                 PROC\r
 158                 EXPORT  UsageFault_Handler        [WEAK]\r
 159                 B       .\r
 160                 ENDP\r
 161 SecureFault_Handler\\r
 162                 PROC\r
 163                 EXPORT  SecureFault_Handler       [WEAK]\r
 164                 B       .\r
 165                 ENDP\r
 166 SVC_Handler     PROC\r
 167                 EXPORT  SVC_Handler               [WEAK]\r
 168                 B       .\r
 169                 ENDP\r
 170 DebugMon_Handler\\r
 171                 PROC\r
 172                 EXPORT  DebugMon_Handler          [WEAK]\r
 173                 B       .\r
 174                 ENDP\r
 175 PendSV_Handler  PROC\r
 176                 EXPORT  PendSV_Handler            [WEAK]\r
 177                 B       .\r
 178                 ENDP\r
 179 SysTick_Handler PROC\r
 180                 EXPORT  SysTick_Handler           [WEAK]\r
 181                 B       .\r
 182                 ENDP\r
 183 \r
 184 Default_Handler PROC\r
 185 \r
 186                 EXPORT  WDT_IRQHandler            [WEAK]\r
 187                 EXPORT  RTC_IRQHandler            [WEAK]\r
 188                 EXPORT  TIM0_IRQHandler           [WEAK]\r
 189                 EXPORT  TIM2_IRQHandler           [WEAK]\r
 190                 EXPORT  MCIA_IRQHandler           [WEAK]\r
 191                 EXPORT  MCIB_IRQHandler           [WEAK]\r
 192                 EXPORT  UART0_IRQHandler          [WEAK]\r
 193                 EXPORT  UART1_IRQHandler          [WEAK]\r
 194                 EXPORT  UART2_IRQHandler          [WEAK]\r
 195                 EXPORT  UART3_IRQHandler          [WEAK]\r
 196                 EXPORT  UART4_IRQHandler          [WEAK]\r
 197                 EXPORT  AACI_IRQHandler           [WEAK]\r
 198                 EXPORT  CLCD_IRQHandler           [WEAK]\r
 199                 EXPORT  ENET_IRQHandler           [WEAK]\r
 200                 EXPORT  USBDC_IRQHandler          [WEAK]\r
 201                 EXPORT  USBHC_IRQHandler          [WEAK]\r
 202                 EXPORT  CHLCD_IRQHandler          [WEAK]\r
 203                 EXPORT  FLEXRAY_IRQHandler        [WEAK]\r
 204                 EXPORT  CAN_IRQHandler            [WEAK]\r
 205                 EXPORT  LIN_IRQHandler            [WEAK]\r
 206                 EXPORT  I2C_IRQHandler            [WEAK]\r
 207                 EXPORT  CPU_CLCD_IRQHandler       [WEAK]\r
 208                 EXPORT  SPI_IRQHandler            [WEAK]\r
 209 \r
 210 WDT_IRQHandler\r
 211 RTC_IRQHandler\r
 212 TIM0_IRQHandler\r
 213 TIM2_IRQHandler\r
 214 MCIA_IRQHandler\r
 215 MCIB_IRQHandler\r
 216 UART0_IRQHandler\r
 217 UART1_IRQHandler\r
 218 UART2_IRQHandler\r
 219 UART3_IRQHandler\r
 220 UART4_IRQHandler\r
 221 AACI_IRQHandler\r
 222 CLCD_IRQHandler\r
 223 ENET_IRQHandler\r
 224 USBDC_IRQHandler\r
 225 USBHC_IRQHandler\r
 226 CHLCD_IRQHandler\r
 227 FLEXRAY_IRQHandler\r
 228 CAN_IRQHandler\r
 229 LIN_IRQHandler\r
 230 I2C_IRQHandler\r
 231 CPU_CLCD_IRQHandler\r
 232 SPI_IRQHandler\r
 233                 B       .\r
 234 \r
 235                 ENDP\r
 236 \r
 237 \r
 238                 ALIGN\r
 239 \r
 240 \r
 241 ; User Initial Stack & Heap\r
 242 \r
 243                 IF      :DEF:__MICROLIB\r
 244 \r
 245                 EXPORT  __initial_sp\r
 246                 EXPORT  __heap_base\r
 247                 EXPORT  __heap_limit\r
 248 \r
 249                 ELSE\r
 250 \r
 251                 IMPORT  __use_two_region_memory\r
 252                 EXPORT  __user_initial_stackheap\r
 253 \r
 254 __user_initial_stackheap PROC\r
 255                 LDR     R0, =  Heap_Mem\r
 256                 LDR     R1, =(Stack_Mem + Stack_Size)\r
 257                 LDR     R2, = (Heap_Mem +  Heap_Size)\r
 258                 LDR     R3, = Stack_Mem\r
 259                 BX      LR\r
 260                 ENDP\r
 261 \r
 262                 ALIGN\r
 263 \r
 264                 ENDIF\r
 265 \r
 266 \r
 267                 END\r