1 /******************************************************************************
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3 * @brief CMSIS MPU API for Armv8-M MPU
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5 * @date 10. January 2018
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6 ******************************************************************************/
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8 * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
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10 * SPDX-License-Identifier: Apache-2.0
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12 * Licensed under the Apache License, Version 2.0 (the License); you may
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13 * not use this file except in compliance with the License.
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14 * You may obtain a copy of the License at
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16 * www.apache.org/licenses/LICENSE-2.0
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18 * Unless required by applicable law or agreed to in writing, software
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19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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21 * See the License for the specific language governing permissions and
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22 * limitations under the License.
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25 #if defined ( __ICCARM__ )
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26 #pragma system_include /* treat file as system include file for MISRA check */
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27 #elif defined (__clang__)
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28 #pragma clang system_header /* treat file as system include file */
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31 #ifndef ARM_MPU_ARMV8_H
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32 #define ARM_MPU_ARMV8_H
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34 /** \brief Attribute for device memory (outer only) */
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35 #define ARM_MPU_ATTR_DEVICE ( 0U )
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37 /** \brief Attribute for non-cacheable, normal memory */
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38 #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
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40 /** \brief Attribute for normal memory (outer and inner)
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41 * \param NT Non-Transient: Set to 1 for non-transient data.
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42 * \param WB Write-Back: Set to 1 to use write-back update policy.
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43 * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
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44 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
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46 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
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47 (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
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49 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
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50 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
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52 /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
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53 #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
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55 /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
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56 #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
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58 /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
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59 #define ARM_MPU_ATTR_DEVICE_GRE (3U)
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61 /** \brief Memory Attribute
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62 * \param O Outer memory attributes
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63 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
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65 #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
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67 /** \brief Normal memory non-shareable */
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68 #define ARM_MPU_SH_NON (0U)
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70 /** \brief Normal memory outer shareable */
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71 #define ARM_MPU_SH_OUTER (2U)
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73 /** \brief Normal memory inner shareable */
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74 #define ARM_MPU_SH_INNER (3U)
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76 /** \brief Memory access permissions
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77 * \param RO Read-Only: Set to 1 for read-only memory.
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78 * \param NP Non-Privileged: Set to 1 for non-privileged memory.
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80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
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82 /** \brief Region Base Address Register value
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83 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
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84 * \param SH Defines the Shareability domain for this memory region.
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85 * \param RO Read-Only: Set to 1 for a read-only memory region.
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86 * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
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87 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
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89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
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90 ((BASE & MPU_RBAR_BASE_Msk) | \
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91 ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
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92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
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93 ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
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95 /** \brief Region Limit Address Register value
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96 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
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97 * \param IDX The attribute index to be associated with this memory region.
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99 #define ARM_MPU_RLAR(LIMIT, IDX) \
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100 ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
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101 ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
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105 * Struct for a single MPU Region
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108 uint32_t RBAR; /*!< Region Base Address Register value */
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109 uint32_t RLAR; /*!< Region Limit Address Register value */
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110 } ARM_MPU_Region_t;
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112 /** Enable the MPU.
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113 * \param MPU_Control Default access permissions for unconfigured regions.
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115 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
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119 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
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120 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
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121 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
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125 /** Disable the MPU.
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127 __STATIC_INLINE void ARM_MPU_Disable(void)
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131 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
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132 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
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134 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
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138 /** Enable the Non-secure MPU.
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139 * \param MPU_Control Default access permissions for unconfigured regions.
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141 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
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145 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
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146 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
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147 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
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151 /** Disable the Non-secure MPU.
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153 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
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157 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
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158 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
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160 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
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164 /** Set the memory attribute encoding to the given MPU.
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165 * \param mpu Pointer to the MPU to be configured.
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166 * \param idx The attribute index to be set [0-7]
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167 * \param attr The attribute value to be set.
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169 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
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171 const uint8_t reg = idx / 4U;
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172 const uint32_t pos = ((idx % 4U) * 8U);
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173 const uint32_t mask = 0xFFU << pos;
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175 if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
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176 return; // invalid index
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179 mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
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182 /** Set the memory attribute encoding.
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183 * \param idx The attribute index to be set [0-7]
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184 * \param attr The attribute value to be set.
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186 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
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188 ARM_MPU_SetMemAttrEx(MPU, idx, attr);
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192 /** Set the memory attribute encoding to the Non-secure MPU.
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193 * \param idx The attribute index to be set [0-7]
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194 * \param attr The attribute value to be set.
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196 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
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198 ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
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202 /** Clear and disable the given MPU region of the given MPU.
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203 * \param mpu Pointer to MPU to be used.
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204 * \param rnr Region number to be cleared.
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206 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
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212 /** Clear and disable the given MPU region.
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213 * \param rnr Region number to be cleared.
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215 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
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217 ARM_MPU_ClrRegionEx(MPU, rnr);
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221 /** Clear and disable the given Non-secure MPU region.
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222 * \param rnr Region number to be cleared.
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224 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
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226 ARM_MPU_ClrRegionEx(MPU_NS, rnr);
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230 /** Configure the given MPU region of the given MPU.
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231 * \param mpu Pointer to MPU to be used.
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232 * \param rnr Region number to be configured.
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233 * \param rbar Value for RBAR register.
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234 * \param rlar Value for RLAR register.
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236 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
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243 /** Configure the given MPU region.
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244 * \param rnr Region number to be configured.
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245 * \param rbar Value for RBAR register.
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246 * \param rlar Value for RLAR register.
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248 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
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250 ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
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254 /** Configure the given Non-secure MPU region.
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255 * \param rnr Region number to be configured.
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256 * \param rbar Value for RBAR register.
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257 * \param rlar Value for RLAR register.
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259 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
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261 ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
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265 /** Memcopy with strictly ordered memory access, e.g. for register targets.
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266 * \param dst Destination data is copied to.
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267 * \param src Source data is copied from.
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268 * \param len Amount of data words to be copied.
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270 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
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273 for (i = 0U; i < len; ++i)
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279 /** Load the given number of MPU regions from a table to the given MPU.
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280 * \param mpu Pointer to the MPU registers to be used.
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281 * \param rnr First region number to be configured.
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282 * \param table Pointer to the MPU configuration table.
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283 * \param cnt Amount of regions to be configured.
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285 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
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287 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
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290 orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
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292 uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
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293 uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
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295 mpu->RNR = rnrBase;
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296 while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
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297 uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
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298 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
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302 rnrBase += MPU_TYPE_RALIASES;
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303 mpu->RNR = rnrBase;
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306 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
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310 /** Load the given number of MPU regions from a table.
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311 * \param rnr First region number to be configured.
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312 * \param table Pointer to the MPU configuration table.
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313 * \param cnt Amount of regions to be configured.
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315 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
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317 ARM_MPU_LoadEx(MPU, rnr, table, cnt);
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321 /** Load the given number of MPU regions from a table to the Non-secure MPU.
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322 * \param rnr First region number to be configured.
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323 * \param table Pointer to the MPU configuration table.
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324 * \param cnt Amount of regions to be configured.
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326 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
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328 ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
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