git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_MPU_Static_Simulator_Keil_GCC/Keil_Specific/startup_MPS_CM4.S

   1 ;/*****************************************************************************\r
   2 ; * @file:    startup_MPS_CM4.s\r
   3 ; * @purpose: CMSIS Cortex-M4 Core Device Startup File\r
   4 ; *           for the ARM 'Microcontroller Prototyping System'\r
   5 ; * @version: V1.00\r
   6 ; * @date:    1. Jun. 2010\r
   7 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
   8 ; *\r
   9 ; * Copyright (C) 2008-2010 ARM Limited. All rights reserved.\r
  10 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M4\r
  11 ; * processor based microcontrollers.  This file can be freely distributed\r
  12 ; * within development tools that are supporting such ARM based processors.\r
  13 ; *\r
  14 ; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
  15 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
  16 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
  17 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
  18 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
  19 ; *\r
  20 ; ****************************************************************************/\r
  21 \r
  22 \r
  23 ; <h> Stack Configuration\r
  24 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
  25 ; </h>\r
  26 Stack_Size      EQU     0x00000800\r
  27 \r
  28                 AREA    STACK, NOINIT, READWRITE, ALIGN=3\r
  29 Stack_Mem       SPACE   Stack_Size\r
  30 __initial_sp\r
  31 \r
  32 \r
  33 ; <h> Heap Configuration\r
  34 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
  35 ; </h>\r
  36 \r
  37 Heap_Size       EQU     0x00000000\r
  38 \r
  39                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3\r
  40 __heap_base\r
  41 Heap_Mem        SPACE   Heap_Size\r
  42 __heap_limit\r
  43 \r
  44 \r
  45                 PRESERVE8\r
  46                 THUMB\r
  47 \r
  48 \r
  49 ; Vector Table Mapped to Address 0 at Reset\r
  50 \r
  51                 AREA    RESET, DATA, READONLY\r
  52                 EXPORT  __Vectors\r
  53 \r
  54 __Vectors       DCD     __initial_sp              ; Top of Stack\r
  55                 DCD     Reset_Handler             ; Reset Handler\r
  56                 DCD     NMI_Handler               ; NMI Handler\r
  57                 DCD     HardFault_Handler         ; Hard Fault Handler\r
  58                 DCD     MemManage_Handler         ; MPU Fault Handler\r
  59                 DCD     BusFault_Handler          ; Bus Fault Handler\r
  60                 DCD     UsageFault_Handler        ; Usage Fault Handler\r
  61                 DCD     0                         ; Reserved\r
  62                 DCD     0                         ; Reserved\r
  63                 DCD     0                         ; Reserved\r
  64                 DCD     0                         ; Reserved\r
  65                 DCD     SVC_Handler               ; SVCall Handler\r
  66                 DCD     DebugMon_Handler          ; Debug Monitor Handler\r
  67                 DCD     0                         ; Reserved\r
  68                 DCD     PendSV_Handler            ; PendSV Handler\r
  69                 DCD     SysTick_Handler           ; SysTick Handler\r
  70 \r
  71 \r
  72                 AREA    |.text|, CODE, READONLY\r
  73 ;                AREA    RESET, CODE, READONLY\r
  74 \r
  75 ; Reset Handler\r
  76 \r
  77 Reset_Handler   PROC\r
  78                 EXPORT  Reset_Handler             [WEAK]\r
  79                 IMPORT  __main\r
  80 \r
  81                 ; Remap vector table\r
  82                 LDR     R0, =__Vectors\r
  83                 LDR     R1, =0xE000ED08\r
  84                 STR     R0,  [r1]\r
  85                 NOP\r
  86 \r
  87                 IF      {CPU} = "Cortex-M4.fp"\r
  88                 LDR     R0, =0xE000ED88           ; Enable CP10,CP11\r
  89                 LDR     R1,[R0]\r
  90                 ORR     R1,R1,#(0xF << 20)\r
  91                 STR     R1,[R0]\r
  92                 ENDIF\r
  93 \r
  94                 LDR     R0, =__main\r
  95                 BX      R0\r
  96                 ENDP\r
  97 \r
  98 \r
  99 ; Dummy Exception Handlers (infinite loops which can be modified)\r
 100 \r
 101 NMI_Handler     PROC\r
 102                 EXPORT  NMI_Handler               [WEAK]\r
 103                 B       .\r
 104                 ENDP\r
 105 HardFault_Handler\\r
 106                 PROC\r
 107                 EXPORT  HardFault_Handler         [WEAK]\r
 108                 B       .\r
 109                 ENDP\r
 110 MemManage_Handler\\r
 111                 PROC\r
 112                 EXPORT  MemManage_Handler         [WEAK]\r
 113                 B       .\r
 114                 ENDP\r
 115 BusFault_Handler\\r
 116                 PROC\r
 117                 EXPORT  BusFault_Handler          [WEAK]\r
 118                 B       .\r
 119                 ENDP\r
 120 UsageFault_Handler\\r
 121                 PROC\r
 122                 EXPORT  UsageFault_Handler        [WEAK]\r
 123                 B       .\r
 124                 ENDP\r
 125 SVC_Handler     PROC\r
 126                 EXPORT  SVC_Handler               [WEAK]\r
 127                 B       .\r
 128                 ENDP\r
 129 DebugMon_Handler\\r
 130                 PROC\r
 131                 EXPORT  DebugMon_Handler          [WEAK]\r
 132                 B       .\r
 133                 ENDP\r
 134 PendSV_Handler  PROC\r
 135                 EXPORT  PendSV_Handler            [WEAK]\r
 136                 B       .\r
 137                 ENDP\r
 138 SysTick_Handler PROC\r
 139                 EXPORT  SysTick_Handler           [WEAK]\r
 140                 B       .\r
 141                 ENDP\r
 142 \r
 143 \r
 144                 ALIGN\r
 145 \r
 146 \r
 147 ; User Initial Stack & Heap\r
 148 \r
 149                 IF      :DEF:__MICROLIB\r
 150 \r
 151                 EXPORT  __initial_sp\r
 152                 EXPORT  __heap_base\r
 153                 EXPORT  __heap_limit\r
 154 \r
 155                 ELSE\r
 156 \r
 157                 IMPORT  __use_two_region_memory\r
 158                 EXPORT  __user_initial_stackheap\r
 159 __user_initial_stackheap\r
 160 \r
 161                 LDR     R0, =  Heap_Mem\r
 162                 LDR     R1, =(Stack_Mem + Stack_Size)\r
 163                 LDR     R2, = (Heap_Mem +  Heap_Size)\r
 164                 LDR     R3, = Stack_Mem\r
 165                 BX      LR\r
 166 \r
 167                 ALIGN\r
 168 \r
 169                 ENDIF\r
 170 \r
 171 \r
 172                 END\r