1 /****************************************************************************************************************************************************************
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3 * This software is supplied by Renesas Electronics Corporation and is only
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4 * intended for use with Renesas products. No other uses are authorized. This
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5 * software is owned by Renesas Electronics Corporation and is protected under
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6 * all applicable laws, including copyright laws.
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7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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16 * Renesas reserves the right, without notice, to make changes to this software
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17 * and to discontinue the availability of this software. By using this software,
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18 * you agree to the additional terms and conditions found by accessing the
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20 * http://www.renesas.com/disclaimer
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22 * Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
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23 ****************************************************************************************************************************************************************/
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24 /***********************************************************************************************************************
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25 * File Name : GNU_LINKER_ATCM.ld
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26 * Device(s) : RZ/T1 (R7S910018)
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27 * Tool-Chain : GNUARM-NONEv14.02-EABI
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28 * H/W Platform : RSK+RZT1 CPU Board
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29 * Description : Linker file for projects that require to load and run from RAM (ATCM)
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30 ***********************************************************************************************************************/
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31 /***********************************************************************************************************************
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32 * History : DD.MM.YYYY Version Description
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34 ***********************************************************************************************************************/
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35 OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
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39 /* Base Address RAM Memory Table 1 Mbyte on-chip RAM */
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42 /* Internal RAM address range H'2000_0000 to H'2001_FFFF is configured as data retention RAM */
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43 /* Write access to this address range has to be enabled by writing to registers SYSCR1 and SYSCR2 */
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44 ATCM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 /* (512KB) H'00000000 to H'0007FFFF */
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45 BTCM (rwx) : ORIGIN = 0x00800000, LENGTH = 0x00800000 /* (32KB) H'00800000 to H'00807FFF */
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46 BUFFER_RAM (rwx) : ORIGIN = 0x20200000, LENGTH = 0x00100000 /* (1024KB) H'08000000 to H'0FFFFFFF */
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47 DATA_RAM0 (rwx) : ORIGIN = 0x24000000, LENGTH = 0x00080000 /* (512KB) H'22000000 to H'2207FFFF */
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48 DATA_RAM1 (rwx) : ORIGIN = 0x22000000, LENGTH = 0x00080000 /* (512KB) H'24000000 to H'2407FFFF */
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50 SPIBSC (rw) : ORIGIN = 0x30000000, LENGTH = 0x04000000 /* attached to H'30000000 to H'33FFFFFF */
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51 CS0 (rw) : ORIGIN = 0x40000000, LENGTH = 0x04000000 /* attached to H'40000000 to H'43FFFFFF */
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52 CS1 (rw) : ORIGIN = 0x44000000, LENGTH = 0x04000000 /* attached to H'44000000 to H'47FFFFFF */
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53 CS2 (rw) : ORIGIN = 0x48000000, LENGTH = 0x04000000 /* attached to H'40000000 to H'4CFFFFFF */
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54 CS3 (rw) : ORIGIN = 0x4C000000, LENGTH = 0x04000000 /* attached to H'4C000000 to H'4FFFFFFF */
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55 CS4 (rw) : ORIGIN = 0x50000000, LENGTH = 0x04000000 /* attached to H'50000000 to H'53FFFFFF */
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56 CS5 (rw) : ORIGIN = 0x54000000, LENGTH = 0x04000000 /* attached to H'54000000 to H'57FFFFFF */
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58 /* Mapped memory type */
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59 SPI_ROM (rw) : ORIGIN = 0x30000000, LENGTH = 0x04000000
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60 CS0_ROM (rw) : ORIGIN = 0x40000000, LENGTH = 0x04000000
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61 CS1_ROM (rw) : ORIGIN = 0x44000000, LENGTH = 0x04000000
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62 SDRAM0_EXT (rw) : ORIGIN = 0x48000000, LENGTH = 0x04000000
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63 SDRAM1_EXT (rw) : ORIGIN = 0x4C000000, LENGTH = 0x04000000
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66 SYS_STACK_SIZE = 0x200; /* Application stack size */
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67 SVC_STACK_SIZE = 0x200; /* SVC mode stack */
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68 IRQ_STACK_SIZE = 0x200; /* IRQ mode stack */
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69 FIQ_STACK_SIZE = 0x200; /* FRQ mode stack */
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70 UND_STACK_SIZE = 0x200; /* SVC mode stack */
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71 ABT_STACK_SIZE = 0x200; /* ABT mode stack */
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72 HEAP_STACK_SIZE = 0x1000; /* Heap stack size */
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74 ATCM_BASE = 0x00000000; /* User application located here */
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75 BTCM_BASE = 0x00800000; /* BTCM base address */
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77 USER_EXEC_BASE = 0x00000000; /* Application loads and runs from here */
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79 USER_RAM = 0x20000000; /* Application's RAM base */
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81 STACK_BASE = 0x00807800; /* Stacks located in BTCM */
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83 SDRAM0_BASE = 0x48000000; /* SDRAM1 is attached to CS2 space */
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84 SDRAM1_BASE = 0x4C000000; /* SDRAM1 is attached to CS3 space */
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88 .reset USER_EXEC_BASE :
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113 _start_data_ROM = .;
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124 _ram_data_size = (_end_data_ROM - _start_data_ROM);
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129 _start_data_RAM = .;
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130 . += _ram_data_size;
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137 PROVIDE(__bss_start__ = .);
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142 PROVIDE(__bss_end__ = .);
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153 . += HEAP_STACK_SIZE;
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157 .sys_stack STACK_BASE :
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159 sys_stack_start = .;
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162 . += SYS_STACK_SIZE;
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166 .svc_stack sys_stack_end :
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168 svc_stack_start = .;
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171 . += SVC_STACK_SIZE;
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175 .irq_stack svc_stack_end :
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177 irq_stack_start = .;
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180 . += IRQ_STACK_SIZE;
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184 .fiq_stack irq_stack_end :
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186 fiq_stack_start = .;
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189 . += FIQ_STACK_SIZE;
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193 .und_stack fiq_stack_end :
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195 und_stack_start = .;
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198 . += UND_STACK_SIZE;
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202 .abt_stack und_stack_end :
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204 abt_stack_start = .;
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207 . += ABT_STACK_SIZE;
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211 /* NOLOAD directs linker NOT to fill VRAMx_SECTION with 0. */
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212 /* Usage of NOLOAD increases speed of linker and download to target */
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213 .sdram0_section SDRAM0_BASE (NOLOAD) : {} > SDRAM0_EXT
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214 .sdram1_section SDRAM1_BASE (NOLOAD) : {} > SDRAM1_EXT
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