1 /***********************************************************************************************************************
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3 * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
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4 * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
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5 * applicable laws, including copyright laws.
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6 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
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7 * OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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8 * NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
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9 * LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
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10 * INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
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11 * ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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12 * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
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13 * of this software. By using this software, you agree to the additional terms and conditions found by accessing the
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15 * http://www.renesas.com/disclaimer
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17 * Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
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18 ***********************************************************************************************************************/
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20 /***********************************************************************************************************************
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21 * File Name : r_cg_tpu.h
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22 * Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
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23 * Device(s) : R7S910018CBG
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24 * Tool-Chain : GCCARM
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25 * Description : This file implements device driver for TPU module.
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26 * Creation Date: 22/04/2015
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27 ***********************************************************************************************************************/
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31 /***********************************************************************************************************************
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32 Macro definitions (Register bit)
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33 ***********************************************************************************************************************/
\r
35 Timer Control Register (TCR)
\r
37 /* Time Prescaler Select (TPSC[2:0]) */
\r
38 #define _TPU_PCLKD_1 (0x00U) /* Internal clock: counts on PCLKD/1 */
\r
39 #define _TPU_PCLKD_4 (0x01U) /* Internal clock: counts on PCLKD/4 */
\r
40 #define _TPU_PCLKD_16 (0x02U) /* Internal clock: counts on PCLKD/16 */
\r
41 #define _TPU_PCLKD_64 (0x03U) /* Internal clock: counts on PCLKD/64 */
\r
42 #define _TPU_PCLKD_256 (0x06U) /* Internal clock: counts on PCLKD/256 */
\r
43 #define _TPU2_PCLKD_1024 (0x07U) /* TPU2 Internal clock: counts on PCLKD/1024 */
\r
44 #define _TPU3_PCLKD_1024 (0x05U) /* TPU3 Internal clock: counts on PCLKD/1024 */
\r
45 #define _TPU4_PCLKD_1024 (0x06U) /* TPU4 Internal clock: counts on PCLKD/1024 */
\r
46 #define _TPU8_PCLKD_1024 (0x07U) /* TPU8 Internal clock: counts on PCLKD/1024 */
\r
47 #define _TPU9_PCLKD_1024 (0x05U) /* TPU9 Internal clock: counts on PCLKD/1024 */
\r
48 #define _TPU10_PCLKD_1024 (0x06U) /* TPU10 Internal clock: counts on PCLKD/1024 */
\r
49 #define _TPU_PCLKD_4096 (0x07U) /* Internal clock: counts on PCLKD/4096 */
\r
50 #define _TPU_TCLKA (0x04U) /* External clock: counts on TCLKA pin input */
\r
51 #define _TPU_TCLKB (0x05U) /* External clock: counts on TCLKB pin input */
\r
52 #define _TPU_TCLKC_06 (0x06U) /* External clock: counts on TCLKC pin input */
\r
53 #define _TPU_TCLKC_05 (0x05U) /* External clock: counts on TCLKC pin input */
\r
54 #define _TPU_TCLKD (0x07U) /* External clock: counts on TCLKD pin input */
\r
55 #define _TPU_TCLKE (0x04U) /* External clock: counts on TCLKE pin input */
\r
56 #define _TPU_TCLKF (0x05U) /* External clock: counts on TCLKF pin input */
\r
57 #define _TPU_TCLKG_06 (0x06U) /* External clock: counts on TCLKG pin input */
\r
58 #define _TPU_TCLKG_05 (0x05U) /* External clock: counts on TCLKG pin input */
\r
59 #define _TPU_TCLKH (0x07U) /* External clock: counts on TCLKH pin input */
\r
60 #define _TPU2_COUNT (0x07U) /* TPU1: Counts on TPU2.TCNT counter overflow/underflow */
\r
61 #define _TPU5_COUNT (0x07U) /* TPU4: Counts on TPU5.TCNT counter overflow/underflow */
\r
62 #define _TPU8_COUNT (0x07U) /* TPU7: Counts on TPU8.TCNT counter overflow/underflow */
\r
63 #define _TPU11_COUNT (0x07U) /* TPU10: Counts on TPU11.TCNT counter overflow/underflow */
\r
64 /* Clock Edge Select (CKEG[1:0]) */
\r
65 #define _TPU_CKEG_IT_F (0x00U) /* Internal Clock: Count at falling edge */
\r
66 #define _TPU_CKEG_EX_R (0x00U) /* External Clock: Count at rising edge */
\r
67 #define _TPU_CKEG_IT_R (0x08U) /* Internal Clock: Count at rising edge */
\r
68 #define _TPU_CKEG_EX_F (0x08U) /* External Clock: Count at falling edge */
\r
69 #define _TPU_CKEG_BOTH (0x10U) /* Count at both edge */
\r
70 /* Counter Clear Select (CCLR[2:0]) */
\r
71 #define _TPU_CKCL_DIS (0x00U) /* TCNT clearing disabled */
\r
72 #define _TPU_CKCL_A (0x20U) /* TCNT cleared by TGRA compare match/input capture */
\r
73 #define _TPU_CKCL_B (0x40U) /* TCNT cleared by TGRB compare match/input capture */
\r
74 #define _TPU_CKCL_SYN (0x60U) /* TCNT cleared by counter clearing in another synchronous channel */
\r
75 #define _TPU_CKCL_C (0xA0U) /* TCNT cleared by TGRC compare match/input capture */
\r
76 #define _TPU_CKCL_D (0xC0U) /* TCNT cleared by TGRD compare match/input capture */
\r
79 Timer Mode Register (TMDR)
\r
81 /* Mode Select (MD[3:0]) */
\r
82 #define _TPU_NORMAL (0x00U) /* Normal mode */
\r
83 #define _TPU_PWM1 (0x02U) /* PWM mode 1 */
\r
84 #define _TPU_PWM2 (0x03U) /* PWM mode 2 */
\r
85 #define _TPU_COT1 (0x04U) /* Phase counting mode 1 */
\r
86 #define _TPU_COT2 (0x05U) /* Phase counting mode 2 */
\r
87 #define _TPU_COT3 (0x06U) /* Phase counting mode 3 */
\r
88 #define _TPU_COT4 (0x07U) /* Phase counting mode 4 */
\r
89 /* Buffer Operation A (BFA) */
\r
90 #define _TPU_BFA_NORMAL (0x00U) /* TPUm.TGRA operates normally (m = 0, 3, 6, 9) */
\r
91 #define _TPU_BFA_BUFFER (0x10U) /* TPUm.TGRA and TPUm.TGRC used together for buffer operation */
\r
92 /* Buffer Operation B (BFB) */
\r
93 #define _TPU_BFB_NORMAL (0x00U) /* TPUm.TGRB operates normally (m = 0, 3, 6, 9) */
\r
94 #define _TPU_BFB_BUFFER (0x20U) /* TPUm.TGRB and TPUm.TGRD used together for buffer operation */
\r
95 /* TGRB Input Capture Input Select (ICSELB) */
\r
96 #define _TPU_ICSELB_BPIN (0x00U) /* Input capture input source is TIOCBn pin */
\r
97 #define _TPU_ICSELB_APIN (0x40U) /* Input capture input source is TIOCAn pin (n = 0 to 11) */
\r
98 /* TGRD Input Capture Input Select (ICSELD) */
\r
99 #define _TPU_ICSELD_DPIN (0x00U) /* Input capture input source is TIOCDn pin */
\r
100 #define _TPU_ICSELD_CPIN (0x80U) /* Input capture input source is TIOCCn pin (n = 0, 3, 6, 9) */
\r
103 Timer I/O Control Register (TIOR)
\r
105 /* I/O Control A (IOA[3:0]) for TPU0.TIORH, TPU1.TIOR, TPU2.TIOR, TPU3.TIORH, TPU4.TIORH, TPU5.TIOR
\r
106 TPU6.TIORH, TPU7.TIOR, TPU8.TIOR, TPU9.TIORH, TPU10.TIOR, TPU11.TIOR*/
\r
107 #define _TPU_IOA_DISABLE (0x00U) /* Output prohibited */
\r
108 #define _TPU_IOA_LL (0x01U) /* Initial output is low. Low output at compare match */
\r
109 #define _TPU_IOA_LH (0x02U) /* Initial output is low. High output at compare match */
\r
110 #define _TPU_IOA_LT (0x03U) /* Initial output is low. Toggle output at compare match */
\r
111 #define _TPU_IOA_HL (0x05U) /* Initial output is high. Low output at compare match */
\r
112 #define _TPU_IOA_HH (0x06U) /* Initial output is high. High output at compare match */
\r
113 #define _TPU_IOA_HT (0x07U) /* Initial output is high. Toggle output at compare match */
\r
114 #define _TPU_IOA_IR (0x08U) /* Input capture at rising edge. */
\r
115 #define _TPU_IOA_IF (0x09U) /* Input capture at falling edge */
\r
116 #define _TPU_IOA_IB (0x0AU) /* Input capture at both edges */
\r
117 #define _TPU_IOA_EX (0x0CU) /* Input capture at TPU1.TCNT or TPU4.TCNT up-count/down-count
\r
118 or TPU7.TCNT or TPU10.TCNT up-count/down-count */
\r
119 #define _TPU_IOA_TGRA (0x0DU) /* Input capture at TPU0.TGRA or TPU3.TGRA compare match/input capture
\r
120 or TPU6.TGRA or TPU9.TGRA compare match/input capture */
\r
121 /* I/O Control B (IOB[3:0]) for TPU0.TIORH, TPU1.TIOR, TPU2.TIOR, TPU3.TIORH, TPU4.TIORH, TPU5.TIOR
\r
122 TPU6.TIORH, TPU7.TIOR, TPU8.TIOR, TPU9.TIORH, TPU10.TIOR, TPU11.TIOR*/
\r
123 #define _TPU_IOB_DISABLE (0x00U) /* Output prohibited */
\r
124 #define _TPU_IOB_LL (0x10U) /* Initial output is low. Low output at compare match */
\r
125 #define _TPU_IOB_LH (0x20U) /* Initial output is low. High output at compare match */
\r
126 #define _TPU_IOB_LT (0x30U) /* Initial output is low. Toggle output at compare match */
\r
127 #define _TPU_IOB_HL (0x50U) /* Initial output is high. Low output at compare match */
\r
128 #define _TPU_IOB_HH (0x60U) /* Initial output is high. High output at compare match */
\r
129 #define _TPU_IOB_HT (0x70U) /* Initial output is high. Toggle output at compare match */
\r
130 #define _TPU_IOB_IR (0x80U) /* Input capture at rising edge */
\r
131 #define _TPU_IOB_IF (0x90U) /* Input capture at falling edge */
\r
132 #define _TPU_IOB_IB (0xA0U) /* Input capture at both edges. */
\r
133 #define _TPU_IOB_EX (0xC0U) /* Input capture at TPU1.TCNT or TPU4.TCNT up-count/down-count
\r
134 or TPU7.TCNT or TPU10.TCNT up-count/down-count*/
\r
135 #define _TPU_IOB_TGRC (0xD0U) /* Input capture at TPU0.TGRC or TPU3.TGRC compare match/input capture
\r
136 or TPU6.TGRC or TPU9.TGRC compare match/input capture*/
\r
137 /* I/O Control C (IOC[3:0]) for TPU0.TIORL, TPU3.TIORL, TPU6.TIORL, TPU9.TIORL */
\r
138 #define _TPU_IOC_DISABLE (0x00U) /* Output prohibited */
\r
139 #define _TPU_IOC_LL (0x01U) /* Initial output is low. Low output at compare match */
\r
140 #define _TPU_IOC_LH (0x02U) /* Initial output is low. High output at compare match */
\r
141 #define _TPU_IOC_LT (0x03U) /* Initial output is low. Toggle output at compare match */
\r
142 #define _TPU_IOC_HL (0x05U) /* Initial output is high. Low output at compare match. */
\r
143 #define _TPU_IOC_HH (0x06U) /* Initial output is high. High output at compare match. */
\r
144 #define _TPU_IOC_HT (0x07U) /* Initial output is high. Toggle output at compare match. */
\r
145 #define _TPU_IOC_IR (0x08U) /* Input capture at rising edge. */
\r
146 #define _TPU_IOC_IF (0x09U) /* Input capture at falling edge. */
\r
147 #define _TPU_IOC_IB (0x0AU) /* Input capture at both edges. */
\r
148 #define _TPU_IOC_EX (0x0CU) /* Input capture at TPU1.TCNT or TPU4.TCNT up-count/down-count
\r
149 or TPU7.TCNT or TPU10.TCNT up-count/down-count. */
\r
150 /* I/O Control D (IOD[3:0]) for TPU0.TIORL, TPU3.TIORL, TPU6.TIORL, TPU9.TIOR */
\r
151 #define _TPU_IOD_DISABLE (0x00U) /* Output prohibited */
\r
152 #define _TPU_IOD_LL (0x10U) /* Initial output is low. Low output at compare match */
\r
153 #define _TPU_IOD_LH (0x20U) /* Initial output is low. High output at compare match */
\r
154 #define _TPU_IOD_LT (0x30U) /* Initial output is low. Toggle output at compare match */
\r
155 #define _TPU_IOD_HL (0x50U) /* Initial output is high. Low output at compare match. */
\r
156 #define _TPU_IOD_HH (0x60U) /* Initial output is high. High output at compare match. */
\r
157 #define _TPU_IOD_HT (0x70U) /* Initial output is high. Toggle output at compare match. */
\r
158 #define _TPU_IOD_IR (0x80U) /* Input capture at rising edge. */
\r
159 #define _TPU_IOD_IF (0x90U) /* Input capture at falling edge. */
\r
160 #define _TPU_IOD_IB (0xA0U) /* Input capture at both edges. */
\r
161 #define _TPU_IOD_EX (0xC0U) /* Input capture at TPU1.TCNT or TPU4.TCNT up-count/down-count
\r
162 or TPU7.TCNT or TPU10.TCNT up-count/down-count. */
\r
165 Timer Start Registers (TSTRA)
\r
167 /* Counter Start 0 (CST0) */
\r
168 #define _TPU_CST0_OFF (0x00U) /* TPU0.TCNT performs count stop */
\r
169 #define _TPU_CST0_ON (0x01U) /* TPU0.TCNT performs count operation */
\r
170 /* Counter Start 1 (CST1) */
\r
171 #define _TPU_CST1_OFF (0x00U) /* TPU1.TCNT performs count stop */
\r
172 #define _TPU_CST1_ON (0x02U) /* TPU1.TCNT performs count operation */
\r
173 /* Counter Start 2 (CST2) */
\r
174 #define _TPU_CST2_OFF (0x00U) /* TPU3.TCNT performs count stop */
\r
175 #define _TPU_CST2_ON (0x04U) /* TPU3.TCNT performs count operation */
\r
176 /* Counter Start 3 (CST3) */
\r
177 #define _TPU_CST3_OFF (0x00U) /* TPU3.TCNT performs count stop */
\r
178 #define _TPU_CST3_ON (0x08U) /* TPU3.TCNT performs count operation */
\r
179 /* Counter Start 4 (CST4) */
\r
180 #define _TPU_CST4_OFF (0x00U) /* TPU4.TCNT performs count stop */
\r
181 #define _TPU_CST4_ON (0x10U) /* TPU4.TCNT performs count operation */
\r
182 /* Counter Start 5 (CST5) */
\r
183 #define _TPU_CST5_OFF (0x00U) /* TPU5.TCNT performs count stop */
\r
184 #define _TPU_CST5_ON (0x20U) /* TPU5.TCNT performs count operation */
\r
187 Timer Start Registers (TSTRB)
\r
189 /* Counter Start 6 (CST0) */
\r
190 #define _TPU_CST6_OFF (0x00U) /* TPU6.TCNT performs count stop */
\r
191 #define _TPU_CST6_ON (0x01U) /* TPU6.TCNT performs count operation */
\r
192 /* Counter Start 7 (CST1) */
\r
193 #define _TPU_CST7_OFF (0x00U) /* TPU7.TCNT performs count stop */
\r
194 #define _TPU_CST7_ON (0x02U) /* TPU7.TCNT performs count operation */
\r
195 /* Counter Start 8 (CST2) */
\r
196 #define _TPU_CST8_OFF (0x00U) /* TPU8.TCNT performs count stop */
\r
197 #define _TPU_CST8_ON (0x04U) /* TPU8.TCNT performs count operation */
\r
198 /* Counter Start 9 (CST3) */
\r
199 #define _TPU_CST9_OFF (0x00U) /* TPU9.TCNT performs count stop */
\r
200 #define _TPU_CST9_ON (0x08U) /* TPU9.TCNT performs count operation */
\r
201 /* Counter Start 10 (CST4) */
\r
202 #define _TPU_CST10_OFF (0x00U) /* TPU10.TCNT performs count stop */
\r
203 #define _TPU_CST10_ON (0x10U) /* TPU10.TCNT performs count operation */
\r
204 /* Counter Start 11 (CST5) */
\r
205 #define _TPU_CST11_OFF (0x00U) /* TPU11.TCNT performs count stop */
\r
206 #define _TPU_CST11_ON (0x20U) /* TPU11.TCNT performs count operation */
\r
209 Noise Filter Control Register (NFCR)
\r
211 /* Noise Filter A Enable Bit (NFAEN) */
\r
212 #define _TPU_NFAEN_DISABLE (0x00U) /* The noise filter for the TIOCAm pin is disabled */
\r
213 #define _TPU_NFAEN_ENABLE (0x01U) /* The noise filter for the TIOCAm pin is enabled */
\r
214 /* Noise Filter B Enable Bit (NFBEN) */
\r
215 #define _TPU_NFBEN_DISABLE (0x00U) /* The noise filter for the TIOCBm pin is disabled */
\r
216 #define _TPU_NFBEN_ENABLE (0x02U) /* The noise filter for the TIOCBm pin is enabled */
\r
217 /* Noise Filter C Enable Bit (NFCEN) */
\r
218 #define _TPU_NFCEN_DISABLE (0x00U) /* The noise filter for the TIOCCm pin is disabled */
\r
219 #define _TPU_NFCEN_ENABLE (0x04U) /* The noise filter for the TIOCCm pin is enabled */
\r
220 /* Noise Filter D Enable Bit (NFDEN) */
\r
221 #define _TPU_NFDEN_DISABLE (0x00U) /* The noise filter for the TIOCDm pin is disabled */
\r
222 #define _TPU_NFDEN_ENABLE (0x08U) /* The noise filter for the TIOCDm pin is enabled */
\r
223 /* Noise Filter Clock Select (NFCS[1:0]) */
\r
224 #define _TPU_NFCS_PCLKD_1 (0x00U) /* PCLKD/1 */
\r
225 #define _TPU_NFCS_PCLKD_8 (0x10U) /* PCLKD/8 */
\r
226 #define _TPU_NFCS_PCLKD_32 (0x20U) /* PCLKD/32 */
\r
227 #define _TPU_NFCS_EXCLK (0x30U) /* The clock source for counting is the external clock */
\r
230 PWM Feedback Select Register (PWMFBSLR)
\r
232 /* TPU (Unit 0) Internal PWM Feedback Enable (TPU0EN)*/
\r
233 #define _TPU_TPU0EN_DISABLE (0x00000000UL) /* Internal PWM feedback input function unit 0 is disabled */
\r
234 #define _TPU_TPU0EN_ENABLE (0x00000001UL) /* Internal PWM feedback input function unit 0 is enabled */
\r
235 /* Internal PWM Feedback Input Source Select 0 (FBSL0[2:0]) */
\r
236 #define _TPU0_PWM_SIG_MTU34 (0x00000010UL) /* PWM output signals of MTU3 and MTU4 */
\r
237 #define _TPU0_PWM_SIG_MTU67 (0x00000014UL) /* PWM output signals of MTU6 and MTU7 */
\r
238 #define _TPU0_PWM_SIG_GPT02 (0x00000018UL) /* PWM output signals of GPT0 to GPT2 */
\r
239 /* TPU (Unit 1) Internal PWM Feedback Enable (TPU1EN)*/
\r
240 #define _TPU_TPU1EN_DISABLE (0x00000000UL) /* Internal PWM feedback input function unit 1 is disabled */
\r
241 #define _TPU_TPU1EN_ENABLE (0x00000100UL) /* Internal PWM feedback input function unit 1 is enabled */
\r
242 /* Internal PWM Feedback Input Source Select 1 (FBSL1[2:0]) */
\r
243 #define _TPU1_PWM_SIG_MTU34 (0x00001000UL) /* PWM output signals of MTU3 and MTU4 */
\r
244 #define _TPU1_PWM_SIG_MTU67 (0x00001400UL) /* PWM output signals of MTU6 and MTU7 */
\r
245 #define _TPU1_PWM_SIG_GPT02 (0x00001800UL) /* PWM output signals of GPT0 to GPT2 */
\r
247 Timer Interrupt Enable Register (TIER)
\r
249 /* TGR Interrupt Enable A (TGIEA) */
\r
250 #define _TPU_TGIEA_DISABLE (0x00U) /* Interrupt requests TGIA disabled */
\r
251 #define _TPU_TGIEA_ENABLE (0x01U) /* Interrupt requests TGIA enabled */
\r
252 /* TGR Interrupt Enable B (TGIEB) */
\r
253 #define _TPU_TGIEB_DISABLE (0x00U) /* Interrupt requests TGIB disabled */
\r
254 #define _TPU_TGIEB_ENABLE (0x02U) /* Interrupt requests TGIB enabled */
\r
255 /* TGR Interrupt Enable C (TGIEC) */
\r
256 #define _TPU_TGIEC_DISABLE (0x00U) /* Interrupt requests TGIC disabled */
\r
257 #define _TPU_TGIEC_ENABLE (0x04U) /* Interrupt requests TGIC enabled */
\r
258 /* TGR Interrupt Enable D (TGIED) */
\r
259 #define _TPU_TGIED_DISABLE (0x00U) /* Interrupt requests TGID disabled */
\r
260 #define _TPU_TGIED_ENABLE (0x08U) /* Interrupt requests TGID enabled */
\r
261 /* Overflow Interrupt Enable (TCIEV) */
\r
262 #define _TPU_TCIEV_DISABLE (0x00U) /* Interrupt requests TCIV disabled */
\r
263 #define _TPU_TCIEV_ENABLE (0x10U) /* Interrupt requests TCIV enabled */
\r
264 /* Underflow Interrupt Enable (TCIEU) */
\r
265 #define _TPU_TCIEU_DISABLE (0x00U) /* Interrupt requests TCIU disabled */
\r
266 #define _TPU_TCIEU_ENABLE (0x20U) /* Interrupt requests TCIU enabled */
\r
267 /* A/D Converter Start Request Enable (TTGE) */
\r
268 #define _TPU_TTGE_DISABLE (0x00U) /* A/D converter start request generation disabled */
\r
269 #define _TPU_TTGE_ENABLE (0x80U) /* A/D converter start request generation enabled */
\r
272 Interrupt Source Priority Register n (PRLn)
\r
274 /* Interrupt Priority Level Select (PRL[3:0]) */
\r
275 #define _TPU_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (highest) */
\r
276 #define _TPU_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */
\r
277 #define _TPU_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */
\r
278 #define _TPU_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */
\r
279 #define _TPU_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */
\r
280 #define _TPU_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */
\r
281 #define _TPU_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */
\r
282 #define _TPU_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */
\r
283 #define _TPU_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */
\r
284 #define _TPU_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */
\r
285 #define _TPU_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */
\r
286 #define _TPU_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */
\r
287 #define _TPU_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */
\r
288 #define _TPU_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */
\r
289 #define _TPU_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */
\r
290 #define _TPU_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 */
\r
291 #define _TPU_PRIORITY_LEVEL16 (0x00000000UL) /* Level 16 */
\r
292 #define _TPU_PRIORITY_LEVEL17 (0x00000001UL) /* Level 17 */
\r
293 #define _TPU_PRIORITY_LEVEL18 (0x00000002UL) /* Level 18 */
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294 #define _TPU_PRIORITY_LEVEL19 (0x00000003UL) /* Level 19 */
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295 #define _TPU_PRIORITY_LEVEL20 (0x00000004UL) /* Level 20 */
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296 #define _TPU_PRIORITY_LEVEL21 (0x00000005UL) /* Level 21 */
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297 #define _TPU_PRIORITY_LEVEL22 (0x00000006UL) /* Level 22 */
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298 #define _TPU_PRIORITY_LEVEL23 (0x00000007UL) /* Level 23 */
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299 #define _TPU_PRIORITY_LEVEL24 (0x00000008UL) /* Level 24 */
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300 #define _TPU_PRIORITY_LEVEL25 (0x00000009UL) /* Level 25 */
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301 #define _TPU_PRIORITY_LEVEL26 (0x0000000AUL) /* Level 26 */
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302 #define _TPU_PRIORITY_LEVEL27 (0x0000000BUL) /* Level 27 */
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303 #define _TPU_PRIORITY_LEVEL28 (0x0000000CUL) /* Level 28 */
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304 #define _TPU_PRIORITY_LEVEL29 (0x0000000DUL) /* Level 29 */
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305 #define _TPU_PRIORITY_LEVEL30 (0x0000000EUL) /* Level 30 */
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306 #define _TPU_PRIORITY_LEVEL31 (0x0000000FUL) /* Level 31 (lowest) */
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309 /***********************************************************************************************************************
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311 ***********************************************************************************************************************/
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312 /* TGRA value channel 9 */
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313 #define _TPU9_TCNTA_VALUE (0x0726U)
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315 /***********************************************************************************************************************
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316 Typedef definitions
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317 ***********************************************************************************************************************/
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319 /***********************************************************************************************************************
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321 ***********************************************************************************************************************/
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322 void R_TPU_Create(void);
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323 void R_TPU9_Start(void);
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324 void R_TPU9_Stop(void);
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326 /* Start user code for function. Do not edit comment generated here */
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327 /* End user code. Do not edit comment generated here */
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projects / freertos / blob