2 ; * FreeRTOS Kernel V10.3.0
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3 ; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 ; * this software and associated documentation files (the "Software"), to deal in
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7 ; * the Software without restriction, including without limitation the rights to
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8 ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 ; * the Software, and to permit persons to whom the Software is furnished to do so,
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10 ; * subject to the following conditions:
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12 ; * The above copyright notice and this permission notice shall be included in all
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13 ; * copies or substantial portions of the Software.
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15 ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 ; * http://www.FreeRTOS.org
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23 ; * http://aws.amazon.com/freertos
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25 ; * 1 tab == 4 spaces!
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28 ;-------------------------------------------------
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31 .ref ulRegTest1Counter
\r
33 .if (__TI_VFP_SUPPORT__)
\r
34 .ref vPortTaskUsesFPU
\r
35 .endif ;__TI_VFP_SUPPORT__
\r
41 .if (__TI_VFP_SUPPORT__)
\r
42 ; Let the port layer know that this task needs its FPU context saving.
\r
46 ; Fill each general purpose register with a known value.
\r
62 .if (__TI_VFP_SUPPORT__)
\r
63 ; Fill each FPU register with a known value.
\r
88 .if (__TI_VFP_SUPPORT__)
\r
89 ; Check all the VFP registers still contain the values set above.
\r
90 ; First save registers that are clobbered by the test.
\r
95 bne reg1_error_loopf
\r
97 bne reg1_error_loopf
\r
100 bne reg1_error_loopf
\r
102 bne reg1_error_loopf
\r
105 bne reg1_error_loopf
\r
107 bne reg1_error_loopf
\r
110 bne reg1_error_loopf
\r
112 bne reg1_error_loopf
\r
115 bne reg1_error_loopf
\r
117 bne reg1_error_loopf
\r
120 bne reg1_error_loopf
\r
122 bne reg1_error_loopf
\r
125 bne reg1_error_loopf
\r
127 bne reg1_error_loopf
\r
130 bne reg1_error_loopf
\r
132 bne reg1_error_loopf
\r
135 bne reg1_error_loopf
\r
137 bne reg1_error_loopf
\r
140 bne reg1_error_loopf
\r
142 bne reg1_error_loopf
\r
145 bne reg1_error_loopf
\r
147 bne reg1_error_loopf
\r
150 bne reg1_error_loopf
\r
152 bne reg1_error_loopf
\r
155 bne reg1_error_loopf
\r
157 bne reg1_error_loopf
\r
160 bne reg1_error_loopf
\r
162 bne reg1_error_loopf
\r
165 bne reg1_error_loopf
\r
167 bne reg1_error_loopf
\r
170 bne reg1_error_loopf
\r
172 bne reg1_error_loopf
\r
174 ; Restore the registers that were clobbered by the test.
\r
177 ; VFP register test passed. Jump to the core register test.
\r
181 ; If this line is hit then a VFP register value was found to be
\r
187 .endif ;__TI_VFP_SUPPORT__
\r
189 ; Test each general purpose register to check that it still contains the
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190 ; expected known value, jumping to vRegTestError1 if any register contains
\r
191 ; an unexpected value.
\r
221 ; This task is still running without jumping to vRegTestError1, so increment
\r
222 ; the loop counter so the check task knows the task is running error free.
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223 stmfd sp!, { r0-r1 }
\r
224 ldr r0, Count1Const
\r
228 ldmfd sp!, { r0-r1 }
\r
230 ; Loop again, performing the same tests.
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233 Count1Const .word ulRegTest1Counter
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239 ;-------------------------------------------------
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242 .ref ulRegTest2Counter
\r
247 .if (__TI_VFP_SUPPORT__)
\r
248 ; Let the port layer know that this task needs its FPU context saving.
\r
249 BL vPortTaskUsesFPU
\r
252 ; Fill each general purpose register with a known value.
\r
253 mov r0, #0xFF000000
\r
254 mov r1, #0x11000000
\r
255 mov r2, #0x22000000
\r
256 mov r3, #0x33000000
\r
257 mov r4, #0x44000000
\r
258 mov r5, #0x55000000
\r
259 mov r6, #0x66000000
\r
260 mov r7, #0x77000000
\r
261 mov r8, #0x88000000
\r
262 mov r9, #0x99000000
\r
263 mov r10, #0xAA000000
\r
264 mov r11, #0xBB000000
\r
265 mov r12, #0xCC000000
\r
266 mov r14, #0xEE000000
\r
268 .if (__TI_VFP_SUPPORT__)
\r
270 ; Fill each FPU register with a known value.
\r
291 .if (__TI_VFP_SUPPORT__)
\r
292 ; Check all the VFP registers still contain the values set above.
\r
293 ; First save registers that are clobbered by the test.
\r
297 cmp r0, #0xFF000000
\r
298 bne reg2_error_loopf
\r
299 cmp r1, #0x11000000
\r
300 bne reg2_error_loopf
\r
302 cmp r0, #0x22000000
\r
303 bne reg2_error_loopf
\r
304 cmp r1, #0x33000000
\r
305 bne reg2_error_loopf
\r
307 cmp r0, #0x44000000
\r
308 bne reg2_error_loopf
\r
309 cmp r1, #0x55000000
\r
310 bne reg2_error_loopf
\r
312 cmp r0, #0x66000000
\r
313 bne reg2_error_loopf
\r
314 cmp r1, #0x77000000
\r
315 bne reg2_error_loopf
\r
317 cmp r0, #0x88000000
\r
318 bne reg2_error_loopf
\r
319 cmp r1, #0x99000000
\r
320 bne reg2_error_loopf
\r
322 cmp r0, #0xAA000000
\r
323 bne reg2_error_loopf
\r
324 cmp r1, #0xBB000000
\r
325 bne reg2_error_loopf
\r
327 cmp r0, #0xFF000000
\r
328 bne reg2_error_loopf
\r
329 cmp r1, #0x11000000
\r
330 bne reg2_error_loopf
\r
332 cmp r0, #0x22000000
\r
333 bne reg2_error_loopf
\r
334 cmp r1, #0x33000000
\r
335 bne reg2_error_loopf
\r
337 cmp r0, #0x44000000
\r
338 bne reg2_error_loopf
\r
339 cmp r1, #0x55000000
\r
340 bne reg2_error_loopf
\r
342 cmp r0, #0x66000000
\r
343 bne reg2_error_loopf
\r
344 cmp r1, #0x77000000
\r
345 bne reg2_error_loopf
\r
347 cmp r0, #0x88000000
\r
348 bne reg2_error_loopf
\r
349 cmp r1, #0x99000000
\r
350 bne reg2_error_loopf
\r
352 cmp r0, #0xAA000000
\r
353 bne reg2_error_loopf
\r
354 cmp r1, #0xBB000000
\r
355 bne reg2_error_loopf
\r
357 cmp r0, #0xFF000000
\r
358 bne reg2_error_loopf
\r
359 cmp r1, #0x11000000
\r
360 bne reg2_error_loopf
\r
362 cmp r0, #0x22000000
\r
363 bne reg2_error_loopf
\r
364 cmp r1, #0x33000000
\r
365 bne reg2_error_loopf
\r
367 cmp r0, #0x44000000
\r
368 bne reg2_error_loopf
\r
369 cmp r1, #0x55000000
\r
370 bne reg2_error_loopf
\r
372 cmp r0, #0x66000000
\r
373 bne reg2_error_loopf
\r
374 cmp r1, #0x77000000
\r
375 bne reg2_error_loopf
\r
377 ; Restore the registers that were clobbered by the test.
\r
380 ; VFP register test passed. Jump to the core register test.
\r
384 ; If this line is hit then a VFP register value was found to be
\r
390 .endif ;__TI_VFP_SUPPORT__
\r
392 ; Test each general purpose register to check that it still contains the
\r
393 ; expected known value, jumping to vRegTestError2 if any register contains
\r
394 ; an unexpected value.
\r
395 cmp r0, #0xFF000000
\r
397 cmp r1, #0x11000000
\r
399 cmp r2, #0x22000000
\r
401 cmp r3, #0x33000000
\r
403 cmp r4, #0x44000000
\r
405 cmp r5, #0x55000000
\r
407 cmp r6, #0x66000000
\r
409 cmp r7, #0x77000000
\r
411 cmp r8, #0x88000000
\r
413 cmp r9, #0x99000000
\r
415 cmp r10, #0xAA000000
\r
417 cmp r11, #0xBB000000
\r
419 cmp r12, #0xCC000000
\r
421 cmp r14, #0xEE000000
\r
424 ; This task is still running without jumping to vRegTestError2, so increment
\r
425 ; the loop counter so the check task knows the task is running error free.
\r
426 stmfd sp!, { r0-r1 }
\r
427 ldr r0, Count2Const
\r
431 ldmfd sp!, { r0-r1 }
\r
433 ; Loop again, performing the same tests.
\r
436 Count2Const .word ulRegTest2Counter
\r
441 ;-------------------------------------------------
\r