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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
  28 * in advertising or otherwise to promote the sale, use or other dealings in
  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32
  33 /*****************************************************************************/
  34 /**
  35 *
  36 * @file xcsudma.c
  37 * @addtogroup csudma_v1_0
  38 * @{
  39 *
  40 * This file contains the implementation of the interface functions for CSU_DMA
  41 * driver. Refer to the header file xcsudma.h for more detailed information.
  42 *
  43 * <pre>
  44 * MODIFICATION HISTORY:
  45 *
  46 * Ver   Who     Date     Changes
  47 * ----- ------  -------- ---------------------------------------------------
  48 * 1.0   vnsld   22/10/14 First release
  49 * 1.1   adk     10/05/16 Fixed CR#951040 race condition in the recv path when
  50 *                        source and destination points to the same buffer.
  51 * </pre>
  52 *
  53 ******************************************************************************/
  54
  55 /***************************** Include Files *********************************/
  56
  57 #include "xcsudma.h"
  58
  59 /************************** Function Prototypes ******************************/
  60
  61
  62 /************************** Function Definitions *****************************/
  63
  64 /*****************************************************************************/
  65 /**
  66 *
  67 * This function initializes an CSU_DMA core. This function must be called
  68 * prior to using an CSU_DMA core. Initialization of an CSU_DMA includes setting
  69 * up the instance data and ensuring the hardware is in a quiescent state.
  70 *
  71 * @param        InstancePtr is a pointer to the XCsuDma instance.
  72 * @param        CfgPtr is a reference to a structure containing information
  73 *               about a specific XCsuDma instance.
  74 * @param        EffectiveAddr is the device base address in the virtual memory
  75 *               address space. The caller is responsible for keeping the
  76 *               address mapping from EffectiveAddr to the device physical
  77 *               base address unchanged once this function is invoked.
  78 *               Unexpected errors may occur if the address mapping changes
  79 *               after this function is called. If address translation is not
  80 *               used, pass in the physical address instead.
  81 *
  82 * @return
  83 *               - XST_SUCCESS if initialization was successful.
  84 *
  85 * @note         None.
  86 *
  87 ******************************************************************************/
  88 s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr,
  89                         u32 EffectiveAddr)
  90 {
  91
  92         /* Verify arguments. */
  93         Xil_AssertNonvoid(InstancePtr != NULL);
  94         Xil_AssertNonvoid(CfgPtr != NULL);
  95         Xil_AssertNonvoid(EffectiveAddr != ((u32)0x0));
  96
  97         /* Setup the instance */
  98         (void)memcpy((void *)&(InstancePtr->Config), (const void *)CfgPtr,
  99                                                 sizeof(XCsuDma_Config));
 100         InstancePtr->Config.BaseAddress = EffectiveAddr;
 101
 102         XCsuDma_Reset();
 103
 104         InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY);
 105
 106         return (XST_SUCCESS);
 107
 108 }
 109
 110 /*****************************************************************************/
 111 /**
 112 *
 113 * This function sets the starting address and amount(size) of the data to be
 114 * transfered from/to the memory through the AXI interface.
 115 *
 116 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 117 * @param        Channel represents the type of channel either it is Source or
 118 *               Destination.
 119 *               Source channel      - XCSUDMA_SRC_CHANNEL
 120 *               Destination Channel - XCSUDMA_DST_CHANNEL
 121 * @param        Addr is a 64 bit variable which holds the starting address of
 122 *               data which needs to write into the memory(DST) (or read from
 123 *               the memory(SRC)).
 124 * @param        Size is a 32 bit variable which represents the number of 4 byte
 125 *               words needs to be transfered from starting address.
 126 * @param        EnDataLast is to trigger an end of message. It will enable or
 127 *               disable data_inp_last signal to stream interface when current
 128 *               command is completed. It is applicable only to source channel
 129 *               and neglected for destination channel.
 130 *               -       1 - Asserts data_inp_last signal.
 131 *               -       0 - data_inp_last will not be asserted.
 132 *
 133 * @return       None.
 134 *
 135 * @note         Data_inp_last signal is asserted simultaneously with the
 136 *               data_inp_valid signal associated with the final 32-bit word
 137 *               transfer.
 138 *
 139 ******************************************************************************/
 140 void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 141                                         UINTPTR Addr, u32 Size, u8 EnDataLast)
 142 {
 143         /* Verify arguments */
 144         Xil_AssertVoid(InstancePtr != NULL);
 145         Xil_AssertVoid(((Addr) & (u64)(XCSUDMA_ADDR_LSB_MASK)) == (u64)0x00);
 146         Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 147                                         (Channel == (XCSUDMA_DST_CHANNEL)));
 148         Xil_AssertVoid(Size <= (u32)(XCSUDMA_SIZE_MAX));
 149         Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
 150
 151         /* Flushing cache memory */
 152         if (Channel == (XCSUDMA_SRC_CHANNEL)) {
 153                 Xil_DCacheFlushRange(Addr, Size << (u32)(XCSUDMA_SIZE_SHIFT));
 154         }
 155         /* Invalidating cache memory */
 156         else {
 157 #if defined(__aarch64__)
 158                 Xil_DCacheInvalidateRange(Addr, Size <<
 159                                         (u32)(XCSUDMA_SIZE_SHIFT));
 160 #else
 161                 Xil_DCacheFlushRange(Addr, Size << (u32)(XCSUDMA_SIZE_SHIFT));
 162 #endif
 163         }
 164
 165         XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 166                 ((u32)(XCSUDMA_ADDR_OFFSET) +
 167                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 168                                 ((u32)(Addr) & (u32)(XCSUDMA_ADDR_MASK)));
 169
 170         XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 171                 ((u32)(XCSUDMA_ADDR_MSB_OFFSET) +
 172                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 173                 (((u64)Addr >> (u32)(XCSUDMA_MSB_ADDR_SHIFT)) &
 174                                         (u32)(XCSUDMA_MSB_ADDR_MASK)));
 175
 176         if (EnDataLast == (u8)(XCSUDMA_LAST_WORD_MASK)) {
 177                 XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 178                         ((u32)(XCSUDMA_SIZE_OFFSET) +
 179                                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 180                         ((Size << (u32)(XCSUDMA_SIZE_SHIFT)) |
 181                                         (u32)(XCSUDMA_LAST_WORD_MASK)));
 182         }
 183         else {
 184                 XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 185                         ((u32)(XCSUDMA_SIZE_OFFSET) +
 186                                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 187                                 (Size << (u32)(XCSUDMA_SIZE_SHIFT)));
 188         }
 189 }
 190
 191 /*****************************************************************************/
 192 /**
 193 *
 194 * This function returns the current address location of the memory, from where
 195 * it has to read the data(SRC) or the location where it has to write the data
 196 * (DST) based on the channel selection.
 197 *
 198 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 199 * @param        Channel represents the type of channel either it is Source or
 200 *               Destination.
 201 *               Source channel      - XCSUDMA_SRC_CHANNEL
 202 *               Destination Channel - XCSUDMA_DST_CHANNEL
 203 *
 204 * @return       Address is a 64 bit variable which holds the current address.
 205 *               - From this location data has to be read(SRC)
 206 *               - At this location data has to be written(DST)
 207 *
 208 * @note         None.
 209 *
 210 ******************************************************************************/
 211 u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
 212 {
 213         u64 FullAddr;
 214
 215         /* Verify arguments */
 216         Xil_AssertNonvoid(InstancePtr != NULL);
 217         Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 218                                         (Channel == (XCSUDMA_DST_CHANNEL)));
 219
 220         FullAddr = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 221                                 ((u32)(XCSUDMA_ADDR_OFFSET) +
 222                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
 223
 224         FullAddr |= (u64)((u64)XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 225                         ((u32)(XCSUDMA_ADDR_MSB_OFFSET) +
 226                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) <<
 227                                 (u64)(XCSUDMA_MSB_ADDR_SHIFT));
 228
 229         return FullAddr;
 230 }
 231
 232 /*****************************************************************************/
 233 /**
 234 *
 235 * This function returns the size of the data yet to be transfered from memory
 236 * to CSU_DMA or CSU_DMA to memory based on the channel selection.
 237 *
 238 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 239 * @param        Channel represents the type of channel either it is Source or
 240 *               Destination.
 241 *               Source channel      - XCSUDMA_SRC_CHANNEL
 242 *               Destination Channel - XCSUDMA_DST_CHANNEL
 243 *
 244 * @return       Size is amount of data yet to be transfered.
 245 *
 246 * @note         None.
 247 *
 248 ******************************************************************************/
 249 u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
 250 {
 251         u32 Size;
 252
 253         /* Verify arguments. */
 254         Xil_AssertNonvoid(InstancePtr != NULL);
 255         Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 256                                         (Channel == (XCSUDMA_DST_CHANNEL)));
 257
 258         Size = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 259                 ((u32)(XCSUDMA_SIZE_OFFSET) +
 260                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) >>
 261                                         (u32)(XCSUDMA_SIZE_SHIFT);
 262
 263         return Size;
 264 }
 265
 266 /*****************************************************************************/
 267 /**
 268 *
 269 * This function pause the Channel data tranfer to/from memory or to/from stream
 270 * based on pause type.
 271 *
 272 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 273 * @param        Channel represents the type of channel either it is Source or
 274 *               Destination.
 275 *               Source channel      - XCSUDMA_SRC_CHANNEL
 276 *               Destination Channel - XCSUDMA_DST_CHANNEL
 277 * @param        Type is type of the pause to be enabled.
 278 *               - XCSUDMA_PAUSE_MEMORY(0) - Pause memory
 279 *                       - SRC Stops issuing of new read commands to memory.
 280 *                       - DST Stops issuing of new write commands to memory.
 281 *               - XCSUDMA_PAUSE_STREAM(1) - Pause stream
 282 *                       - SRC Stops transfer of data from FIFO to Stream.
 283 *                       - DST Stops transfer of data from stream to FIFO.
 284 *
 285 * @return       None.
 286 *
 287 * @note         None.
 288 *
 289 ******************************************************************************/
 290 void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 291                                                 XCsuDma_PauseType Type)
 292 {
 293         /* Verify arguments. */
 294         Xil_AssertVoid(InstancePtr != NULL);
 295         Xil_AssertVoid((Type == (XCSUDMA_PAUSE_MEMORY)) ||
 296                                 (Type == (XCSUDMA_PAUSE_STREAM)));
 297         Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 298                                         (Channel == (XCSUDMA_DST_CHANNEL)));
 299         Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
 300
 301         /* Pause Memory Read/Write/Stream operations */
 302         if (Type == (XCSUDMA_PAUSE_MEMORY)) {
 303                 XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 304                         ((u32)(XCSUDMA_CTRL_OFFSET) +
 305                                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 306                         (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 307                                 ((u32)(XCSUDMA_CTRL_OFFSET) +
 308                                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) |
 309                                         (u32)(XCSUDMA_CTRL_PAUSE_MEM_MASK)));
 310         }
 311         if (Type == (XCSUDMA_PAUSE_STREAM)) {
 312                 XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 313                         ((u32)(XCSUDMA_CTRL_OFFSET) +
 314                                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 315                         (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 316                                 ((u32)(XCSUDMA_CTRL_OFFSET) +
 317                                 (Channel * (u32)XCSUDMA_OFFSET_DIFF))) |
 318                                 (u32)(XCSUDMA_CTRL_PAUSE_STRM_MASK)));
 319         }
 320 }
 321
 322 /*****************************************************************************/
 323 /**
 324 *
 325 * This functions checks whether Channel's memory or stream is paused or not
 326 * based on the given pause type.
 327 *
 328 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 329 * @param        Channel represents the type of channel either it is Source or
 330 *               Destination.
 331 *               Source channel      - XCSUDMA_SRC_CHANNEL
 332 *               Destination Channel - XCSUDMA_DST_CHANNEL
 333 * @param        Type is type of the pause which needs to be checked.
 334 *               - XCSUDMA_PAUSE_MEMORY(0) - Pause memory
 335 *                       - SRC Stops issuing of new read commands to memory.
 336 *                       - DST Stops issuing of new write commands to memory.
 337 *               - XCSUDMA_PAUSE_STREAM(1) - Pause stream
 338 *                       - SRC Stops transfer of data from FIFO to Stream.
 339 *                       - DST Stops transfer of data from stream to FIFO.
 340 *
 341 * @return       Returns the pause status.
 342 *               - TRUE if it is in paused state.
 343 *               - FALSE if it is not in pause state.
 344 *
 345 * @note         None.
 346 *
 347 ******************************************************************************/
 348 s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 349                 XCsuDma_PauseType Type)
 350 {
 351
 352         u32 Data;
 353         s32 PauseState;
 354
 355         /* Verify arguments. */
 356         Xil_AssertNonvoid(InstancePtr != NULL);
 357         Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 358                                         (Channel == (XCSUDMA_DST_CHANNEL)));
 359         Xil_AssertNonvoid((Type == (XCSUDMA_PAUSE_MEMORY)) ||
 360                                         (Type == (XCSUDMA_PAUSE_STREAM)));
 361
 362         Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 363                         ((u32)(XCSUDMA_CTRL_OFFSET) +
 364                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
 365
 366         /* To know Pause condition of Memory Read/Write/Stream operations */
 367         if (Type == (XCSUDMA_PAUSE_MEMORY)) {
 368                 if ((Data & (u32)(XCSUDMA_CTRL_PAUSE_MEM_MASK)) ==
 369                                                                 (u32)0x00) {
 370                         PauseState = (s32)(FALSE);
 371                 }
 372                 else {
 373                         PauseState = (s32)(TRUE);
 374                 }
 375         }
 376         else {
 377                 if ((Data & (u32)(XCSUDMA_CTRL_PAUSE_STRM_MASK)) ==
 378                                                                 (u32)0x00) {
 379                                 PauseState = (s32)(FALSE);
 380                 }
 381                 else {
 382                         PauseState = (s32)(TRUE);
 383                 }
 384         }
 385
 386         return (s32)PauseState;
 387
 388 }
 389
 390 /*****************************************************************************/
 391 /**
 392 *
 393 * This function resumes the channel if it is in paused state and continues
 394 * where it has left or no effect if it is not in paused state, based on the
 395 * type of pause.
 396 *
 397 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 398 * @param        Channel represents the type of channel either it is Source or
 399 *               Destination.
 400 *               Source channel      - XCSUDMA_SRC_CHANNEL
 401 *               Destination Channel - XCSUDMA_DST_CHANNEL
 402 * @param        Type is type of the pause to be Resume if it is in pause
 403 *               state.
 404 *               - XCSUDMA_PAUSE_MEMORY(0) - Pause memory
 405 *                       - SRC Stops issuing of new read commands to memory.
 406 *                       - DST Stops issuing of new write commands to memory.
 407 *               - XCSUDMA_PAUSE_STREAM(1) - Pause stream
 408 *                       - SRC Stops transfer of data from FIFO to Stream.
 409 *                       - DST Stops transfer of data from stream to FIFO.
 410 *
 411 * @return       None.
 412 *
 413 * @note         None.
 414 *
 415 ******************************************************************************/
 416 void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 417                 XCsuDma_PauseType Type)
 418 {
 419         u32 Data;
 420         /* Verify arguments. */
 421         Xil_AssertVoid(InstancePtr != NULL);
 422         Xil_AssertVoid((Type == (XCSUDMA_PAUSE_MEMORY)) ||
 423                         (Type == (XCSUDMA_PAUSE_STREAM)));
 424         Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 425                                         (Channel == (XCSUDMA_DST_CHANNEL)));
 426         Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
 427
 428         Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 429                         ((u32)(XCSUDMA_CTRL_OFFSET) +
 430                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
 431
 432         if (Type == (XCSUDMA_PAUSE_MEMORY)) {
 433                 XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 434                 ((u32)(XCSUDMA_CTRL_OFFSET) +
 435                 ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
 436                 (Data &
 437                                 (~(XCSUDMA_CTRL_PAUSE_MEM_MASK))));
 438         }
 439         if (Type == (XCSUDMA_PAUSE_STREAM)) {
 440                 XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 441                 ((u32)(XCSUDMA_CTRL_OFFSET) +
 442                 (((u32)Channel) * (u32)(XCSUDMA_OFFSET_DIFF))),
 443                         ( Data &
 444                         (~(XCSUDMA_CTRL_PAUSE_STRM_MASK))));
 445         }
 446 }
 447
 448 /*****************************************************************************/
 449 /**
 450 *
 451 * This function returns the sum of all the data read from AXI memory. It is
 452 * valid only one we use CSU_DMA source channel.
 453 *
 454 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 455 *
 456 * @return       Returns the sum of all the data read from memory.
 457 *
 458 * @note         Before start of the transfer need to clear this register to get
 459 *               correct sum otherwise it adds to previous value which results
 460 *               to wrong output.
 461 *               Valid only for source channel
 462 *
 463 ******************************************************************************/
 464 u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr)
 465 {
 466         u32 ChkSum;
 467
 468         /* Verify arguments. */
 469         Xil_AssertNonvoid(InstancePtr != NULL);
 470         Xil_AssertNonvoid(InstancePtr->IsReady ==
 471                                 (u32)(XIL_COMPONENT_IS_READY));
 472
 473         ChkSum = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 474                                                 (u32)(XCSUDMA_CRC_OFFSET));
 475
 476         return ChkSum;
 477
 478 }
 479 /*****************************************************************************/
 480 /**
 481 *
 482 * This function clears the check sum of the data read from AXI memory. It is
 483 * valid only for CSU_DMA source channel.
 484 *
 485 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 486 *
 487 * @return       Returns the sum of all the data read from memory.
 488 *
 489 * @note         Before start of the transfer need to clear this register to get
 490 *               correct sum otherwise it adds to previous value which results
 491 *               to wrong output.
 492 *
 493 ******************************************************************************/
 494 void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr)
 495 {
 496
 497         /* Verify arguments. */
 498         Xil_AssertVoid(InstancePtr != NULL);
 499
 500         XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 501                 (u32)(XCSUDMA_CRC_OFFSET), (u32)(XCSUDMA_CRC_RESET_MASK));
 502 }
 503
 504 /*****************************************************************************/
 505 /**
 506 * This function cofigures all the values of CSU_DMA's Channels with the values
 507 * of updated XCsuDma_Configure structure.
 508 *
 509 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 510 * @param        Channel represents the type of channel either it is Source or
 511 *               Destination.
 512 *               Source channel      - XCSUDMA_SRC_CHANNEL
 513 *               Destination Channel - XCSUDMA_DST_CHANNEL
 514 * @param        ConfigurValues is a pointer to the structure XCsuDma_Configure
 515 *               whose values are used to configure CSU_DMA core.
 516 *               - SssFifoThesh   When the DST FIFO level >= this value,
 517 *                 the SSS interface signal, "data_out_fifo_level_hit" will be
 518 *                 asserted. This mechanism can be used by the SSS to flow
 519 *                 control data that is being looped back from the SRC DMA.
 520 *                       - Range is (0x10 to 0x7A) threshold is 17 to 123
 521 *                       entries.
 522 *                       - It is valid only for DST CSU_DMA IP.
 523 *               - ApbErr          When accessed to invalid APB the resulting
 524 *                 pslerr will be
 525 *                       - 0 - 1'b0
 526 *                       - 1 - 1'b1
 527 *               - EndianType      Type of endianness
 528 *                       - 0 doesn't change order
 529 *                       - 1 will flip the order.
 530 *               - AxiBurstType....Type of the burst
 531 *                       - 0 will issue INCR type burst
 532 *                       - 1 will issue FIXED type burst
 533 *               - TimeoutValue    Time out value for timers
 534 *                       - 0x000 to 0xFFE are valid inputs
 535 *                       - 0xFFF clears both timers
 536 *               - FifoThresh......Programmed watermark value
 537 *                       - Range is 0x00 to 0x80 (0 to 128 entries).
 538 *               - Acache         Sets the AXI CACHE bits on the AXI Write/Read
 539 *               channel.
 540 *                       - Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1]
 541 *                         for DST channel are always 1, we need to configure
 542 *                         remaining 3 signal support
 543 *                         (Bufferable, Read allocate and Write allocate).
 544 *                       Valid inputs are:
 545 *                       - 0x000 - Cacheable, but do not allocate
 546 *                       - 0x001 - Cacheable and bufferable, but do not allocate
 547 *                       - 0x010 - Cacheable write-through, allocate on reads
 548 *                                 only
 549 *                       - 0x011 - Cacheable write-back, allocate on reads only
 550 *                       - 0x100 - Cacheable write-through, allocate on writes
 551 *                                 only
 552 *                       - 0x101 - Cacheable write-back, allocate on writes only
 553 *                       - 0x110 - Cacheable write-through, allocate on both
 554 *                                 reads and writes
 555 *                       - 0x111 - Cacheable write-back, allocate on both reads
 556 *                                 and writes
 557 *               - RouteBit        To select route
 558 *                       - 0 : Command will be routed normally
 559 *                       - 1 : Command will be routed to APU's cache controller
 560 *               - TimeoutEn       To enable or disable time out counters
 561 *                       - 0 : The 2 Timeout counters are disabled
 562 *                       - 1 : The 2 Timeout counters are enabled
 563 *               - TimeoutPre      Set the prescaler value for the timeout in
 564 *               clk (~2.5ns) cycles
 565 *                       - Range is 0x000(Prescaler enables timer every cycles)
 566 *                         to 0xFFF(Prescaler enables timer every 4096 cycles)
 567 *               - MaxOutCmds      Controls the maximumum number of outstanding
 568 *               AXI read commands issued.
 569 *                       - Range is 0x0(Up to 1 Outstanding Read command
 570 *                         allowed) to 0x8 (Up to 9 Outstanding Read
 571 *                         command allowed)
 572 *
 573 * @return       None.
 574 *
 575 * @note         To use timers timeout value Timeout enable field should be
 576 *               enabled.
 577 *
 578 ******************************************************************************/
 579 void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 580                                         XCsuDma_Configure *ConfigurValues)
 581 {
 582         u32 Data;
 583
 584         /* Verify arguments. */
 585         Xil_AssertVoid(InstancePtr != NULL);
 586         Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
 587         Xil_AssertVoid(ConfigurValues != NULL);
 588         Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 589                                 (Channel == (XCSUDMA_DST_CHANNEL)));
 590         Xil_AssertVoid(XCsuDma_IsBusy(InstancePtr, Channel) != (s32)(TRUE));
 591
 592         Data = (((ConfigurValues->EndianType <<
 593                         (u32)(XCSUDMA_CTRL_ENDIAN_SHIFT)) &
 594                         (u32)(XCSUDMA_CTRL_ENDIAN_MASK)) |
 595                 ((ConfigurValues->ApbErr <<
 596                         (u32)(XCSUDMA_CTRL_APB_ERR_SHIFT)) &
 597                         (u32)(XCSUDMA_CTRL_APB_ERR_MASK)) |
 598                 ((ConfigurValues->AxiBurstType <<
 599                         (u32)(XCSUDMA_CTRL_BURST_SHIFT)) &
 600                         (u32)(XCSUDMA_CTRL_BURST_MASK)) |
 601                 ((ConfigurValues->TimeoutValue <<
 602                         (u32)(XCSUDMA_CTRL_TIMEOUT_SHIFT)) &
 603                         (u32)(XCSUDMA_CTRL_TIMEOUT_MASK)) |
 604                 ((ConfigurValues->FifoThresh <<
 605                         (u32)(XCSUDMA_CTRL_FIFO_THRESH_SHIFT)) &
 606                         (u32)(XCSUDMA_CTRL_FIFO_THRESH_MASK)));
 607         if(Channel == XCSUDMA_DST_CHANNEL) {
 608                 Data = Data | (u32)((ConfigurValues->SssFifoThesh <<
 609                                 (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT)) &
 610                                 (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK));
 611         }
 612
 613         XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 614                         ((u32)(XCSUDMA_CTRL_OFFSET) +
 615                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data);
 616
 617         Data = (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 618                         ((u32)(XCSUDMA_CTRL2_OFFSET) +
 619                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) &
 620                                 (u32)(XCSUDMA_CTRL2_RESERVED_MASK));
 621         Data |= (((ConfigurValues->Acache <<
 622                         (u32)(XCSUDMA_CTRL2_ACACHE_SHIFT)) &
 623                         (u32)(XCSUDMA_CTRL2_ACACHE_MASK)) |
 624                 ((ConfigurValues->RouteBit <<
 625                         (u32)(XCSUDMA_CTRL2_ROUTE_SHIFT)) &
 626                         (u32)(XCSUDMA_CTRL2_ROUTE_MASK)) |
 627                 ((ConfigurValues->TimeoutEn <<
 628                         (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT)) &
 629                         (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_MASK)) |
 630                 ((ConfigurValues->TimeoutPre <<
 631                         (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT)) &
 632                         (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_MASK)) |
 633                 ((ConfigurValues->MaxOutCmds) &
 634                         (u32)(XCSUDMA_CTRL2_MAXCMDS_MASK)));
 635
 636         XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
 637                 ((u32)(XCSUDMA_CTRL2_OFFSET) +
 638                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data);
 639 }
 640
 641 /*****************************************************************************/
 642 /**
 643 *
 644 * This function updates XCsuDma_Configure structure members with the cofigured
 645 * values of CSU_DMA's Channel.
 646 *
 647 * @param        InstancePtr is a pointer to XCsuDma instance to be worked on.
 648 * @param        Channel represents the type of channel either it is Source or
 649 *               Destination.
 650 *               Source channel      - XCSUDMA_SRC_CHANNEL
 651 *               Destination Channel - XCSUDMA_DST_CHANNEL
 652 * @param        ConfigurValues is a pointer to the structure XCsuDma_Configure
 653 *               whose members are updated with configurations of CSU_DMA core.
 654 *               - SssFifoThesh   When the DST FIFO level >= this value,
 655 *                 the SSS interface signal, "data_out_fifo_level_hit" will be
 656 *                 asserted. This mechanism can be used by the SSS to flow
 657 *                 control data that is being looped back from the SRC DMA.
 658 *                       - Range is (0x10 to 0x7A) threshold is 17 to 123
 659 *                       entries.
 660 *                       - It is valid only for DST CSU_DMA IP.
 661 *               - ApbErr          When accessed to invalid APB the resulting
 662 *                 pslerr will be
 663 *                       - 0 - 1'b0
 664 *                       - 1 - 1'b1
 665 *               - EndianType      Type of endianness
 666 *                       - 0 doesn't change order
 667 *                       - 1 will flip the order.
 668 *               - AxiBurstType....Type of the burst
 669 *                       - 0 will issue INCR type burst
 670 *                       - 1 will issue FIXED type burst
 671 *               - TimeoutValue    Time out value for timers
 672 *                       - 0x000 to 0xFFE are valid inputs
 673 *                       - 0xFFF clears both timers
 674 *               - FifoThresh......Programmed watermark value
 675 *                       - Range is 0x00 to 0x80 (0 to 128 entries).
 676 *               - Acache         Sets the AXI CACHE bits on the AXI Write/Read
 677 *               channel.
 678 *                       - Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1]
 679 *                         for DST channel are always 1, we need to configure
 680 *                         remaining 3 signal support
 681 *                         (Bufferable, Read allocate and Write allocate).
 682 *                       Valid inputs are:
 683 *                       - 0x000 - Cacheable, but do not allocate
 684 *                       - 0x001 - Cacheable and bufferable, but do not allocate
 685 *                       - 0x010 - Cacheable write-through, allocate on reads
 686 *                                 only
 687 *                       - 0x011 - Cacheable write-back, allocate on reads only
 688 *                       - 0x100 - Cacheable write-through, allocate on writes
 689 *                                 only
 690 *                       - 0x101 - Cacheable write-back, allocate on writes only
 691 *                       - 0x110 - Cacheable write-through, allocate on both
 692 *                                 reads and writes
 693 *                       - 0x111 - Cacheable write-back, allocate on both reads
 694 *                                 and writes
 695 *               - RouteBit        To select route
 696 *                       - 0 : Command will be routed based normally
 697 *                       - 1 : Command will be routed to APU's cache controller
 698 *               - TimeoutEn       To enable or disable time out counters
 699 *                       - 0 : The 2 Timeout counters are disabled
 700 *                       - 1 : The 2 Timeout counters are enabled
 701 *               - TimeoutPre      Set the prescaler value for the timeout in
 702 *               clk (~2.5ns) cycles
 703 *                       - Range is 0x000(Prescaler enables timer every cycles)
 704 *                        to 0xFFF(Prescaler enables timer every 4096 cycles)
 705 *               - MaxOutCmds      Controls the maximumum number of outstanding
 706 *               AXI read commands issued.
 707 *                       - Range is 0x0(Up to 1 Outstanding Read command
 708 *                       allowed) to 0x8 (Up to 9 Outstanding Read command
 709 *                       allowed)
 710 *
 711 * @return       None.
 712 *
 713 * @note         None.
 714 *
 715 ******************************************************************************/
 716 void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 717                                 XCsuDma_Configure *ConfigurValues)
 718 {
 719         u32 Data;
 720
 721         /* Verify arguments. */
 722         Xil_AssertVoid(InstancePtr != NULL);
 723         Xil_AssertVoid(ConfigurValues != NULL);
 724         Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
 725                                 (Channel == (XCSUDMA_DST_CHANNEL)));
 726
 727         Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 728                 ((u32)(XCSUDMA_CTRL_OFFSET) +
 729                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
 730
 731         if (Channel == (XCSUDMA_DST_CHANNEL)) {
 732                 ConfigurValues->SssFifoThesh =
 733                         (u8)((Data &
 734                                 (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK)) >>
 735                                 (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT));
 736         }
 737         ConfigurValues->ApbErr =
 738                 (u8)((Data & (u32)(XCSUDMA_CTRL_APB_ERR_MASK)) >>
 739                                 (u32)(XCSUDMA_CTRL_APB_ERR_SHIFT));
 740         ConfigurValues->EndianType =
 741                 (u8)((Data & (u32)(XCSUDMA_CTRL_ENDIAN_MASK)) >>
 742                                 (u32)(XCSUDMA_CTRL_ENDIAN_SHIFT));
 743         ConfigurValues->AxiBurstType =
 744                 (u8)((Data & (u32)(XCSUDMA_CTRL_BURST_MASK)) >>
 745                                 (u32)(XCSUDMA_CTRL_BURST_SHIFT));
 746         ConfigurValues->TimeoutValue =
 747                 ((Data & (u32)(XCSUDMA_CTRL_TIMEOUT_MASK)) >>
 748                                 (u32)(XCSUDMA_CTRL_TIMEOUT_SHIFT));
 749         ConfigurValues->FifoThresh =
 750                 (u8)((Data & (u32)(XCSUDMA_CTRL_FIFO_THRESH_MASK)) >>
 751                                 (u32)(XCSUDMA_CTRL_FIFO_THRESH_SHIFT));
 752
 753         Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
 754                         ((u32)(XCSUDMA_CTRL2_OFFSET) +
 755                         ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
 756
 757         ConfigurValues->Acache =
 758                         (u8)((Data & (u32)(XCSUDMA_CTRL2_ACACHE_MASK)) >>
 759                                         (u32)(XCSUDMA_CTRL2_ACACHE_SHIFT));
 760         ConfigurValues->RouteBit =
 761                         (u8)((Data & (u32)(XCSUDMA_CTRL2_ROUTE_MASK)) >>
 762                                         (u32)(XCSUDMA_CTRL2_ROUTE_SHIFT));
 763         ConfigurValues->TimeoutEn =
 764                         (u8)((Data & (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_MASK)) >>
 765                                 (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT));
 766         ConfigurValues->TimeoutPre =
 767                         (u16)((Data & (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_MASK)) >>
 768                                 (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT));
 769         ConfigurValues->MaxOutCmds =
 770                         (u8)((Data & (u32)(XCSUDMA_CTRL2_MAXCMDS_MASK)));
 771
 772 }
 773 /** @} */