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31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup gpiops_v3_3
39 * This header file contains the identifiers and basic driver functions (or
40 * macros) that can be used to access the device. Other driver functions
41 * are defined in xgpiops.h.
44 * MODIFICATION HISTORY:
46 * Ver Who Date Changes
47 * ----- ---- -------- -------------------------------------------------
48 * 1.00a sv 01/15/10 First Release
49 * 1.02a hk 08/22/13 Added low level reset API function prototype and
50 * related constant definitions
51 * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
52 * 3.1 kvn 04/13/15 Corrected reset values of banks.
55 ******************************************************************************/
56 #ifndef XGPIOPS_HW_H /* prevent circular inclusions */
57 #define XGPIOPS_HW_H /* by using protection macros */
61 #endif /* __cplusplus */
63 /***************************** Include Files *********************************/
65 #include "xil_types.h"
66 #include "xil_assert.h"
69 /************************** Constant Definitions *****************************/
71 /** @name Register offsets for the GPIO. Each register is 32 bits.
74 #define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */
75 #define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */
76 #define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */
77 #define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */
78 #define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */
79 #define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */
80 #define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */
81 #define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */
82 #define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/
83 #define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */
84 #define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */
85 #define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */
86 #define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */
89 /** @name Register offsets for each Bank.
92 #define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */
93 #define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */
94 #define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */
97 /* For backwards compatibility */
98 #define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40
100 /** @name Interrupt type reset values for each bank
103 #ifdef XPAR_PSU_GPIO_0_BASEADDR
104 #define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
105 #define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU
106 #define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU
108 #define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /* Resets specific to Zynq */
109 #define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU
110 #define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU
113 #define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /* Reset common to both platforms */
114 #define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
115 #define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU
118 /**************************** Type Definitions *******************************/
120 /***************** Macros (Inline Functions) Definitions *********************/
122 /****************************************************************************/
125 * This macro reads the given register.
127 * @param BaseAddr is the base address of the device.
128 * @param RegOffset is the register offset to be read.
130 * @return The 32-bit value of the register
134 *****************************************************************************/
135 #define XGpioPs_ReadReg(BaseAddr, RegOffset) \
136 Xil_In32((BaseAddr) + (u32)(RegOffset))
138 /****************************************************************************/
141 * This macro writes to the given register.
143 * @param BaseAddr is the base address of the device.
144 * @param RegOffset is the offset of the register to be written.
145 * @param Data is the 32-bit value to write to the register.
151 *****************************************************************************/
152 #define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
153 Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
155 /************************** Function Prototypes ******************************/
157 void XGpioPs_ResetHw(u32 BaseAddress);
161 #endif /* __cplusplus */
163 #endif /* XGPIOPS_HW_H */