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31 ******************************************************************************/
32 /*****************************************************************************/
35 * @file xgpiops_intr.c
36 * @addtogroup gpiops_v3_3
39 * This file contains functions related to GPIO interrupt handling.
42 * MODIFICATION HISTORY:
44 * Ver Who Date Changes
45 * ----- ---- -------- -----------------------------------------------
46 * 1.00a sv 01/18/10 First Release
47 * 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
48 * passed to API's. CR# 822636
49 * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
50 * 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
53 ******************************************************************************/
55 /***************************** Include Files *********************************/
59 /************************** Constant Definitions *****************************/
61 /**************************** Type Definitions *******************************/
63 /***************** Macros (Inline Functions) Definitions *********************/
65 /************************** Variable Definitions *****************************/
67 /************************** Function Prototypes ******************************/
69 void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
71 /****************************************************************************/
74 * This function enables the interrupts for the specified pins in the specified
77 * @param InstancePtr is a pointer to the XGpioPs instance.
78 * @param Bank is the bank number of the GPIO to operate on.
79 * Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
80 * @param Mask is the bit mask of the pins for which interrupts are to
81 * be enabled. Bit positions of 1 will be enabled. Bit positions
82 * of 0 will keep the previous setting.
88 *****************************************************************************/
89 void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
91 Xil_AssertVoid(InstancePtr != NULL);
92 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
93 Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
95 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
96 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
97 XGPIOPS_INTEN_OFFSET, Mask);
100 /****************************************************************************/
103 * This function enables the interrupt for the specified pin.
105 * @param InstancePtr is a pointer to the XGpioPs instance.
106 * @param Pin is the pin number for which the interrupt is to be enabled.
107 * Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
113 *****************************************************************************/
114 void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin)
120 Xil_AssertVoid(InstancePtr != NULL);
121 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
122 Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
124 /* Get the Bank number and Pin number within the bank. */
125 XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
127 IntrReg = ((u32)1 << (u32)PinNumber);
128 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
129 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
130 XGPIOPS_INTEN_OFFSET, IntrReg);
133 /****************************************************************************/
136 * This function disables the interrupts for the specified pins in the specified
139 * @param InstancePtr is a pointer to the XGpioPs instance.
140 * @param Bank is the bank number of the GPIO to operate on.
141 * Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
142 * @param Mask is the bit mask of the pins for which interrupts are
143 * to be disabled. Bit positions of 1 will be disabled. Bit
144 * positions of 0 will keep the previous setting.
150 *****************************************************************************/
151 void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
153 Xil_AssertVoid(InstancePtr != NULL);
154 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
155 Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
157 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
158 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
159 XGPIOPS_INTDIS_OFFSET, Mask);
162 /****************************************************************************/
165 * This function disables the interrupts for the specified pin.
167 * @param InstancePtr is a pointer to the XGpioPs instance.
168 * @param Pin is the pin number for which the interrupt is to be disabled.
169 * Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
175 *****************************************************************************/
176 void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin)
182 Xil_AssertVoid(InstancePtr != NULL);
183 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
184 Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
186 /* Get the Bank number and Pin number within the bank. */
187 XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
189 IntrReg = ((u32)1 << (u32)PinNumber);
190 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
191 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
192 XGPIOPS_INTDIS_OFFSET, IntrReg);
195 /****************************************************************************/
198 * This function returns the interrupt enable status for a bank.
200 * @param InstancePtr is a pointer to the XGpioPs instance.
201 * @param Bank is the bank number of the GPIO to operate on.
202 * Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
204 * @return Enabled interrupt(s) in a 32-bit format. Bit positions with 1
205 * indicate that the interrupt for that pin is enabled, bit
206 * positions with 0 indicate that the interrupt for that pin is
211 *****************************************************************************/
212 u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank)
216 Xil_AssertNonvoid(InstancePtr != NULL);
217 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
218 Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
220 IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
221 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
222 XGPIOPS_INTMASK_OFFSET);
226 /****************************************************************************/
229 * This function returns whether interrupts are enabled for the specified pin.
231 * @param InstancePtr is a pointer to the XGpioPs instance.
232 * @param Pin is the pin number for which the interrupt enable status
234 * Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
237 * - TRUE if the interrupt is enabled.
238 * - FALSE if the interrupt is disabled.
242 *****************************************************************************/
243 u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin)
249 Xil_AssertNonvoid(InstancePtr != NULL);
250 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
251 Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
253 /* Get the Bank number and Pin number within the bank. */
254 XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
256 IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
257 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
258 XGPIOPS_INTMASK_OFFSET);
260 return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? FALSE : TRUE);
263 /****************************************************************************/
266 * This function returns interrupt status read from Interrupt Status Register.
268 * @param InstancePtr is a pointer to the XGpioPs instance.
269 * @param Bank is the bank number of the GPIO to operate on.
270 * Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
272 * @return The value read from Interrupt Status Register.
276 *****************************************************************************/
277 u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank)
279 Xil_AssertNonvoid(InstancePtr != NULL);
280 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
281 Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
283 return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
284 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
285 XGPIOPS_INTSTS_OFFSET);
288 /****************************************************************************/
291 * This function returns interrupt enable status of the specified pin.
293 * @param InstancePtr is a pointer to the XGpioPs instance.
294 * @param Pin is the pin number for which the interrupt enable status
296 * Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
299 * - TRUE if the interrupt has occurred.
300 * - FALSE if the interrupt has not occurred.
304 *****************************************************************************/
305 u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin)
311 Xil_AssertNonvoid(InstancePtr != NULL);
312 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
313 Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
315 /* Get the Bank number and Pin number within the bank. */
316 XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
318 IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
319 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
320 XGPIOPS_INTSTS_OFFSET);
322 return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? TRUE : FALSE);
325 /****************************************************************************/
328 * This function clears pending interrupt(s) with the provided mask. This
329 * function should be called after the software has serviced the interrupts
332 * @param InstancePtr is a pointer to the XGpioPs instance.
333 * @param Bank is the bank number of the GPIO to operate on.
334 * Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
335 * @param Mask is the mask of the interrupts to be cleared. Bit positions
336 * of 1 will be cleared. Bit positions of 0 will not change the
337 * previous interrupt status.
341 *****************************************************************************/
342 void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
344 Xil_AssertVoid(InstancePtr != NULL);
345 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
346 Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
348 /* Clear the currently pending interrupts. */
349 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
350 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
351 XGPIOPS_INTSTS_OFFSET, Mask);
354 /****************************************************************************/
357 * This function clears the specified pending interrupt. This function should be
358 * called after the software has serviced the interrupts that are pending.
360 * @param InstancePtr is a pointer to the XGpioPs instance.
361 * @param Pin is the pin number for which the interrupt status is to be
362 * cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
366 *****************************************************************************/
367 void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin)
373 Xil_AssertVoid(InstancePtr != NULL);
374 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
375 Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
377 /* Get the Bank number and Pin number within the bank. */
378 XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
380 /* Clear the specified pending interrupts. */
381 IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
382 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
383 XGPIOPS_INTSTS_OFFSET);
385 IntrReg &= ((u32)1 << PinNumber);
386 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
387 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
388 XGPIOPS_INTSTS_OFFSET, IntrReg);
391 /****************************************************************************/
394 * This function is used for setting the Interrupt Type, Interrupt Polarity and
395 * Interrupt On Any for the specified GPIO Bank pins.
397 * @param InstancePtr is a pointer to an XGpioPs instance.
398 * @param Bank is the bank number of the GPIO to operate on.
399 * Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
400 * @param IntrType is the 32 bit mask of the interrupt type.
401 * 0 means Level Sensitive and 1 means Edge Sensitive.
402 * @param IntrPolarity is the 32 bit mask of the interrupt polarity.
403 * 0 means Active Low or Falling Edge and 1 means Active High or
405 * @param IntrOnAny is the 32 bit mask of the interrupt trigger for
406 * edge triggered interrupts. 0 means trigger on single edge using
407 * the configured interrupt polarity and 1 means trigger on both
412 * @note This function is used for setting the interrupt related
413 * properties of all the pins in the specified bank. The previous
414 * state of the pins is not maintained.
415 * To change the Interrupt properties of a single GPIO pin, use the
416 * function XGpioPs_SetPinIntrType().
418 *****************************************************************************/
419 void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
420 u32 IntrPolarity, u32 IntrOnAny)
422 Xil_AssertVoid(InstancePtr != NULL);
423 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
424 Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
426 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
427 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
428 XGPIOPS_INTTYPE_OFFSET, IntrType);
430 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
431 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
432 XGPIOPS_INTPOL_OFFSET, IntrPolarity);
434 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
435 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
436 XGPIOPS_INTANY_OFFSET, IntrOnAny);
439 /****************************************************************************/
442 * This function is used for getting the Interrupt Type, Interrupt Polarity and
443 * Interrupt On Any for the specified GPIO Bank pins.
445 * @param InstancePtr is a pointer to an XGpioPs instance.
446 * @param Bank is the bank number of the GPIO to operate on.
447 * Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
448 * @param IntrType returns the 32 bit mask of the interrupt type.
449 * 0 means Level Sensitive and 1 means Edge Sensitive.
450 * @param IntrPolarity returns the 32 bit mask of the interrupt
451 * polarity. 0 means Active Low or Falling Edge and 1 means
452 * Active High or Rising Edge.
453 * @param IntrOnAny returns the 32 bit mask of the interrupt trigger for
454 * edge triggered interrupts. 0 means trigger on single edge using
455 * the configured interrupt polarity and 1 means trigger on both
462 *****************************************************************************/
463 void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
464 u32 *IntrPolarity, u32 *IntrOnAny)
467 Xil_AssertVoid(InstancePtr != NULL);
468 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
469 Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
471 *IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
472 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
473 XGPIOPS_INTTYPE_OFFSET);
475 *IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
476 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
477 XGPIOPS_INTPOL_OFFSET);
479 *IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
480 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
481 XGPIOPS_INTANY_OFFSET);
484 /****************************************************************************/
487 * This function is used for setting the IRQ Type of a single GPIO pin.
489 * @param InstancePtr is a pointer to an XGpioPs instance.
490 * @param Pin is the pin number whose IRQ type is to be set.
491 * Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
492 * @param IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
493 * defined in xgpiops.h to specify the IRQ type.
499 *****************************************************************************/
500 void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
508 Xil_AssertVoid(InstancePtr != NULL);
509 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
510 Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
511 Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
513 /* Get the Bank number and Pin number within the bank. */
514 XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
516 IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
517 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
518 XGPIOPS_INTTYPE_OFFSET);
520 IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
521 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
522 XGPIOPS_INTPOL_OFFSET);
524 IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
525 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
526 XGPIOPS_INTANY_OFFSET);
529 case XGPIOPS_IRQ_TYPE_EDGE_RISING:
530 IntrTypeReg |= ((u32)1 << (u32)PinNumber);
531 IntrPolReg |= ((u32)1 << (u32)PinNumber);
532 IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
534 case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
535 IntrTypeReg |= ((u32)1 << (u32)PinNumber);
536 IntrPolReg &= ~((u32)1 << (u32)PinNumber);
537 IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
539 case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
540 IntrTypeReg |= ((u32)1 << (u32)PinNumber);
541 IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
543 case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
544 IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
545 IntrPolReg |= ((u32)1 << (u32)PinNumber);
547 case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
548 IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
549 IntrPolReg &= ~((u32)1 << (u32)PinNumber);
552 /**< Default statement is added for MISRA C compliance. */
556 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
557 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
558 XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
560 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
561 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
562 XGPIOPS_INTPOL_OFFSET, IntrPolReg);
564 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
565 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
566 XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
569 /****************************************************************************/
572 * This function returns the IRQ Type of a given GPIO pin.
574 * @param InstancePtr is a pointer to an XGpioPs instance.
575 * @param Pin is the pin number whose IRQ type is to be obtained.
576 * Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
580 * @note Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
581 * returned by this function.
583 *****************************************************************************/
584 u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin)
593 Xil_AssertNonvoid(InstancePtr != NULL);
594 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
595 Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
597 /* Get the Bank number and Pin number within the bank. */
598 XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
600 IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
601 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
602 XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber);
604 if (IntrType == ((u32)1 << PinNumber)) {
606 IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
607 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
608 XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber);
610 IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
611 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
612 XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
615 if (IntrOnAny == ((u32)1 << PinNumber)) {
616 IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
617 } else if (IntrPol == ((u32)1 << PinNumber)) {
618 IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
620 IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
624 IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
625 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
626 XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
628 if (IntrPol == ((u32)1 << PinNumber)) {
629 IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
631 IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
638 /*****************************************************************************/
641 * This function sets the status callback function. The callback function is
642 * called by the XGpioPs_IntrHandler when an interrupt occurs.
644 * @param InstancePtr is a pointer to the XGpioPs instance.
645 * @param CallBackRef is the upper layer callback reference passed back
646 * when the callback function is invoked.
647 * @param FuncPtr is the pointer to the callback function.
652 * @note The handler is called within interrupt context, so it should do
653 * its work quickly and queue potentially time-consuming work to a
656 ******************************************************************************/
657 void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
658 XGpioPs_Handler FuncPointer)
660 Xil_AssertVoid(InstancePtr != NULL);
661 Xil_AssertVoid(FuncPointer != NULL);
662 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
664 InstancePtr->Handler = FuncPointer;
665 InstancePtr->CallBackRef = CallBackRef;
668 /*****************************************************************************/
671 * This function is the interrupt handler for GPIO interrupts.It checks the
672 * interrupt status registers of all the banks to determine the actual bank in
673 * which an interrupt has been triggered. It then calls the upper layer callback
674 * handler set by the function XGpioPs_SetBankHandler(). The callback is called
677 * @param InstancePtr is a pointer to the XGpioPs instance.
681 * @note This function does not save and restore the processor context
682 * such that the user must provide this processing.
684 ******************************************************************************/
685 void XGpioPs_IntrHandler(XGpioPs *InstancePtr)
691 Xil_AssertVoid(InstancePtr != NULL);
692 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
694 for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) {
695 IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
696 if (IntrStatus != (u32)0) {
697 IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,
699 XGpioPs_IntrClear((XGpioPs *)InstancePtr, Bank,
700 (IntrStatus & IntrEnabled));
701 InstancePtr->Handler(InstancePtr->
703 (IntrStatus & IntrEnabled));
708 /*****************************************************************************/
711 * This is a stub for the status callback. The stub is here in case the upper
712 * layers do not set the handler.
714 * @param CallBackRef is a pointer to the upper layer callback reference
715 * @param Bank is the GPIO Bank in which an interrupt occurred.
716 * @param Status is the Interrupt status of the GPIO bank.
722 ******************************************************************************/
723 void StubHandler(void *CallBackRef, u32 Bank, u32 Status)
729 Xil_AssertVoidAlways();