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32 /*****************************************************************************/
35 * @file xiicps_options.c
36 * @addtogroup iicps_v3_0
39 * Contains functions for the configuration of the XIccPs driver.
42 * MODIFICATION HISTORY:
44 * Ver Who Date Changes
45 * ----- ------ -------- -----------------------------------------------
46 * 1.00a drg/jz 01/30/10 First release
47 * 1.02a sg 08/29/12 Updated the logic to arrive at the best divisors
48 * to achieve I2C clock with minimum error.
49 * This is a fix for CR #674195
50 * 1.03a hk 05/04/13 Initialized BestDivA and BestDivB to 0.
51 * This is fix for CR#704398 to remove warning.
52 * 2.0 hk 03/07/14 Limited frequency set when 100KHz or 400KHz is
53 * selected. This is a hardware limitation. CR#779290.
54 * 2.1 hk 04/24/14 Fix for CR# 761060 - provision for repeated start.
55 * 2.3 sk 10/07/14 Repeated start feature removed.
56 * 3.0 sk 12/06/14 Implemented Repeated start feature.
57 * 01/31/15 Modified the code according to MISRAC 2012 Compliant.
58 * 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
62 ******************************************************************************/
64 /***************************** Include Files *********************************/
68 /************************** Constant Definitions *****************************/
71 /**************************** Type Definitions *******************************/
74 /***************** Macros (Inline Functions) Definitions *********************/
77 /************************** Function Prototypes ******************************/
80 /************************** Variable Definitions *****************************/
82 * Create the table of options which are processed to get/set the device
83 * options. These options are table driven to allow easy maintenance and
84 * expansion of the options.
91 static OptionsMap OptionsTable[] = {
92 {XIICPS_7_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
93 {XIICPS_10_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
94 {XIICPS_SLAVE_MON_OPTION, XIICPS_CR_SLVMON_MASK},
95 {XIICPS_REP_START_OPTION, XIICPS_CR_HOLD_MASK},
98 #define XIICPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))
100 /*****************************************************************************/
103 * This function sets the options for the IIC device driver. The options control
104 * how the device behaves relative to the IIC bus. The device must be idle
105 * rather than busy transferring data before setting these device options.
107 * @param InstancePtr is a pointer to the XIicPs instance.
108 * @param Options contains the specified options to be set. This is a bit
109 * mask where a 1 means to turn the option on. One or more bit
110 * values may be contained in the mask. See the bit definitions
111 * named XIICPS_*_OPTION in xiicps.h.
114 * - XST_SUCCESS if options are successfully set.
115 * - XST_DEVICE_IS_STARTED if the device is currently transferring
116 * data. The transfer must complete or be aborted before setting
121 ******************************************************************************/
122 s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
126 u32 OptionsVar = Options;
128 Xil_AssertNonvoid(InstancePtr != NULL);
129 Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
131 ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
135 * If repeated start option is requested, set the flag.
136 * The hold bit in CR will be written by driver when the next transfer
139 if ((OptionsVar & (u32)XIICPS_REP_START_OPTION) != (u32)0 ) {
140 InstancePtr->IsRepeatedStart = 1;
141 OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
145 * Loop through the options table, turning the option on.
147 for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
148 if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
150 * 10-bit option is specially treated, because it is
151 * using the 7-bit option, so turning it on means
152 * turning 7-bit option off.
154 if ((OptionsTable[Index].Option &
155 XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
157 ControlReg &= ~OptionsTable[Index].Mask;
160 ControlReg |= OptionsTable[Index].Mask;
166 * Now write to the control register. Leave it to the upper layers
167 * to restart the device.
169 XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
173 * Keep a copy of what options this instance has.
175 InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
177 return (s32)XST_SUCCESS;
180 /*****************************************************************************/
183 * This function clears the options for the IIC device driver. The options
184 * control how the device behaves relative to the IIC bus. The device must be
185 * idle rather than busy transferring data before setting these device options.
187 * @param InstancePtr is a pointer to the XIicPs instance.
188 * @param Options contains the specified options to be cleared. This is a
189 * bit mask where a 1 means to turn the option off. One or more bit
190 * values may be contained in the mask. See the bit definitions
191 * named XIICPS_*_OPTION in xiicps.h.
194 * - XST_SUCCESS if options are successfully set.
195 * - XST_DEVICE_IS_STARTED if the device is currently transferring
196 * data. The transfer must complete or be aborted before setting
201 ******************************************************************************/
202 s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options)
206 u32 OptionsVar = Options;
208 Xil_AssertNonvoid(InstancePtr != NULL);
209 Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
211 ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
215 * If repeated start option is cleared, set the flag.
216 * The hold bit in CR will be cleared by driver when the
217 * following transfer ends.
219 if ((OptionsVar & XIICPS_REP_START_OPTION) != (u32)0x0U ) {
220 InstancePtr->IsRepeatedStart = 0;
221 OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
225 * Loop through the options table and clear the specified options.
227 for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
228 if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
231 * 10-bit option is specially treated, because it is
232 * using the 7-bit option, so clearing it means turning
235 if ((OptionsTable[Index].Option &
236 XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
239 ControlReg |= OptionsTable[Index].Mask;
243 ControlReg &= ~OptionsTable[Index].Mask;
250 * Now write the control register. Leave it to the upper layers
251 * to restart the device.
253 XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
257 * Keep a copy of what options this instance has.
259 InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
264 /*****************************************************************************/
267 * This function gets the options for the IIC device. The options control how
268 * the device behaves relative to the IIC bus.
270 * @param InstancePtr is a pointer to the XIicPs instance.
272 * @return 32 bit mask of the options, where a 1 means the option is on,
273 * and a 0 means to the option is off. One or more bit values may
274 * be contained in the mask. See the bit definitions named
275 * XIICPS_*_OPTION in the file xiicps.h.
279 ******************************************************************************/
280 u32 XIicPs_GetOptions(XIicPs *InstancePtr)
282 u32 OptionsFlag = 0U;
286 Xil_AssertNonvoid(InstancePtr != NULL);
287 Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
290 * Read control register to find which options are currently set.
292 ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
296 * Loop through the options table to determine which options are set.
298 for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
299 if ((ControlReg & OptionsTable[Index].Mask) != (u32)0x0U) {
300 OptionsFlag |= OptionsTable[Index].Option;
302 if ((ControlReg & XIICPS_CR_NEA_MASK) == (u32)0x0U) {
303 OptionsFlag |= XIICPS_10_BIT_ADDR_OPTION;
307 if (InstancePtr->IsRepeatedStart != 0 ) {
308 OptionsFlag |= XIICPS_REP_START_OPTION;
313 /*****************************************************************************/
316 * This function sets the serial clock rate for the IIC device. The device
317 * must be idle rather than busy transferring data before setting these device
320 * The data rate is set by values in the control register. The formula for
321 * determining the correct register values is:
322 * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
323 * See the hardware data sheet for a full explanation of setting the serial
326 * @param InstancePtr is a pointer to the XIicPs instance.
327 * @param FsclHz is the clock frequency in Hz. The two most common clock
328 * rates are 100KHz and 400KHz.
331 * - XST_SUCCESS if options are successfully set.
332 * - XST_DEVICE_IS_STARTED if the device is currently transferring
333 * data. The transfer must complete or be aborted before setting
335 * - XST_FAILURE if the Fscl frequency can not be set.
337 * @note The clock can not be faster than the input clock divide by 22.
339 ******************************************************************************/
340 s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
355 u32 FsclHzVar = FsclHz;
357 Xil_AssertNonvoid(InstancePtr != NULL);
358 Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
359 Xil_AssertNonvoid(FsclHzVar > 0U);
361 if (0U != XIicPs_In32((InstancePtr->Config.BaseAddress) +
362 XIICPS_TRANS_SIZE_OFFSET)) {
363 return (s32)XST_DEVICE_IS_STARTED;
367 * Assume Div_a is 0 and calculate (divisor_a+1) x (divisor_b+1).
369 Temp = (InstancePtr->Config.InputClockHz) / ((u32)22U * FsclHzVar);
372 * If the answer is negative or 0, the Fscl input is out of range.
374 if ((u32)(0U) == Temp) {
375 return (s32)XST_FAILURE;
379 * If frequency 400KHz is selected, 384.6KHz should be set.
380 * If frequency 100KHz is selected, 90KHz should be set.
381 * This is due to a hardware limitation.
383 if(FsclHzVar > (u32)384600U) {
384 FsclHzVar = (u32)384600U;
387 if((FsclHzVar <= (u32)100000U) && (FsclHzVar > (u32)90000U)) {
388 FsclHzVar = (u32)90000U;
392 * TempLimit helps in iterating over the consecutive value of Temp to
393 * find the closest clock rate achievable with divisors.
394 * Iterate over the next value only if fractional part is involved.
396 TempLimit = (((InstancePtr->Config.InputClockHz) %
397 ((u32)22 * FsclHzVar)) != (u32)0x0U) ?
398 Temp + (u32)1U : Temp;
399 BestError = FsclHzVar;
403 for ( ; Temp <= TempLimit ; Temp++)
405 LastError = FsclHzVar;
409 for (Div_b = 0U; Div_b < 64U; Div_b++) {
411 Div_a = Temp / (Div_b + 1U);
414 Div_a = Div_a - (u32)1U;
419 ActualFscl = (InstancePtr->Config.InputClockHz) /
420 (22U * (Div_a + 1U) * (Div_b + 1U));
422 if (ActualFscl > FsclHzVar){
423 CurrentError = (ActualFscl - FsclHzVar);}
425 CurrentError = (FsclHzVar - ActualFscl);}
427 if (LastError > CurrentError) {
430 LastError = CurrentError;
435 * Used to capture the best divisors.
437 if (LastError < BestError) {
438 BestError = LastError;
446 * Read the control register and mask the Divisors.
448 ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
449 (u32)XIICPS_CR_OFFSET);
450 ControlReg &= ~((u32)XIICPS_CR_DIV_A_MASK | (u32)XIICPS_CR_DIV_B_MASK);
451 ControlReg |= (BestDivA << XIICPS_CR_DIV_A_SHIFT) |
452 (BestDivB << XIICPS_CR_DIV_B_SHIFT);
454 XIicPs_WriteReg(InstancePtr->Config.BaseAddress, (u32)XIICPS_CR_OFFSET,
457 return (s32)XST_SUCCESS;
460 /*****************************************************************************/
463 * This function gets the serial clock rate for the IIC device. The device
464 * must be idle rather than busy transferring data before setting these device
467 * @param InstancePtr is a pointer to the XIicPs instance.
469 * @return The value of the IIC clock to the nearest Hz based on the
470 * control register settings. The actual value may not be exact to
471 * to integer math rounding errors.
475 ******************************************************************************/
476 u32 XIicPs_GetSClk(XIicPs *InstancePtr)
483 Xil_AssertNonvoid(InstancePtr != NULL);
484 Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
486 ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
489 Div_a = (ControlReg & XIICPS_CR_DIV_A_MASK) >> XIICPS_CR_DIV_A_SHIFT;
490 Div_b = (ControlReg & XIICPS_CR_DIV_B_MASK) >> XIICPS_CR_DIV_B_SHIFT;
492 ActualFscl = (InstancePtr->Config.InputClockHz) /
493 (22U * (Div_a + 1U) * (Div_b + 1U));