1 /******************************************************************************
3 * Copyright (C) 2014 Xilinx, Inc. All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 * Except as contained in this notice, the name of the Xilinx shall not be used
28 * in advertising or otherwise to promote the sale, use or other dealings in
29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup qspipsu_v1_0
40 * This is the header file for the implementation of QSPIPSU driver.
41 * Generic QSPI interface allows for communication to any QSPI slave device.
42 * GQSPI contains a GENFIFO into which the bus transfers required are to be
43 * pushed with appropriate configuration. The controller provides TX and RX
44 * FIFO's and a DMA to be used for RX transfers. The controller executes each
45 * GENFIFO entry noting the configuration and places data on the bus as required
47 * The different options in GENFIFO are as follows:
48 * IMM_DATA : Can be one byte of data to be transmitted, number of clocks or
49 * number of bytes in transfer.
50 * DATA_XFER : Indicates that data/clocks need to be transmitted or received.
51 * EXPONENT : e when 2^e bytes are involved in transfer.
52 * SPI_MODE : SPI/Dual SPI/Quad SPI
53 * CS : Lower or Upper CS or Both
54 * Bus : Lower or Upper Bus or Both
55 * TX : When selected, controller transmits data in IMM or fetches number of
56 * bytes mentioned form TX FIFO. If not selected, dummies are pumped.
57 * RX : When selected, controller receives and fills the RX FIFO/allows RX DMA
58 * of requested number of bytes. If not selected, RX data is discarded.
59 * Stripe : Byte stripe over lower and upper bus or not.
60 * Poll : Polls response to match for to a set value (used along with POLL_CFG
61 * registers) and then proceeds to next GENFIFO entry.
62 * This feature is not currently used in the driver.
64 * GENFIFO has manual and auto start options.
65 * All DMA requests need a 4-byte aligned destination address buffer and
66 * size of transfer should also be a multiple of 4.
67 * This driver supports DMA RX and IO RX.
70 * This driver uses the GQSPI controller with RX DMA. It supports both
71 * interrupt and polled transfers. Manual start of GENFIFO is used.
72 * XQspiPsu_CfgInitialize() initializes the instance variables.
73 * Additional setting can be done using SetOptions/ClearOptions functions
74 * and SelectSlave function.
77 * Polled or Interrupt transfers can be done. The transfer function needs the
78 * message(s) to be transmitted in the form of an array of type XQspiPsu_Msg.
79 * This is supposed to contain the byte count and any TX/RX buffers as required.
80 * Flags can be used indicate further information such as whether the message
81 * should be striped. The transfer functions form and write GENFIFO entries,
82 * check the status of the transfer and report back to the application
86 * MODIFICATION HISTORY:
88 * Ver Who Date Changes
89 * ----- --- -------- -----------------------------------------------.
90 * 1.0 hk 08/21/14 First release
91 * sk 03/13/15 Added IO mode support.
92 * hk 03/18/15 Switch to I/O mode before clearing RX FIFO.
93 * Clear and disbale DMA interrupts/status in abort.
94 * Use DMA DONE bit instead of BUSY as recommended.
95 * sk 04/24/15 Modified the code according to MISRAC-2012.
96 * sk 06/17/15 Removed NULL checks for Rx/Tx buffers. As
97 * writing/reading from 0x0 location is permitted.
98 * 1.1 sk 04/12/16 Added debug message prints.
99 * 1.2 nsk 07/01/16 Added LQSPI support
100 * Modified XQspiPsu_Select() macro in xqspipsu.h
101 * Added XQspiPsu_GetLqspiConfigReg() in xqspipsu.h
102 * Added required macros in xqspipsu_hw.h
103 * Modified XQspiPsu_SetOptions() to support
104 * LQSPI options and updated OptionsTable in
106 * rk 07/15/16 Added support for TapDelays at different frequencies.
107 * nsk 08/05/16 Added example support PollData and PollTimeout
108 * Added XQSPIPSU_MSG_FLAG_POLL macro in xqspipsu.h
109 * Added XQspiPsu_Create_PollConfigData and
110 * XQspiPsu_PollData() functions in xqspipsu.c
111 * 1.3 nsk 09/16/16 Update PollData and Polltimeout support for dual parallel
112 * configuration. Updated XQspiPsu_PollData() and
113 * XQspiPsu_Create_PollConfigData() functions in xqspipsu.c
114 * and also modified the polldata example
118 ******************************************************************************/
119 #ifndef XQSPIPSU_H_ /* prevent circular inclusions */
120 #define XQSPIPSU_H_ /* by using protection macros */
126 /***************************** Include Files *********************************/
129 #include "xqspipsu_hw.h"
130 #include "xil_cache.h"
132 /**************************** Type Definitions *******************************/
134 * The handler data type allows the user to define a callback function to
135 * handle the asynchronous processing for the QSPIPSU device. The application
136 * using this driver is expected to define a handler of this type to support
137 * interrupt driven mode. The handler executes in an interrupt context, so
138 * only minimal processing should be performed.
140 * @param CallBackRef is the callback reference passed in by the upper
141 * layer when setting the callback functions, and passed back to
142 * the upper layer when the callback is invoked. Its type is
143 * not important to the driver, so it is a void pointer.
144 * @param StatusEvent holds one or more status events that have occurred.
145 * See the XQspiPsu_SetStatusHandler() for details on the status
146 * events that can be passed in the callback.
147 * @param ByteCount indicates how many bytes of data were successfully
148 * transferred. This may be less than the number of bytes
149 * requested if the status event indicates an error.
151 typedef void (*XQspiPsu_StatusHandler) (void *CallBackRef, u32 StatusEvent,
155 * This typedef contains configuration information for a flash message.
170 * This typedef contains configuration information for the device.
173 u16 DeviceId; /**< Unique ID of device */
174 u32 BaseAddress; /**< Base address of the device */
175 u32 InputClockHz; /**< Input clock frequency */
176 u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
177 u8 BusWidth; /**< Bus width available on board */
181 * The XQspiPsu driver instance data. The user is required to allocate a
182 * variable of this type for every QSPIPSU device in the system. A pointer
183 * to a variable of this type is then passed to the driver API functions.
186 XQspiPsu_Config Config; /**< Configuration structure */
187 u32 IsReady; /**< Device is initialized and ready */
189 u8 *SendBufferPtr; /**< Buffer to send (state) */
190 u8 *RecvBufferPtr; /**< Buffer to receive (state) */
191 u8 *GenFifoBufferPtr; /**< Gen FIFO entries */
192 s32 TxBytes; /**< Number of bytes to transfer (state) */
193 s32 RxBytes; /**< Number of bytes left to transfer(state) */
194 s32 GenFifoEntries; /**< Number of Gen FIFO entries remaining */
195 u32 IsBusy; /**< A transfer is in progress (state) */
196 u32 ReadMode; /**< DMA or IO mode */
204 XQspiPsu_StatusHandler StatusHandler;
205 void *StatusRef; /**< Callback reference for status handler */
208 /***************** Macros (Inline Functions) Definitions *********************/
210 #define XQSPIPSU_READMODE_DMA 0x0U
211 #define XQSPIPSU_READMODE_IO 0x1U
213 #define XQSPIPSU_SELECT_FLASH_CS_LOWER 0x1U
214 #define XQSPIPSU_SELECT_FLASH_CS_UPPER 0x2U
215 #define XQSPIPSU_SELECT_FLASH_CS_BOTH 0x3U
217 #define XQSPIPSU_SELECT_FLASH_BUS_LOWER 0x1U
218 #define XQSPIPSU_SELECT_FLASH_BUS_UPPER 0x2U
219 #define XQSPIPSU_SELECT_FLASH_BUS_BOTH 0x3U
221 #define XQSPIPSU_SELECT_MODE_SPI 0x1U
222 #define XQSPIPSU_SELECT_MODE_DUALSPI 0x2U
223 #define XQSPIPSU_SELECT_MODE_QUADSPI 0x4U
225 #define XQSPIPSU_GENFIFO_CS_SETUP 0x05U
226 #define XQSPIPSU_GENFIFO_CS_HOLD 0x04U
228 #define XQSPIPSU_CLK_ACTIVE_LOW_OPTION 0x2U
229 #define XQSPIPSU_CLK_PHASE_1_OPTION 0x4U
230 #define XQSPIPSU_MANUAL_START_OPTION 0x8U
231 #define XQSPIPSU_LQSPI_MODE_OPTION 0x20U
233 #define XQSPIPSU_GENFIFO_EXP_START 0x100U
235 #define XQSPIPSU_DMA_BYTES_MAX 0x10000000U
237 #define XQSPIPSU_CLK_PRESCALE_2 0x00U
238 #define XQSPIPSU_CLK_PRESCALE_4 0x01U
239 #define XQSPIPSU_CLK_PRESCALE_8 0x02U
240 #define XQSPIPSU_CLK_PRESCALE_16 0x03U
241 #define XQSPIPSU_CLK_PRESCALE_32 0x04U
242 #define XQSPIPSU_CLK_PRESCALE_64 0x05U
243 #define XQSPIPSU_CLK_PRESCALE_128 0x06U
244 #define XQSPIPSU_CLK_PRESCALE_256 0x07U
245 #define XQSPIPSU_CR_PRESC_MAXIMUM 7U
247 #define XQSPIPSU_CONNECTION_MODE_SINGLE 0U
248 #define XQSPIPSU_CONNECTION_MODE_STACKED 1U
249 #define XQSPIPSU_CONNECTION_MODE_PARALLEL 2U
252 #define XQSPIPSU_FREQ_40MHZ 40000000
253 #define XQSPIPSU_FREQ_100MHZ 100000000
254 #define XQSPIPSU_FREQ_150MHZ 150000000
256 /* Add more flags as required */
257 #define XQSPIPSU_MSG_FLAG_STRIPE 0x1U
258 #define XQSPIPSU_MSG_FLAG_RX 0x2U
259 #define XQSPIPSU_MSG_FLAG_TX 0x4U
260 #define XQSPIPSU_MSG_FLAG_POLL 0x8U
262 #define XQspiPsu_Select(InstancePtr, Mask) XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, Mask)
264 #define XQspiPsu_Enable(InstancePtr) XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)
266 #define XQspiPsu_Disable(InstancePtr) XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, 0x0U)
268 #define XQspiPsu_GetLqspiConfigReg(InstancePtr) XQspiPsu_In32((XQSPIPS_BASEADDR) + XQSPIPSU_LQSPI_CR_OFFSET)
270 /************************** Function Prototypes ******************************/
272 /* Initialization and reset */
273 XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId);
274 s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
276 void XQspiPsu_Reset(XQspiPsu *InstancePtr);
277 void XQspiPsu_Abort(XQspiPsu *InstancePtr);
279 /* Transfer functions and handlers */
280 s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
282 s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
284 s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr);
285 void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef,
286 XQspiPsu_StatusHandler FuncPointer);
288 /* Configuration functions */
289 s32 XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler);
290 void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus);
291 s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options);
292 s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options);
293 u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr);
294 s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode);
301 #endif /* XQSPIPSU_H_ */