1 /******************************************************************************
3 * Copyright (C) 2014 Xilinx, Inc. All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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28 * in advertising or otherwise to promote the sale, use or other dealings in
29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup qspipsu_v1_0
39 * This file contains low level access funcitons using the base address
40 * directly without an instance.
43 * MODIFICATION HISTORY:
45 * Ver Who Date Changes
46 * ----- --- -------- -----------------------------------------------.
47 * 1.0 hk 08/21/14 First release
48 * hk 03/18/15 Add DMA status register masks required.
49 * sk 04/24/15 Modified the code according to MISRAC-2012.
50 * 1.2 nsk 07/01/16 Added LQSPI supported Masks
51 * rk 07/15/16 Added support for TapDelays at different frequencies.
55 ******************************************************************************/
56 #ifndef _XQSPIPSU_HW_H_ /* prevent circular inclusions */
57 #define _XQSPIPSU_HW_H_ /* by using protection macros */
63 /***************************** Include Files *********************************/
65 #include "xil_types.h"
66 #include "xil_assert.h"
68 #include "xparameters.h"
70 /************************** Constant Definitions *****************************/
75 #define XQSPIPS_BASEADDR 0XFF0F0000U
80 #define XQSPIPSU_BASEADDR 0xFF0F0100U
81 #define XQSPIPSU_OFFSET 0x100U
84 * Register: XQSPIPS_EN_REG
86 #define XQSPIPS_EN_REG ( ( XQSPIPS_BASEADDR ) + 0X00000014U )
88 #define XQSPIPS_EN_SHIFT 0
89 #define XQSPIPS_EN_WIDTH 1
90 #define XQSPIPS_EN_MASK 0X00000001U
93 * Register: XQSPIPSU_CFG
95 #define XQSPIPSU_CFG_OFFSET 0X00000000U
96 #define XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U
98 #define XQSPIPSU_CFG_MODE_EN_SHIFT 30
99 #define XQSPIPSU_CFG_MODE_EN_WIDTH 2
100 #define XQSPIPSU_CFG_MODE_EN_MASK 0XC0000000U
101 #define XQSPIPSU_CFG_MODE_EN_DMA_MASK 0X80000000U
103 #define XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT 29
104 #define XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH 1
105 #define XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK 0X20000000U
107 #define XQSPIPSU_CFG_START_GEN_FIFO_SHIFT 28
108 #define XQSPIPSU_CFG_START_GEN_FIFO_WIDTH 1
109 #define XQSPIPSU_CFG_START_GEN_FIFO_MASK 0X10000000U
111 #define XQSPIPSU_CFG_ENDIAN_SHIFT 26
112 #define XQSPIPSU_CFG_ENDIAN_WIDTH 1
113 #define XQSPIPSU_CFG_ENDIAN_MASK 0X04000000U
115 #define XQSPIPSU_CFG_EN_POLL_TO_SHIFT 20
116 #define XQSPIPSU_CFG_EN_POLL_TO_WIDTH 1
117 #define XQSPIPSU_CFG_EN_POLL_TO_MASK 0X00100000U
119 #define XQSPIPSU_CFG_WP_HOLD_SHIFT 19
120 #define XQSPIPSU_CFG_WP_HOLD_WIDTH 1
121 #define XQSPIPSU_CFG_WP_HOLD_MASK 0X00080000U
123 #define XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT 3
124 #define XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH 3
125 #define XQSPIPSU_CFG_BAUD_RATE_DIV_MASK 0X00000038U
127 #define XQSPIPSU_CFG_CLK_PHA_SHIFT 2
128 #define XQSPIPSU_CFG_CLK_PHA_WIDTH 1
129 #define XQSPIPSU_CFG_CLK_PHA_MASK 0X00000004U
131 #define XQSPIPSU_CFG_CLK_POL_SHIFT 1
132 #define XQSPIPSU_CFG_CLK_POL_WIDTH 1
133 #define XQSPIPSU_CFG_CLK_POL_MASK 0X00000002U
136 * Register: XQSPIPSU_CFG
138 #define XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U
139 #define XQSPIPSU_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
140 #define XQSPIPSU_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
141 #define XQSPIPSU_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Seperate memory bus */
142 #define XQSPIPSU_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
143 #define XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK 0x01000000 /**< Upper memory page */
144 #define XQSPIPSU_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
145 #define XQSPIPSU_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
146 #define XQSPIPSU_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
148 #define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
149 #define XQSPIPS_LQSPI_CR_RST_STATE 0x80000003 /**< Default LQSPI CR value */
150 #define XQSPIPS_LQSPI_CFG_RST_STATE 0x800238C1 /**< Default LQSPI CFG value */
152 * Register: XQSPIPSU_ISR
154 #define XQSPIPSU_ISR_OFFSET 0X00000004U
156 #define XQSPIPSU_ISR_RXEMPTY_SHIFT 11
157 #define XQSPIPSU_ISR_RXEMPTY_WIDTH 1
158 #define XQSPIPSU_ISR_RXEMPTY_MASK 0X00000800U
160 #define XQSPIPSU_ISR_GENFIFOFULL_SHIFT 10
161 #define XQSPIPSU_ISR_GENFIFOFULL_WIDTH 1
162 #define XQSPIPSU_ISR_GENFIFOFULL_MASK 0X00000400U
164 #define XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT 9
165 #define XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH 1
166 #define XQSPIPSU_ISR_GENFIFONOT_FULL_MASK 0X00000200U
168 #define XQSPIPSU_ISR_TXEMPTY_SHIFT 8
169 #define XQSPIPSU_ISR_TXEMPTY_WIDTH 1
170 #define XQSPIPSU_ISR_TXEMPTY_MASK 0X00000100U
172 #define XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT 7
173 #define XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH 1
174 #define XQSPIPSU_ISR_GENFIFOEMPTY_MASK 0X00000080U
176 #define XQSPIPSU_ISR_RXFULL_SHIFT 5
177 #define XQSPIPSU_ISR_RXFULL_WIDTH 1
178 #define XQSPIPSU_ISR_RXFULL_MASK 0X00000020U
180 #define XQSPIPSU_ISR_RXNEMPTY_SHIFT 4
181 #define XQSPIPSU_ISR_RXNEMPTY_WIDTH 1
182 #define XQSPIPSU_ISR_RXNEMPTY_MASK 0X00000010U
184 #define XQSPIPSU_ISR_TXFULL_SHIFT 3
185 #define XQSPIPSU_ISR_TXFULL_WIDTH 1
186 #define XQSPIPSU_ISR_TXFULL_MASK 0X00000008U
188 #define XQSPIPSU_ISR_TXNOT_FULL_SHIFT 2
189 #define XQSPIPSU_ISR_TXNOT_FULL_WIDTH 1
190 #define XQSPIPSU_ISR_TXNOT_FULL_MASK 0X00000004U
192 #define XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT 1
193 #define XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH 1
194 #define XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK 0X00000002U
196 #define XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002U
199 * Register: XQSPIPSU_IER
201 #define XQSPIPSU_IER_OFFSET 0X00000008U
203 #define XQSPIPSU_IER_RXEMPTY_SHIFT 11
204 #define XQSPIPSU_IER_RXEMPTY_WIDTH 1
205 #define XQSPIPSU_IER_RXEMPTY_MASK 0X00000800U
207 #define XQSPIPSU_IER_GENFIFOFULL_SHIFT 10
208 #define XQSPIPSU_IER_GENFIFOFULL_WIDTH 1
209 #define XQSPIPSU_IER_GENFIFOFULL_MASK 0X00000400U
211 #define XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT 9
212 #define XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH 1
213 #define XQSPIPSU_IER_GENFIFONOT_FULL_MASK 0X00000200U
215 #define XQSPIPSU_IER_TXEMPTY_SHIFT 8
216 #define XQSPIPSU_IER_TXEMPTY_WIDTH 1
217 #define XQSPIPSU_IER_TXEMPTY_MASK 0X00000100U
219 #define XQSPIPSU_IER_GENFIFOEMPTY_SHIFT 7
220 #define XQSPIPSU_IER_GENFIFOEMPTY_WIDTH 1
221 #define XQSPIPSU_IER_GENFIFOEMPTY_MASK 0X00000080U
223 #define XQSPIPSU_IER_RXFULL_SHIFT 5
224 #define XQSPIPSU_IER_RXFULL_WIDTH 1
225 #define XQSPIPSU_IER_RXFULL_MASK 0X00000020U
227 #define XQSPIPSU_IER_RXNEMPTY_SHIFT 4
228 #define XQSPIPSU_IER_RXNEMPTY_WIDTH 1
229 #define XQSPIPSU_IER_RXNEMPTY_MASK 0X00000010U
231 #define XQSPIPSU_IER_TXFULL_SHIFT 3
232 #define XQSPIPSU_IER_TXFULL_WIDTH 1
233 #define XQSPIPSU_IER_TXFULL_MASK 0X00000008U
235 #define XQSPIPSU_IER_TXNOT_FULL_SHIFT 2
236 #define XQSPIPSU_IER_TXNOT_FULL_WIDTH 1
237 #define XQSPIPSU_IER_TXNOT_FULL_MASK 0X00000004U
239 #define XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT 1
240 #define XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH 1
241 #define XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK 0X00000002U
244 * Register: XQSPIPSU_IDR
246 #define XQSPIPSU_IDR_OFFSET 0X0000000CU
248 #define XQSPIPSU_IDR_RXEMPTY_SHIFT 11
249 #define XQSPIPSU_IDR_RXEMPTY_WIDTH 1
250 #define XQSPIPSU_IDR_RXEMPTY_MASK 0X00000800U
252 #define XQSPIPSU_IDR_GENFIFOFULL_SHIFT 10
253 #define XQSPIPSU_IDR_GENFIFOFULL_WIDTH 1
254 #define XQSPIPSU_IDR_GENFIFOFULL_MASK 0X00000400U
256 #define XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT 9
257 #define XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH 1
258 #define XQSPIPSU_IDR_GENFIFONOT_FULL_MASK 0X00000200U
260 #define XQSPIPSU_IDR_TXEMPTY_SHIFT 8
261 #define XQSPIPSU_IDR_TXEMPTY_WIDTH 1
262 #define XQSPIPSU_IDR_TXEMPTY_MASK 0X00000100U
264 #define XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT 7
265 #define XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH 1
266 #define XQSPIPSU_IDR_GENFIFOEMPTY_MASK 0X00000080U
268 #define XQSPIPSU_IDR_RXFULL_SHIFT 5
269 #define XQSPIPSU_IDR_RXFULL_WIDTH 1
270 #define XQSPIPSU_IDR_RXFULL_MASK 0X00000020U
272 #define XQSPIPSU_IDR_RXNEMPTY_SHIFT 4
273 #define XQSPIPSU_IDR_RXNEMPTY_WIDTH 1
274 #define XQSPIPSU_IDR_RXNEMPTY_MASK 0X00000010U
276 #define XQSPIPSU_IDR_TXFULL_SHIFT 3
277 #define XQSPIPSU_IDR_TXFULL_WIDTH 1
278 #define XQSPIPSU_IDR_TXFULL_MASK 0X00000008U
280 #define XQSPIPSU_IDR_TXNOT_FULL_SHIFT 2
281 #define XQSPIPSU_IDR_TXNOT_FULL_WIDTH 1
282 #define XQSPIPSU_IDR_TXNOT_FULL_MASK 0X00000004U
284 #define XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT 1
285 #define XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH 1
286 #define XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK 0X00000002U
288 #define XQSPIPSU_IDR_ALL_MASK 0X0FBEU
291 * Register: XQSPIPSU_IMR
293 #define XQSPIPSU_IMR_OFFSET 0X00000010U
295 #define XQSPIPSU_IMR_RXEMPTY_SHIFT 11
296 #define XQSPIPSU_IMR_RXEMPTY_WIDTH 1
297 #define XQSPIPSU_IMR_RXEMPTY_MASK 0X00000800U
299 #define XQSPIPSU_IMR_GENFIFOFULL_SHIFT 10
300 #define XQSPIPSU_IMR_GENFIFOFULL_WIDTH 1
301 #define XQSPIPSU_IMR_GENFIFOFULL_MASK 0X00000400U
303 #define XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT 9
304 #define XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH 1
305 #define XQSPIPSU_IMR_GENFIFONOT_FULL_MASK 0X00000200U
307 #define XQSPIPSU_IMR_TXEMPTY_SHIFT 8
308 #define XQSPIPSU_IMR_TXEMPTY_WIDTH 1
309 #define XQSPIPSU_IMR_TXEMPTY_MASK 0X00000100U
311 #define XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT 7
312 #define XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH 1
313 #define XQSPIPSU_IMR_GENFIFOEMPTY_MASK 0X00000080U
315 #define XQSPIPSU_IMR_RXFULL_SHIFT 5
316 #define XQSPIPSU_IMR_RXFULL_WIDTH 1
317 #define XQSPIPSU_IMR_RXFULL_MASK 0X00000020U
319 #define XQSPIPSU_IMR_RXNEMPTY_SHIFT 4
320 #define XQSPIPSU_IMR_RXNEMPTY_WIDTH 1
321 #define XQSPIPSU_IMR_RXNEMPTY_MASK 0X00000010U
323 #define XQSPIPSU_IMR_TXFULL_SHIFT 3
324 #define XQSPIPSU_IMR_TXFULL_WIDTH 1
325 #define XQSPIPSU_IMR_TXFULL_MASK 0X00000008U
327 #define XQSPIPSU_IMR_TXNOT_FULL_SHIFT 2
328 #define XQSPIPSU_IMR_TXNOT_FULL_WIDTH 1
329 #define XQSPIPSU_IMR_TXNOT_FULL_MASK 0X00000004U
331 #define XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT 1
332 #define XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH 1
333 #define XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK 0X00000002U
336 * Register: XQSPIPSU_EN_REG
338 #define XQSPIPSU_EN_OFFSET 0X00000014U
340 #define XQSPIPSU_EN_SHIFT 0
341 #define XQSPIPSU_EN_WIDTH 1
342 #define XQSPIPSU_EN_MASK 0X00000001U
345 * Register: XQSPIPSU_TXD
347 #define XQSPIPSU_TXD_OFFSET 0X0000001CU
349 #define XQSPIPSU_TXD_SHIFT 0
350 #define XQSPIPSU_TXD_WIDTH 32
351 #define XQSPIPSU_TXD_MASK 0XFFFFFFFFU
353 #define XQSPIPSU_TXD_DEPTH 64
356 * Register: XQSPIPSU_RXD
358 #define XQSPIPSU_RXD_OFFSET 0X00000020U
360 #define XQSPIPSU_RXD_SHIFT 0
361 #define XQSPIPSU_RXD_WIDTH 32
362 #define XQSPIPSU_RXD_MASK 0XFFFFFFFFU
365 * Register: XQSPIPSU_TX_THRESHOLD
367 #define XQSPIPSU_TX_THRESHOLD_OFFSET 0X00000028U
369 #define XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT 0
370 #define XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH 6
371 #define XQSPIPSU_TX_FIFO_THRESHOLD_MASK 0X0000003FU
372 #define XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL 0X01U
375 * Register: XQSPIPSU_RX_THRESHOLD
377 #define XQSPIPSU_RX_THRESHOLD_OFFSET 0X0000002CU
379 #define XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT 0
380 #define XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH 6
381 #define XQSPIPSU_RX_FIFO_THRESHOLD_MASK 0X0000003FU
382 #define XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL 0X01U
384 #define XQSPIPSU_RXFIFO_THRESHOLD_OPT 32U
387 * Register: XQSPIPSU_GPIO
389 #define XQSPIPSU_GPIO_OFFSET 0X00000030U
391 #define XQSPIPSU_GPIO_WP_N_SHIFT 0
392 #define XQSPIPSU_GPIO_WP_N_WIDTH 1
393 #define XQSPIPSU_GPIO_WP_N_MASK 0X00000001U
396 * Register: XQSPIPSU_LPBK_DLY_ADJ
398 #define XQSPIPSU_LPBK_DLY_ADJ_OFFSET 0X00000038U
400 #define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT 5
401 #define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH 1
402 #define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK 0X00000020U
404 #define XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT 3
405 #define XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH 2
406 #define XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK 0X00000018U
408 #define XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT 0
409 #define XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH 3
410 #define XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK 0X00000007U
413 * Register: XQSPIPSU_GEN_FIFO
415 #define XQSPIPSU_GEN_FIFO_OFFSET 0X00000040U
417 #define XQSPIPSU_GEN_FIFO_DATA_SHIFT 0
418 #define XQSPIPSU_GEN_FIFO_DATA_WIDTH 20
419 #define XQSPIPSU_GEN_FIFO_DATA_MASK 0X000FFFFFU
422 * Register: XQSPIPSU_SEL
424 #define XQSPIPSU_SEL_OFFSET 0X00000044U
426 #define XQSPIPSU_SEL_SHIFT 0
427 #define XQSPIPSU_SEL_WIDTH 1
428 #define XQSPIPSU_SEL_LQSPI_MASK 0X0U
429 #define XQSPIPSU_SEL_GQSPI_MASK 0X00000001U
432 * Register: XQSPIPSU_FIFO_CTRL
434 #define XQSPIPSU_FIFO_CTRL_OFFSET 0X0000004CU
436 #define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT 2
437 #define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH 1
438 #define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK 0X00000004U
440 #define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT 1
441 #define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH 1
442 #define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK 0X00000002U
444 #define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT 0
445 #define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH 1
446 #define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK 0X00000001U
449 * Register: XQSPIPSU_GF_THRESHOLD
451 #define XQSPIPSU_GF_THRESHOLD_OFFSET 0X00000050U
453 #define XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT 0
454 #define XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH 5
455 #define XQSPIPSU_GEN_FIFO_THRESHOLD_MASK 0X0000001F
456 #define XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL 0X10U
459 * Register: XQSPIPSU_POLL_CFG
461 #define XQSPIPSU_POLL_CFG_OFFSET 0X00000054U
463 #define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT 31
464 #define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH 1
465 #define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK 0X80000000U
467 #define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT 30
468 #define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH 1
469 #define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK 0X40000000U
471 #define XQSPIPSU_POLL_CFG_MASK_EN_SHIFT 8
472 #define XQSPIPSU_POLL_CFG_MASK_EN_WIDTH 8
473 #define XQSPIPSU_POLL_CFG_MASK_EN_MASK 0X0000FF00U
475 #define XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT 0
476 #define XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH 8
477 #define XQSPIPSU_POLL_CFG_DATA_VALUE_MASK 0X000000FFU
480 * Register: XQSPIPSU_P_TIMEOUT
482 #define XQSPIPSU_P_TO_OFFSET 0X00000058U
484 #define XQSPIPSU_P_TO_VALUE_SHIFT 0
485 #define XQSPIPSU_P_TO_VALUE_WIDTH 32
486 #define XQSPIPSU_P_TO_VALUE_MASK 0XFFFFFFFFU
489 * Register: XQSPIPSU_XFER_STS
491 #define XQSPIPSU_XFER_STS_OFFSET 0X0000005CU
493 #define XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT 0
494 #define XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH 32
495 #define XQSPIPSU_XFER_STS_PEND_BYTES_MASK 0XFFFFFFFFU
498 * Register: XQSPIPSU_GF_SNAPSHOT
500 #define XQSPIPSU_GF_SNAPSHOT_OFFSET 0X00000060U
502 #define XQSPIPSU_GF_SNAPSHOT_SHIFT 0
503 #define XQSPIPSU_GF_SNAPSHOT_WIDTH 20
504 #define XQSPIPSU_GF_SNAPSHOT_MASK 0X000FFFFFU
507 * Register: XQSPIPSU_RX_COPY
509 #define XQSPIPSU_RX_COPY_OFFSET 0X00000064U
511 #define XQSPIPSU_RX_COPY_UPPER_SHIFT 8
512 #define XQSPIPSU_RX_COPY_UPPER_WIDTH 8
513 #define XQSPIPSU_RX_COPY_UPPER_MASK 0X0000FF00U
515 #define XQSPIPSU_RX_COPY_LOWER_SHIFT 0
516 #define XQSPIPSU_RX_COPY_LOWER_WIDTH 8
517 #define XQSPIPSU_RX_COPY_LOWER_MASK 0X000000FFU
520 * Register: XQSPIPSU_MOD_ID
522 #define XQSPIPSU_MOD_ID_OFFSET 0X000000FCU
524 #define XQSPIPSU_MOD_ID_SHIFT 0
525 #define XQSPIPSU_MOD_ID_WIDTH 32
526 #define XQSPIPSU_MOD_ID_MASK 0XFFFFFFFFU
529 * Register: XQSPIPSU_QSPIDMA_DST_ADDR
531 #define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET 0X00000700U
533 #define XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT 2
534 #define XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH 30
535 #define XQSPIPSU_QSPIDMA_DST_ADDR_MASK 0XFFFFFFFCU
538 * Register: XQSPIPSU_QSPIDMA_DST_SIZE
540 #define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET 0X00000704U
542 #define XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT 2
543 #define XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH 27
544 #define XQSPIPSU_QSPIDMA_DST_SIZE_MASK 0X1FFFFFFCU
547 * Register: XQSPIPSU_QSPIDMA_DST_STS
549 #define XQSPIPSU_QSPIDMA_DST_STS_OFFSET 0X00000708U
551 #define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT 13
552 #define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH 3
553 #define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK 0X0000E000U
555 #define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT 5
556 #define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH 8
557 #define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK 0X00001FE0U
559 #define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT 1
560 #define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH 4
561 #define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK 0X0000001EU
563 #define XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT 0
564 #define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH 1
565 #define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK 0X00000001U
567 #define XQSPIPSU_QSPIDMA_DST_STS_WTC 0xE000U
570 * Register: XQSPIPSU_QSPIDMA_DST_CTRL
572 #define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET 0X0000070CU
574 #define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT 25
575 #define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH 7
576 #define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK 0XFE000000U
578 #define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT 24
579 #define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH 1
580 #define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK 0X01000000U
582 #define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT 23
583 #define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH 1
584 #define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK 0X00800000U
586 #define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT 22
587 #define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH 1
588 #define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK 0X00400000U
590 #define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT 10
591 #define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH 12
592 #define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK 0X003FFC00U
594 #define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT 2
595 #define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH 8
596 #define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK 0X000003FCU
598 #define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT 1
599 #define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH 1
600 #define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK 0X00000002U
602 #define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT 0
603 #define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH 1
604 #define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK 0X00000001U
606 #define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL 0x403FFA00U
609 * Register: XQSPIPSU_QSPIDMA_DST_I_STS
611 #define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET 0X00000714U
613 #define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT 7
614 #define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH 1
615 #define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK 0X00000080U
617 #define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT 6
618 #define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH 1
619 #define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK 0X00000040U
621 #define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT 5
622 #define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH 1
623 #define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK 0X00000020U
625 #define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT 4
626 #define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH 1
627 #define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK 0X00000010U
629 #define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT 3
630 #define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH 1
631 #define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK 0X00000008U
633 #define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT 2
634 #define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH 1
635 #define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK 0X00000004U
637 #define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT 1
638 #define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH 1
639 #define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK 0X00000002U
641 #define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK 0X000000FCU
642 #define XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK 0X000000FEU
645 * Register: XQSPIPSU_QSPIDMA_DST_I_EN
647 #define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET 0X00000718U
649 #define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT 7
650 #define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH 1
651 #define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK 0X00000080U
653 #define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT 6
654 #define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH 1
655 #define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK 0X00000040U
657 #define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT 5
658 #define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH 1
659 #define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK 0X00000020U
661 #define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT 4
662 #define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH 1
663 #define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK 0X00000010U
665 #define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT 3
666 #define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH 1
667 #define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK 0X00000008U
669 #define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT 2
670 #define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH 1
671 #define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK 0X00000004U
673 #define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT 1
674 #define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH 1
675 #define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK 0X00000002U
678 * Register: XQSPIPSU_QSPIDMA_DST_I_DIS
680 #define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET 0X0000071CU
682 #define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT 7
683 #define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH 1
684 #define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK 0X00000080U
686 #define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT 6
687 #define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH 1
688 #define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK 0X00000040U
690 #define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT 5
691 #define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH 1
692 #define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK 0X00000020U
694 #define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT 4
695 #define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH 1
696 #define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK 0X00000010U
698 #define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT 3
699 #define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH 1
700 #define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK 0X00000008U
702 #define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT 2
703 #define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH 1
704 #define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK 0X00000004U
706 #define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT 1
707 #define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH 1
708 #define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK 0X00000002U
711 * Register: XQSPIPSU_QSPIDMA_DST_IMR
713 #define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET 0X00000720U
715 #define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT 7
716 #define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH 1
717 #define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK 0X00000080U
719 #define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT 6
720 #define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH 1
721 #define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK 0X00000040U
723 #define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT 5
724 #define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH 1
725 #define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK 0X00000020U
727 #define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT 4
728 #define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH 1
729 #define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK 0X00000010U
731 #define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT 3
732 #define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH 1
733 #define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK 0X00000008U
735 #define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT 2
736 #define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH 1
737 #define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK 0X00000004U
739 #define XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT 1
740 #define XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH 1
741 #define XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK 0X00000002U
744 * Register: XQSPIPSU_QSPIDMA_DST_CTRL2
746 #define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET 0X00000724U
748 #define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT 27
749 #define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH 1
750 #define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK 0X08000000U
752 #define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT 24
753 #define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH 3
754 #define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK 0X07000000U
756 #define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT 22
757 #define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH 1
758 #define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK 0X00400000U
760 #define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT 19
761 #define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH 3
762 #define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK 0X00380000U
764 #define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT 16
765 #define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH 3
766 #define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK 0X00070000U
768 #define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT 4
769 #define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH 12
770 #define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK 0X0000FFF0U
772 #define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT 0
773 #define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH 4
774 #define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK 0X0000000FU
777 * Register: XQSPIPSU_QSPIDMA_DST_ADDR_MSB
779 #define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET 0X00000728U
781 #define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT 0
782 #define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH 12
783 #define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK 0X00000FFFU
786 * Register: XQSPIPSU_QSPIDMA_FUTURE_ECO
788 #define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET 0X00000EFCU
790 #define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT 0
791 #define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH 32
792 #define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK 0XFFFFFFFFU
797 #define XQSPIPSU_GENFIFO_IMM_DATA_MASK 0xFFU
798 #define XQSPIPSU_GENFIFO_DATA_XFER 0x100U
799 #define XQSPIPSU_GENFIFO_EXP 0x200U
800 #define XQSPIPSU_GENFIFO_MODE_SPI 0x400U
801 #define XQSPIPSU_GENFIFO_MODE_DUALSPI 0x800U
802 #define XQSPIPSU_GENFIFO_MODE_QUADSPI 0xC00U
803 #define XQSPIPSU_GENFIFO_MODE_MASK 0xC00U /* And with ~MASK first */
804 #define XQSPIPSU_GENFIFO_CS_LOWER 0x1000U
805 #define XQSPIPSU_GENFIFO_CS_UPPER 0x2000U
806 #define XQSPIPSU_GENFIFO_BUS_LOWER 0x4000U
807 #define XQSPIPSU_GENFIFO_BUS_UPPER 0x8000U
808 #define XQSPIPSU_GENFIFO_BUS_BOTH 0xC000U /* inverse is no bus */
809 #define XQSPIPSU_GENFIFO_BUS_MASK 0xC000U /* And with ~MASK first */
810 #define XQSPIPSU_GENFIFO_TX 0x10000U /* inverse is zero pump */
811 #define XQSPIPSU_GENFIFO_RX 0x20000U /* inverse is RX discard */
812 #define XQSPIPSU_GENFIFO_STRIPE 0x40000U
813 #define XQSPIPSU_GENFIFO_POLL 0x80000U
815 /*QSPI Data delay register*/
816 #define XQSPIPSU_DATA_DLY_ADJ_OFFSET 0X000000F8U
818 #define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT 31
819 #define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_WIDTH 1
820 #define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_MASK 0X80000000U
822 #define XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT 28
823 #define XQSPIPSU_DATA_DLY_ADJ_DLY_WIDTH 3
824 #define XQSPIPSU_DATA_DLY_ADJ_DLY_MASK 0X70000000U
826 /* Tapdelay Bypass register*/
827 #define IOU_TAPDLY_BYPASS_OFFSET 0X00000390
828 #define IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02
829 #define IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01
830 #define IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004
832 /***************** Macros (Inline Functions) Definitions *********************/
834 #define XQspiPsu_In32 Xil_In32
835 #define XQspiPsu_Out32 Xil_Out32
837 /****************************************************************************/
841 * @param BaseAddress contains the base address of the device.
842 * @param RegOffset contains the offset from the 1st register of the
843 * device to the target register.
845 * @return The value read from the register.
847 * @note C-Style signature:
848 * u32 XQspiPsu_ReadReg(u32 BaseAddress. s32 RegOffset)
850 ******************************************************************************/
851 #define XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset))
853 /***************************************************************************/
855 * Write to a register.
857 * @param BaseAddress contains the base address of the device.
858 * @param RegOffset contains the offset from the 1st register of the
859 * device to target register.
860 * @param RegisterValue is the value to be written to the register.
864 * @note C-Style signature:
865 * void XQspiPsu_WriteReg(u32 BaseAddress, s32 RegOffset,
868 ******************************************************************************/
869 #define XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))
877 #endif /* _XQSPIPSU_H_ */