1 /******************************************************************************
3 * Copyright (C) 2014 Xilinx, Inc. All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 * Except as contained in this notice, the name of the Xilinx shall not be used
28 * in advertising or otherwise to promote the sale, use or other dealings in
29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup qspipsu_v1_7
39 * This file contains low level access funcitons using the base address
40 * directly without an instance.
43 * MODIFICATION HISTORY:
45 * Ver Who Date Changes
46 * ----- --- -------- -----------------------------------------------.
47 * 1.0 hk 08/21/14 First release
48 * hk 03/18/15 Add DMA status register masks required.
49 * sk 04/24/15 Modified the code according to MISRAC-2012.
50 * 1.2 nsk 07/01/16 Added LQSPI supported Masks
51 * rk 07/15/16 Added support for TapDelays at different frequencies.
52 * 1.7 tjs 03/14/18 Added support in EL1 NS mode.
56 ******************************************************************************/
57 #ifndef _XQSPIPSU_HW_H_ /* prevent circular inclusions */
58 #define _XQSPIPSU_HW_H_ /* by using protection macros */
64 /***************************** Include Files *********************************/
66 #include "xil_types.h"
67 #include "xil_assert.h"
69 #include "xparameters.h"
71 /************************** Constant Definitions *****************************/
76 #define XQSPIPS_BASEADDR 0XFF0F0000U
81 #define XQSPIPSU_BASEADDR 0xFF0F0100U
82 #define XQSPIPSU_OFFSET 0x100U
85 * Register: XQSPIPS_EN_REG
87 #define XQSPIPS_EN_REG ( ( XQSPIPS_BASEADDR ) + 0X00000014U )
89 #define XQSPIPS_EN_SHIFT 0
90 #define XQSPIPS_EN_WIDTH 1
91 #define XQSPIPS_EN_MASK 0X00000001U
94 * Register: XQSPIPSU_CFG
96 #define XQSPIPSU_CFG_OFFSET 0X00000000U
97 #define XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U
99 #define XQSPIPSU_CFG_MODE_EN_SHIFT 30
100 #define XQSPIPSU_CFG_MODE_EN_WIDTH 2
101 #define XQSPIPSU_CFG_MODE_EN_MASK 0XC0000000U
102 #define XQSPIPSU_CFG_MODE_EN_DMA_MASK 0X80000000U
104 #define XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT 29
105 #define XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH 1
106 #define XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK 0X20000000U
108 #define XQSPIPSU_CFG_START_GEN_FIFO_SHIFT 28
109 #define XQSPIPSU_CFG_START_GEN_FIFO_WIDTH 1
110 #define XQSPIPSU_CFG_START_GEN_FIFO_MASK 0X10000000U
112 #define XQSPIPSU_CFG_ENDIAN_SHIFT 26
113 #define XQSPIPSU_CFG_ENDIAN_WIDTH 1
114 #define XQSPIPSU_CFG_ENDIAN_MASK 0X04000000U
116 #define XQSPIPSU_CFG_EN_POLL_TO_SHIFT 20
117 #define XQSPIPSU_CFG_EN_POLL_TO_WIDTH 1
118 #define XQSPIPSU_CFG_EN_POLL_TO_MASK 0X00100000U
120 #define XQSPIPSU_CFG_WP_HOLD_SHIFT 19
121 #define XQSPIPSU_CFG_WP_HOLD_WIDTH 1
122 #define XQSPIPSU_CFG_WP_HOLD_MASK 0X00080000U
124 #define XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT 3
125 #define XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH 3
126 #define XQSPIPSU_CFG_BAUD_RATE_DIV_MASK 0X00000038U
128 #define XQSPIPSU_CFG_CLK_PHA_SHIFT 2
129 #define XQSPIPSU_CFG_CLK_PHA_WIDTH 1
130 #define XQSPIPSU_CFG_CLK_PHA_MASK 0X00000004U
132 #define XQSPIPSU_CFG_CLK_POL_SHIFT 1
133 #define XQSPIPSU_CFG_CLK_POL_WIDTH 1
134 #define XQSPIPSU_CFG_CLK_POL_MASK 0X00000002U
137 * Register: XQSPIPSU_CFG
139 #define XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U
140 #define XQSPIPSU_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
141 #define XQSPIPSU_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
142 #define XQSPIPSU_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Seperate memory bus */
143 #define XQSPIPSU_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
144 #define XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK 0x01000000 /**< Upper memory page */
145 #define XQSPIPSU_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
146 #define XQSPIPSU_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
147 #define XQSPIPSU_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
149 #define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
150 #define XQSPIPS_LQSPI_CR_RST_STATE 0x80000003 /**< Default LQSPI CR value */
151 #define XQSPIPS_LQSPI_CR_4_BYTE_STATE 0x88000013 /**< Default 4 Byte LQSPI CR value */
152 #define XQSPIPS_LQSPI_CFG_RST_STATE 0x800238C1 /**< Default LQSPI CFG value */
154 * Register: XQSPIPSU_ISR
156 #define XQSPIPSU_ISR_OFFSET 0X00000004U
158 #define XQSPIPSU_ISR_RXEMPTY_SHIFT 11
159 #define XQSPIPSU_ISR_RXEMPTY_WIDTH 1
160 #define XQSPIPSU_ISR_RXEMPTY_MASK 0X00000800U
162 #define XQSPIPSU_ISR_GENFIFOFULL_SHIFT 10
163 #define XQSPIPSU_ISR_GENFIFOFULL_WIDTH 1
164 #define XQSPIPSU_ISR_GENFIFOFULL_MASK 0X00000400U
166 #define XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT 9
167 #define XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH 1
168 #define XQSPIPSU_ISR_GENFIFONOT_FULL_MASK 0X00000200U
170 #define XQSPIPSU_ISR_TXEMPTY_SHIFT 8
171 #define XQSPIPSU_ISR_TXEMPTY_WIDTH 1
172 #define XQSPIPSU_ISR_TXEMPTY_MASK 0X00000100U
174 #define XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT 7
175 #define XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH 1
176 #define XQSPIPSU_ISR_GENFIFOEMPTY_MASK 0X00000080U
178 #define XQSPIPSU_ISR_RXFULL_SHIFT 5
179 #define XQSPIPSU_ISR_RXFULL_WIDTH 1
180 #define XQSPIPSU_ISR_RXFULL_MASK 0X00000020U
182 #define XQSPIPSU_ISR_RXNEMPTY_SHIFT 4
183 #define XQSPIPSU_ISR_RXNEMPTY_WIDTH 1
184 #define XQSPIPSU_ISR_RXNEMPTY_MASK 0X00000010U
186 #define XQSPIPSU_ISR_TXFULL_SHIFT 3
187 #define XQSPIPSU_ISR_TXFULL_WIDTH 1
188 #define XQSPIPSU_ISR_TXFULL_MASK 0X00000008U
190 #define XQSPIPSU_ISR_TXNOT_FULL_SHIFT 2
191 #define XQSPIPSU_ISR_TXNOT_FULL_WIDTH 1
192 #define XQSPIPSU_ISR_TXNOT_FULL_MASK 0X00000004U
194 #define XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT 1
195 #define XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH 1
196 #define XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK 0X00000002U
198 #define XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002U
201 * Register: XQSPIPSU_IER
203 #define XQSPIPSU_IER_OFFSET 0X00000008U
205 #define XQSPIPSU_IER_RXEMPTY_SHIFT 11
206 #define XQSPIPSU_IER_RXEMPTY_WIDTH 1
207 #define XQSPIPSU_IER_RXEMPTY_MASK 0X00000800U
209 #define XQSPIPSU_IER_GENFIFOFULL_SHIFT 10
210 #define XQSPIPSU_IER_GENFIFOFULL_WIDTH 1
211 #define XQSPIPSU_IER_GENFIFOFULL_MASK 0X00000400U
213 #define XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT 9
214 #define XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH 1
215 #define XQSPIPSU_IER_GENFIFONOT_FULL_MASK 0X00000200U
217 #define XQSPIPSU_IER_TXEMPTY_SHIFT 8
218 #define XQSPIPSU_IER_TXEMPTY_WIDTH 1
219 #define XQSPIPSU_IER_TXEMPTY_MASK 0X00000100U
221 #define XQSPIPSU_IER_GENFIFOEMPTY_SHIFT 7
222 #define XQSPIPSU_IER_GENFIFOEMPTY_WIDTH 1
223 #define XQSPIPSU_IER_GENFIFOEMPTY_MASK 0X00000080U
225 #define XQSPIPSU_IER_RXFULL_SHIFT 5
226 #define XQSPIPSU_IER_RXFULL_WIDTH 1
227 #define XQSPIPSU_IER_RXFULL_MASK 0X00000020U
229 #define XQSPIPSU_IER_RXNEMPTY_SHIFT 4
230 #define XQSPIPSU_IER_RXNEMPTY_WIDTH 1
231 #define XQSPIPSU_IER_RXNEMPTY_MASK 0X00000010U
233 #define XQSPIPSU_IER_TXFULL_SHIFT 3
234 #define XQSPIPSU_IER_TXFULL_WIDTH 1
235 #define XQSPIPSU_IER_TXFULL_MASK 0X00000008U
237 #define XQSPIPSU_IER_TXNOT_FULL_SHIFT 2
238 #define XQSPIPSU_IER_TXNOT_FULL_WIDTH 1
239 #define XQSPIPSU_IER_TXNOT_FULL_MASK 0X00000004U
241 #define XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT 1
242 #define XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH 1
243 #define XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK 0X00000002U
246 * Register: XQSPIPSU_IDR
248 #define XQSPIPSU_IDR_OFFSET 0X0000000CU
250 #define XQSPIPSU_IDR_RXEMPTY_SHIFT 11
251 #define XQSPIPSU_IDR_RXEMPTY_WIDTH 1
252 #define XQSPIPSU_IDR_RXEMPTY_MASK 0X00000800U
254 #define XQSPIPSU_IDR_GENFIFOFULL_SHIFT 10
255 #define XQSPIPSU_IDR_GENFIFOFULL_WIDTH 1
256 #define XQSPIPSU_IDR_GENFIFOFULL_MASK 0X00000400U
258 #define XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT 9
259 #define XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH 1
260 #define XQSPIPSU_IDR_GENFIFONOT_FULL_MASK 0X00000200U
262 #define XQSPIPSU_IDR_TXEMPTY_SHIFT 8
263 #define XQSPIPSU_IDR_TXEMPTY_WIDTH 1
264 #define XQSPIPSU_IDR_TXEMPTY_MASK 0X00000100U
266 #define XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT 7
267 #define XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH 1
268 #define XQSPIPSU_IDR_GENFIFOEMPTY_MASK 0X00000080U
270 #define XQSPIPSU_IDR_RXFULL_SHIFT 5
271 #define XQSPIPSU_IDR_RXFULL_WIDTH 1
272 #define XQSPIPSU_IDR_RXFULL_MASK 0X00000020U
274 #define XQSPIPSU_IDR_RXNEMPTY_SHIFT 4
275 #define XQSPIPSU_IDR_RXNEMPTY_WIDTH 1
276 #define XQSPIPSU_IDR_RXNEMPTY_MASK 0X00000010U
278 #define XQSPIPSU_IDR_TXFULL_SHIFT 3
279 #define XQSPIPSU_IDR_TXFULL_WIDTH 1
280 #define XQSPIPSU_IDR_TXFULL_MASK 0X00000008U
282 #define XQSPIPSU_IDR_TXNOT_FULL_SHIFT 2
283 #define XQSPIPSU_IDR_TXNOT_FULL_WIDTH 1
284 #define XQSPIPSU_IDR_TXNOT_FULL_MASK 0X00000004U
286 #define XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT 1
287 #define XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH 1
288 #define XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK 0X00000002U
290 #define XQSPIPSU_IDR_ALL_MASK 0X0FBEU
293 * Register: XQSPIPSU_IMR
295 #define XQSPIPSU_IMR_OFFSET 0X00000010U
297 #define XQSPIPSU_IMR_RXEMPTY_SHIFT 11
298 #define XQSPIPSU_IMR_RXEMPTY_WIDTH 1
299 #define XQSPIPSU_IMR_RXEMPTY_MASK 0X00000800U
301 #define XQSPIPSU_IMR_GENFIFOFULL_SHIFT 10
302 #define XQSPIPSU_IMR_GENFIFOFULL_WIDTH 1
303 #define XQSPIPSU_IMR_GENFIFOFULL_MASK 0X00000400U
305 #define XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT 9
306 #define XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH 1
307 #define XQSPIPSU_IMR_GENFIFONOT_FULL_MASK 0X00000200U
309 #define XQSPIPSU_IMR_TXEMPTY_SHIFT 8
310 #define XQSPIPSU_IMR_TXEMPTY_WIDTH 1
311 #define XQSPIPSU_IMR_TXEMPTY_MASK 0X00000100U
313 #define XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT 7
314 #define XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH 1
315 #define XQSPIPSU_IMR_GENFIFOEMPTY_MASK 0X00000080U
317 #define XQSPIPSU_IMR_RXFULL_SHIFT 5
318 #define XQSPIPSU_IMR_RXFULL_WIDTH 1
319 #define XQSPIPSU_IMR_RXFULL_MASK 0X00000020U
321 #define XQSPIPSU_IMR_RXNEMPTY_SHIFT 4
322 #define XQSPIPSU_IMR_RXNEMPTY_WIDTH 1
323 #define XQSPIPSU_IMR_RXNEMPTY_MASK 0X00000010U
325 #define XQSPIPSU_IMR_TXFULL_SHIFT 3
326 #define XQSPIPSU_IMR_TXFULL_WIDTH 1
327 #define XQSPIPSU_IMR_TXFULL_MASK 0X00000008U
329 #define XQSPIPSU_IMR_TXNOT_FULL_SHIFT 2
330 #define XQSPIPSU_IMR_TXNOT_FULL_WIDTH 1
331 #define XQSPIPSU_IMR_TXNOT_FULL_MASK 0X00000004U
333 #define XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT 1
334 #define XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH 1
335 #define XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK 0X00000002U
338 * Register: XQSPIPSU_EN_REG
340 #define XQSPIPSU_EN_OFFSET 0X00000014U
342 #define XQSPIPSU_EN_SHIFT 0
343 #define XQSPIPSU_EN_WIDTH 1
344 #define XQSPIPSU_EN_MASK 0X00000001U
347 * Register: XQSPIPSU_TXD
349 #define XQSPIPSU_TXD_OFFSET 0X0000001CU
351 #define XQSPIPSU_TXD_SHIFT 0
352 #define XQSPIPSU_TXD_WIDTH 32
353 #define XQSPIPSU_TXD_MASK 0XFFFFFFFFU
355 #define XQSPIPSU_TXD_DEPTH 64
358 * Register: XQSPIPSU_RXD
360 #define XQSPIPSU_RXD_OFFSET 0X00000020U
362 #define XQSPIPSU_RXD_SHIFT 0
363 #define XQSPIPSU_RXD_WIDTH 32
364 #define XQSPIPSU_RXD_MASK 0XFFFFFFFFU
367 * Register: XQSPIPSU_TX_THRESHOLD
369 #define XQSPIPSU_TX_THRESHOLD_OFFSET 0X00000028U
371 #define XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT 0
372 #define XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH 6
373 #define XQSPIPSU_TX_FIFO_THRESHOLD_MASK 0X0000003FU
374 #define XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL 0X01U
377 * Register: XQSPIPSU_RX_THRESHOLD
379 #define XQSPIPSU_RX_THRESHOLD_OFFSET 0X0000002CU
381 #define XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT 0
382 #define XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH 6
383 #define XQSPIPSU_RX_FIFO_THRESHOLD_MASK 0X0000003FU
384 #define XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL 0X01U
386 #define XQSPIPSU_RXFIFO_THRESHOLD_OPT 32U
389 * Register: XQSPIPSU_GPIO
391 #define XQSPIPSU_GPIO_OFFSET 0X00000030U
393 #define XQSPIPSU_GPIO_WP_N_SHIFT 0
394 #define XQSPIPSU_GPIO_WP_N_WIDTH 1
395 #define XQSPIPSU_GPIO_WP_N_MASK 0X00000001U
398 * Register: XQSPIPSU_LPBK_DLY_ADJ
400 #define XQSPIPSU_LPBK_DLY_ADJ_OFFSET 0X00000038U
402 #define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT 5
403 #define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH 1
404 #define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK 0X00000020U
406 #define XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT 3
407 #define XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH 2
408 #define XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK 0X00000018U
410 #define XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT 0
411 #define XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH 3
412 #define XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK 0X00000007U
415 * Register: XQSPIPSU_GEN_FIFO
417 #define XQSPIPSU_GEN_FIFO_OFFSET 0X00000040U
419 #define XQSPIPSU_GEN_FIFO_DATA_SHIFT 0
420 #define XQSPIPSU_GEN_FIFO_DATA_WIDTH 20
421 #define XQSPIPSU_GEN_FIFO_DATA_MASK 0X000FFFFFU
424 * Register: XQSPIPSU_SEL
426 #define XQSPIPSU_SEL_OFFSET 0X00000044U
428 #define XQSPIPSU_SEL_SHIFT 0
429 #define XQSPIPSU_SEL_WIDTH 1
430 #define XQSPIPSU_SEL_LQSPI_MASK 0X0U
431 #define XQSPIPSU_SEL_GQSPI_MASK 0X00000001U
434 * Register: XQSPIPSU_FIFO_CTRL
436 #define XQSPIPSU_FIFO_CTRL_OFFSET 0X0000004CU
438 #define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT 2
439 #define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH 1
440 #define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK 0X00000004U
442 #define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT 1
443 #define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH 1
444 #define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK 0X00000002U
446 #define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT 0
447 #define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH 1
448 #define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK 0X00000001U
451 * Register: XQSPIPSU_GF_THRESHOLD
453 #define XQSPIPSU_GF_THRESHOLD_OFFSET 0X00000050U
455 #define XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT 0
456 #define XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH 5
457 #define XQSPIPSU_GEN_FIFO_THRESHOLD_MASK 0X0000001F
458 #define XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL 0X10U
461 * Register: XQSPIPSU_POLL_CFG
463 #define XQSPIPSU_POLL_CFG_OFFSET 0X00000054U
465 #define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT 31
466 #define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH 1
467 #define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK 0X80000000U
469 #define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT 30
470 #define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH 1
471 #define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK 0X40000000U
473 #define XQSPIPSU_POLL_CFG_MASK_EN_SHIFT 8
474 #define XQSPIPSU_POLL_CFG_MASK_EN_WIDTH 8
475 #define XQSPIPSU_POLL_CFG_MASK_EN_MASK 0X0000FF00U
477 #define XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT 0
478 #define XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH 8
479 #define XQSPIPSU_POLL_CFG_DATA_VALUE_MASK 0X000000FFU
482 * Register: XQSPIPSU_P_TIMEOUT
484 #define XQSPIPSU_P_TO_OFFSET 0X00000058U
486 #define XQSPIPSU_P_TO_VALUE_SHIFT 0
487 #define XQSPIPSU_P_TO_VALUE_WIDTH 32
488 #define XQSPIPSU_P_TO_VALUE_MASK 0XFFFFFFFFU
491 * Register: XQSPIPSU_XFER_STS
493 #define XQSPIPSU_XFER_STS_OFFSET 0X0000005CU
495 #define XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT 0
496 #define XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH 32
497 #define XQSPIPSU_XFER_STS_PEND_BYTES_MASK 0XFFFFFFFFU
500 * Register: XQSPIPSU_GF_SNAPSHOT
502 #define XQSPIPSU_GF_SNAPSHOT_OFFSET 0X00000060U
504 #define XQSPIPSU_GF_SNAPSHOT_SHIFT 0
505 #define XQSPIPSU_GF_SNAPSHOT_WIDTH 20
506 #define XQSPIPSU_GF_SNAPSHOT_MASK 0X000FFFFFU
509 * Register: XQSPIPSU_RX_COPY
511 #define XQSPIPSU_RX_COPY_OFFSET 0X00000064U
513 #define XQSPIPSU_RX_COPY_UPPER_SHIFT 8
514 #define XQSPIPSU_RX_COPY_UPPER_WIDTH 8
515 #define XQSPIPSU_RX_COPY_UPPER_MASK 0X0000FF00U
517 #define XQSPIPSU_RX_COPY_LOWER_SHIFT 0
518 #define XQSPIPSU_RX_COPY_LOWER_WIDTH 8
519 #define XQSPIPSU_RX_COPY_LOWER_MASK 0X000000FFU
522 * Register: XQSPIPSU_MOD_ID
524 #define XQSPIPSU_MOD_ID_OFFSET 0X000000FCU
526 #define XQSPIPSU_MOD_ID_SHIFT 0
527 #define XQSPIPSU_MOD_ID_WIDTH 32
528 #define XQSPIPSU_MOD_ID_MASK 0XFFFFFFFFU
531 * Register: XQSPIPSU_QSPIDMA_DST_ADDR
533 #define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET 0X00000700U
535 #define XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT 2
536 #define XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH 30
537 #define XQSPIPSU_QSPIDMA_DST_ADDR_MASK 0XFFFFFFFCU
540 * Register: XQSPIPSU_QSPIDMA_DST_SIZE
542 #define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET 0X00000704U
544 #define XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT 2
545 #define XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH 27
546 #define XQSPIPSU_QSPIDMA_DST_SIZE_MASK 0X1FFFFFFCU
549 * Register: XQSPIPSU_QSPIDMA_DST_STS
551 #define XQSPIPSU_QSPIDMA_DST_STS_OFFSET 0X00000708U
553 #define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT 13
554 #define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH 3
555 #define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK 0X0000E000U
557 #define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT 5
558 #define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH 8
559 #define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK 0X00001FE0U
561 #define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT 1
562 #define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH 4
563 #define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK 0X0000001EU
565 #define XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT 0
566 #define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH 1
567 #define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK 0X00000001U
569 #define XQSPIPSU_QSPIDMA_DST_STS_WTC 0xE000U
572 * Register: XQSPIPSU_QSPIDMA_DST_CTRL
574 #define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET 0X0000070CU
576 #define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT 25
577 #define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH 7
578 #define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK 0XFE000000U
580 #define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT 24
581 #define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH 1
582 #define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK 0X01000000U
584 #define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT 23
585 #define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH 1
586 #define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK 0X00800000U
588 #define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT 22
589 #define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH 1
590 #define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK 0X00400000U
592 #define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT 10
593 #define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH 12
594 #define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK 0X003FFC00U
596 #define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT 2
597 #define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH 8
598 #define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK 0X000003FCU
600 #define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT 1
601 #define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH 1
602 #define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK 0X00000002U
604 #define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT 0
605 #define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH 1
606 #define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK 0X00000001U
608 #define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL 0x403FFA00U
611 * Register: XQSPIPSU_QSPIDMA_DST_I_STS
613 #define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET 0X00000714U
615 #define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT 7
616 #define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH 1
617 #define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK 0X00000080U
619 #define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT 6
620 #define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH 1
621 #define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK 0X00000040U
623 #define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT 5
624 #define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH 1
625 #define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK 0X00000020U
627 #define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT 4
628 #define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH 1
629 #define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK 0X00000010U
631 #define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT 3
632 #define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH 1
633 #define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK 0X00000008U
635 #define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT 2
636 #define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH 1
637 #define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK 0X00000004U
639 #define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT 1
640 #define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH 1
641 #define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK 0X00000002U
643 #define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK 0X000000FCU
644 #define XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK 0X000000FEU
647 * Register: XQSPIPSU_QSPIDMA_DST_I_EN
649 #define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET 0X00000718U
651 #define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT 7
652 #define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH 1
653 #define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK 0X00000080U
655 #define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT 6
656 #define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH 1
657 #define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK 0X00000040U
659 #define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT 5
660 #define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH 1
661 #define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK 0X00000020U
663 #define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT 4
664 #define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH 1
665 #define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK 0X00000010U
667 #define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT 3
668 #define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH 1
669 #define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK 0X00000008U
671 #define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT 2
672 #define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH 1
673 #define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK 0X00000004U
675 #define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT 1
676 #define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH 1
677 #define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK 0X00000002U
680 * Register: XQSPIPSU_QSPIDMA_DST_I_DIS
682 #define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET 0X0000071CU
684 #define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT 7
685 #define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH 1
686 #define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK 0X00000080U
688 #define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT 6
689 #define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH 1
690 #define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK 0X00000040U
692 #define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT 5
693 #define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH 1
694 #define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK 0X00000020U
696 #define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT 4
697 #define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH 1
698 #define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK 0X00000010U
700 #define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT 3
701 #define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH 1
702 #define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK 0X00000008U
704 #define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT 2
705 #define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH 1
706 #define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK 0X00000004U
708 #define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT 1
709 #define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH 1
710 #define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK 0X00000002U
713 * Register: XQSPIPSU_QSPIDMA_DST_IMR
715 #define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET 0X00000720U
717 #define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT 7
718 #define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH 1
719 #define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK 0X00000080U
721 #define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT 6
722 #define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH 1
723 #define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK 0X00000040U
725 #define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT 5
726 #define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH 1
727 #define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK 0X00000020U
729 #define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT 4
730 #define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH 1
731 #define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK 0X00000010U
733 #define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT 3
734 #define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH 1
735 #define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK 0X00000008U
737 #define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT 2
738 #define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH 1
739 #define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK 0X00000004U
741 #define XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT 1
742 #define XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH 1
743 #define XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK 0X00000002U
746 * Register: XQSPIPSU_QSPIDMA_DST_CTRL2
748 #define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET 0X00000724U
750 #define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT 27
751 #define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH 1
752 #define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK 0X08000000U
754 #define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT 24
755 #define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH 3
756 #define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK 0X07000000U
758 #define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT 22
759 #define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH 1
760 #define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK 0X00400000U
762 #define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT 19
763 #define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH 3
764 #define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK 0X00380000U
766 #define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT 16
767 #define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH 3
768 #define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK 0X00070000U
770 #define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT 4
771 #define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH 12
772 #define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK 0X0000FFF0U
774 #define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT 0
775 #define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH 4
776 #define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK 0X0000000FU
779 * Register: XQSPIPSU_QSPIDMA_DST_ADDR_MSB
781 #define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET 0X00000728U
783 #define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT 0
784 #define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH 12
785 #define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK 0X00000FFFU
788 * Register: XQSPIPSU_QSPIDMA_FUTURE_ECO
790 #define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET 0X00000EFCU
792 #define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT 0
793 #define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH 32
794 #define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK 0XFFFFFFFFU
799 #define XQSPIPSU_GENFIFO_IMM_DATA_MASK 0xFFU
800 #define XQSPIPSU_GENFIFO_DATA_XFER 0x100U
801 #define XQSPIPSU_GENFIFO_EXP 0x200U
802 #define XQSPIPSU_GENFIFO_MODE_SPI 0x400U
803 #define XQSPIPSU_GENFIFO_MODE_DUALSPI 0x800U
804 #define XQSPIPSU_GENFIFO_MODE_QUADSPI 0xC00U
805 #define XQSPIPSU_GENFIFO_MODE_MASK 0xC00U /* And with ~MASK first */
806 #define XQSPIPSU_GENFIFO_CS_LOWER 0x1000U
807 #define XQSPIPSU_GENFIFO_CS_UPPER 0x2000U
808 #define XQSPIPSU_GENFIFO_BUS_LOWER 0x4000U
809 #define XQSPIPSU_GENFIFO_BUS_UPPER 0x8000U
810 #define XQSPIPSU_GENFIFO_BUS_BOTH 0xC000U /* inverse is no bus */
811 #define XQSPIPSU_GENFIFO_BUS_MASK 0xC000U /* And with ~MASK first */
812 #define XQSPIPSU_GENFIFO_TX 0x10000U /* inverse is zero pump */
813 #define XQSPIPSU_GENFIFO_RX 0x20000U /* inverse is RX discard */
814 #define XQSPIPSU_GENFIFO_STRIPE 0x40000U
815 #define XQSPIPSU_GENFIFO_POLL 0x80000U
817 /*QSPI Data delay register*/
818 #define XQSPIPSU_DATA_DLY_ADJ_OFFSET 0X000000F8U
820 #define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT 31
821 #define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_WIDTH 1
822 #define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_MASK 0X80000000U
824 #define XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT 28
825 #define XQSPIPSU_DATA_DLY_ADJ_DLY_WIDTH 3
826 #define XQSPIPSU_DATA_DLY_ADJ_DLY_MASK 0X70000000U
828 /* Tapdelay Bypass register*/
829 #define IOU_TAPDLY_BYPASS_OFFSET 0X00000390
830 #define IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02
831 #define IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01
832 #define IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004
833 #define IOU_TAPDLY_RESET_STATE 0x7
835 /***************** Macros (Inline Functions) Definitions *********************/
837 #define XQspiPsu_In32 Xil_In32
838 #define XQspiPsu_Out32 Xil_Out32
840 /****************************************************************************/
844 * @param BaseAddress contains the base address of the device.
845 * @param RegOffset contains the offset from the 1st register of the
846 * device to the target register.
848 * @return The value read from the register.
850 * @note C-Style signature:
851 * u32 XQspiPsu_ReadReg(u32 BaseAddress. s32 RegOffset)
853 ******************************************************************************/
854 #define XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset))
856 /***************************************************************************/
858 * Write to a register.
860 * @param BaseAddress contains the base address of the device.
861 * @param RegOffset contains the offset from the 1st register of the
862 * device to target register.
863 * @param RegisterValue is the value to be written to the register.
867 * @note C-Style signature:
868 * void XQspiPsu_WriteReg(u32 BaseAddress, s32 RegOffset,
871 ******************************************************************************/
872 #define XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))
880 #endif /* _XQSPIPSU_H_ */