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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2017 Xilinx, Inc.  All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
  28 * in advertising or otherwise to promote the sale, use or other dealings in
  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /****************************************************************************/
  33 /**
  34 *
  35 * @file xresetps.c
  36 * @addtogroup xresetps_v1_0
  37 * @{
  38 *
  39 * Contains the implementation of interface functions of the XResetPs driver.
  40 * See xresetps.h for a description of the driver.
  41 *
  42 * <pre>
  43 * MODIFICATION HISTORY:
  44 * Ver   Who    Date     Changes
  45 * ----- ------ -------- ---------------------------------------------
  46 * 1.00  cjp    09/05/17 First release
  47 * </pre>
  48 *
  49 ******************************************************************************/
  50
  51 /***************************** Include Files *********************************/
  52 #include "xresetps.h"
  53 #include "xresetps_hw.h"
  54 #include "xil_types.h"
  55
  56 /************************** Constant Definitions *****************************/
  57 #define XRESETPS_RSTID_BASE             (1000)
  58 #define XRESETPS_REGADDR_INVALID        (0xFFFFFFFFU)
  59 #define XRESETPS_BM_INVALID             (0xFFFFFFFFU)
  60
  61 /**************************** Type Definitions *******************************/
  62 typedef struct {
  63         const u32                 SlcrregAddr;
  64         const u32                 SlcrregBitmask;
  65         const u32                 PwrStateBitmask;
  66         const XResetPs_PulseTypes PulseType;
  67         const u8                  SupportedActions;
  68 } XResetPs_Lookup;
  69
  70 /************************** Variable Definitions *****************************/
  71 #if !EL1_NONSECURE
  72 const static XResetPs_Lookup ResetMap[] = {
  73         /*
  74          *      {Control Register, Control Bitmask,
  75          *       Power State Bitask, Pulse Type,
  76          *       Supported Actions},
  77          */
  78         {XRESETPS_CRF_APB_RST_FPD_TOP,  PCIE_CFG_RESET_MASK,
  79         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
  80         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
  81         {XRESETPS_CRF_APB_RST_FPD_TOP,  PCIE_BRIDGE_RESET_MASK,
  82         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
  83         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
  84         {XRESETPS_CRF_APB_RST_FPD_TOP,  PCIE_CTRL_RESET_MASK,
  85         PCIE_CTRL_PSCHK_MASK,           XRESETPS_PT_DLY_PSCHK,
  86         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
  87         {XRESETPS_CRF_APB_RST_FPD_TOP,  DP_RESET_MASK,
  88         DP_PSCHK_MASK,                  XRESETPS_PT_DLY_PSCHK,
  89         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
  90         {XRESETPS_CRF_APB_RST_FPD_TOP,  SWDT_RESET_MASK,
  91         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
  92         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
  93         {XRESETPS_CRF_APB_RST_FPD_TOP,  AFI_FM5_RESET_MASK,
  94         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
  95         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
  96         {XRESETPS_CRF_APB_RST_FPD_TOP,  AFI_FM4_RESET_MASK,
  97         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
  98         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
  99         {XRESETPS_CRF_APB_RST_FPD_TOP,  AFI_FM3_RESET_MASK,
 100         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 101         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 102         {XRESETPS_CRF_APB_RST_FPD_TOP,  AFI_FM2_RESET_MASK,
 103         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 104         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 105         {XRESETPS_CRF_APB_RST_FPD_TOP,  AFI_FM1_RESET_MASK,
 106         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 107         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 108         {XRESETPS_CRF_APB_RST_FPD_TOP,  AFI_FM0_RESET_MASK,
 109         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 110         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 111         {XRESETPS_CRF_APB_RST_FPD_TOP,  GDMA_RESET_MASK,
 112         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 113         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 114         {XRESETPS_CRF_APB_RST_FPD_TOP,  GPU_PP1_RESET_MASK,
 115         GPU_PP1_PSCHK_MASK,             XRESETPS_PT_DLY_PSCHK,
 116         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 117         {XRESETPS_CRF_APB_RST_FPD_TOP,  GPU_PP0_RESET_MASK,
 118         GPU_PP0_PSCHK_MASK,             XRESETPS_PT_DLY_PSCHK,
 119         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 120         {XRESETPS_CRF_APB_RST_FPD_TOP,  GPU_RESET_MASK,
 121         GPU_PSCHK_MASK,                 XRESETPS_PT_DLY_PSCHK,
 122         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 123         {XRESETPS_CRF_APB_RST_FPD_TOP,  GT_RESET_MASK,
 124         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 125         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 126         {XRESETPS_CRF_APB_RST_FPD_TOP,  SATA_RESET_MASK,
 127         SATA_PSCHK_MASK,                XRESETPS_PT_DLY_PSCHK,
 128         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 129         {XRESETPS_CRF_APB_RST_FPD_APU,  ACPU3_PWRON_RESET_MASK,
 130         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 131         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 132         {XRESETPS_CRF_APB_RST_FPD_APU,  ACPU2_PWRON_RESET_MASK,
 133         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 134         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 135         {XRESETPS_CRF_APB_RST_FPD_APU,  ACPU1_PWRON_RESET_MASK,
 136         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 137         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 138         {XRESETPS_CRF_APB_RST_FPD_APU,  ACPU0_PWRON_RESET_MASK,
 139         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 140         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 141         {XRESETPS_CRF_APB_RST_FPD_APU,  APU_L2_RESET_MASK,
 142         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 143         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 144         {XRESETPS_CRF_APB_RST_FPD_APU,  ACPU3_RESET_MASK,
 145         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 146         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 147         {XRESETPS_CRF_APB_RST_FPD_APU,  ACPU2_RESET_MASK,
 148         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 149         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 150         {XRESETPS_CRF_APB_RST_FPD_APU,  ACPU1_RESET_MASK,
 151         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 152         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 153         {XRESETPS_CRF_APB_RST_FPD_APU,  ACPU0_RESET_MASK,
 154         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 155         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 156         {XRESETPS_CRF_APB_RST_DDR_SS,   DDR_RESET_MASK,
 157         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 158         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 159         {XRESETPS_CRF_APB_RST_DDR_SS,   DDR_APM_RESET_MASK,
 160         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 161         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 162         {XRESETPS_CRL_APB_RESET_CTRL,   SOFT_RESET_MASK,
 163         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 164         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 165         {XRESETPS_CRL_APB_RST_LPD_IOU0, GEM0_RESET_MASK,
 166         XRESETPS_BM_INVALID,            XRESETPS_PT_DLY_NO_PSCHK,
 167         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 168         {XRESETPS_CRL_APB_RST_LPD_IOU0, GEM1_RESET_MASK,
 169         XRESETPS_BM_INVALID,            XRESETPS_PT_DLY_NO_PSCHK,
 170         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 171         {XRESETPS_CRL_APB_RST_LPD_IOU0, GEM2_RESET_MASK,
 172         XRESETPS_BM_INVALID,            XRESETPS_PT_DLY_NO_PSCHK,
 173         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 174         {XRESETPS_CRL_APB_RST_LPD_IOU0, GEM3_RESET_MASK,
 175         XRESETPS_BM_INVALID,            XRESETPS_PT_DLY_NO_PSCHK,
 176         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 177         {XRESETPS_CRL_APB_RST_LPD_IOU2, QSPI_RESET_MASK,
 178         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 179         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 180         {XRESETPS_CRL_APB_RST_LPD_IOU2, UART0_RESET_MASK,
 181         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 182         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 183         {XRESETPS_CRL_APB_RST_LPD_IOU2, UART1_RESET_MASK,
 184         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 185         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 186         {XRESETPS_CRL_APB_RST_LPD_IOU2, SPI0_RESET_MASK,
 187         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 188         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 189         {XRESETPS_CRL_APB_RST_LPD_IOU2, SPI1_RESET_MASK,
 190         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 191         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 192         {XRESETPS_CRL_APB_RST_LPD_IOU2, SDIO0_RESET_MASK,
 193         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 194         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 195         {XRESETPS_CRL_APB_RST_LPD_IOU2, SDIO1_RESET_MASK,
 196         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 197         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 198         {XRESETPS_CRL_APB_RST_LPD_IOU2, CAN0_RESET_MASK,
 199         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 200         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 201         {XRESETPS_CRL_APB_RST_LPD_IOU2, CAN1_RESET_MASK,
 202         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 203         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 204         {XRESETPS_CRL_APB_RST_LPD_IOU2, I2C0_RESET_MASK,
 205         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 206         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 207         {XRESETPS_CRL_APB_RST_LPD_IOU2, I2C1_RESET_MASK,
 208         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 209         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 210         {XRESETPS_CRL_APB_RST_LPD_IOU2, TTC0_RESET_MASK,
 211         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 212         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 213         {XRESETPS_CRL_APB_RST_LPD_IOU2, TTC1_RESET_MASK,
 214         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 215         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 216         {XRESETPS_CRL_APB_RST_LPD_IOU2, TTC2_RESET_MASK,
 217         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 218         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 219         {XRESETPS_CRL_APB_RST_LPD_IOU2, TTC3_RESET_MASK,
 220         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 221         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 222         {XRESETPS_CRL_APB_RST_LPD_IOU2, SWDT_RESET_MASK,
 223         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 224         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 225         {XRESETPS_CRL_APB_RST_LPD_IOU2, NAND_RESET_MASK,
 226         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 227         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 228         {XRESETPS_CRL_APB_RST_LPD_IOU2, ADMA_RESET_MASK,
 229         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 230         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 231         {XRESETPS_CRL_APB_RST_LPD_IOU2, GPIO_RESET_MASK,
 232         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 233         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 234         {XRESETPS_CRL_APB_RST_LPD_IOU2, IOU_CC_RESET_MASK,
 235         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 236         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 237         {XRESETPS_CRL_APB_RST_LPD_IOU2, TIMESTAMP_RESET_MASK,
 238         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 239         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 240         {XRESETPS_CRL_APB_RST_LPD_TOP,  RPU_R50_RESET_MASK,
 241         R50_PSCHK_MASK,                 XRESETPS_PT_DLY_PSCHK,
 242         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 243         {XRESETPS_CRL_APB_RST_LPD_TOP,  RPU_R51_RESET_MASK,
 244         R51_PSCHK_MASK,                 XRESETPS_PT_DLY_PSCHK,
 245         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 246         {XRESETPS_CRL_APB_RST_LPD_TOP,  RPU_AMBA_RESET_MASK,
 247         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 248         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 249         {XRESETPS_CRL_APB_RST_LPD_TOP,  OCM_RESET_MASK,
 250         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 251         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 252         {XRESETPS_CRL_APB_RST_LPD_TOP,  RPU_PGE_RESET_MASK,
 253         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 254         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 255         {XRESETPS_CRL_APB_RST_LPD_TOP,  USB0_CORERESET_MASK,
 256         XRESETPS_BM_INVALID,            XRESETPS_PT_DLY_NO_PSCHK,
 257         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 258         {XRESETPS_CRL_APB_RST_LPD_TOP,  USB1_CORERESET_MASK,
 259         XRESETPS_BM_INVALID,            XRESETPS_PT_DLY_NO_PSCHK,
 260         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 261         {XRESETPS_CRL_APB_RST_LPD_TOP,  USB0_HIBERRESET_MASK,
 262         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 263         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 264         {XRESETPS_CRL_APB_RST_LPD_TOP,  USB1_HIBERRESET_MASK,
 265         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 266         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 267         {XRESETPS_CRL_APB_RST_LPD_TOP,  USB0_APB_RESET_MASK,
 268         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 269         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 270         {XRESETPS_CRL_APB_RST_LPD_TOP,  USB1_APB_RESET_MASK,
 271         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 272         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 273         {XRESETPS_CRL_APB_RST_LPD_TOP,  IPI_RESET_MASK,
 274         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 275         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 276         {XRESETPS_CRL_APB_RST_LPD_TOP,  APM_RESET_MASK,
 277         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 278         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 279         {XRESETPS_CRL_APB_RST_LPD_TOP,  RTC_RESET_MASK,
 280         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 281         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 282         {XRESETPS_CRL_APB_RST_LPD_TOP,  SYSMON_RESET_MASK,
 283         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 284         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 285         {XRESETPS_CRL_APB_RST_LPD_TOP,  AFI_FM6_RESET_MASK,
 286         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 287         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 288         {XRESETPS_CRL_APB_RST_LPD_TOP,  LPD_SWDT_RESET_MASK,
 289         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 290         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 291         {XRESETPS_CRL_APB_RST_LPD_TOP,  FPD_RESET_MASK,
 292         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 293         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 294         {XRESETPS_CRL_APB_RST_LPD_DBG,  RPU_DBG1_RESET_MASK,
 295         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 296         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 297         {XRESETPS_CRL_APB_RST_LPD_DBG,  RPU_DBG0_RESET_MASK,
 298         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 299         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 300         {XRESETPS_CRL_APB_RST_LPD_DBG,  DBG_LPD_RESET_MASK,
 301         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 302         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 303         {XRESETPS_CRL_APB_RST_LPD_DBG,  DBG_FPD_RESET_MASK,
 304         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 305         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 306         {XRESETPS_CRF_APB_APLL_CTRL,    APLL_RESET_MASK,
 307         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 308         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 309         {XRESETPS_CRF_APB_DPLL_CTRL,    DPLL_RESET_MASK,
 310         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 311         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 312         {XRESETPS_CRF_APB_VPLL_CTRL,    VPLL_RESET_MASK,
 313         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 314         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 315         {XRESETPS_CRL_APB_IOPLL_CTRL,   IOPLL_RESET_MASK,
 316         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 317         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 318         {XRESETPS_CRL_APB_RPLL_CTRL,    RPLL_RESET_MASK,
 319         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 320         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)},
 321         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL0_RESET_MASK,
 322         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 323         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 324         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL1_RESET_MASK,
 325         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 326         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 327         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL2_RESET_MASK,
 328         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 329         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 330         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL3_RESET_MASK,
 331         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 332         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 333         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL4_RESET_MASK,
 334         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 335         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 336         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL5_RESET_MASK,
 337         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 338         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 339         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL6_RESET_MASK,
 340         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 341         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 342         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL7_RESET_MASK,
 343         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 344         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 345         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL8_RESET_MASK,
 346         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 347         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 348         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL9_RESET_MASK,
 349         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 350         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 351         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL10_RESET_MASK,
 352         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 353         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 354         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL11_RESET_MASK,
 355         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 356         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 357         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL12_RESET_MASK,
 358         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 359         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 360         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL13_RESET_MASK,
 361         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 362         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 363         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL14_RESET_MASK,
 364         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 365         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 366         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL15_RESET_MASK,
 367         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 368         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 369         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL16_RESET_MASK,
 370         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 371         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 372         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL17_RESET_MASK,
 373         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 374         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 375         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL18_RESET_MASK,
 376         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 377         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 378         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL19_RESET_MASK,
 379         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 380         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 381         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL20_RESET_MASK,
 382         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 383         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 384         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL21_RESET_MASK,
 385         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 386         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 387         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL22_RESET_MASK,
 388         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 389         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 390         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL23_RESET_MASK,
 391         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 392         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 393         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL24_RESET_MASK,
 394         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 395         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 396         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL25_RESET_MASK,
 397         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 398         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 399         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL26_RESET_MASK,
 400         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 401         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 402         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL27_RESET_MASK,
 403         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 404         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 405         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL28_RESET_MASK,
 406         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 407         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 408         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL29_RESET_MASK,
 409         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 410         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 411         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL30_RESET_MASK,
 412         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 413         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 414         {XRESETPS_PMU_IOM_GPO3_CTRL,    GPO3_PL31_RESET_MASK,
 415         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 416         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 417         {XRESETPS_PMU_GLB_RST_CTRL,     RPU_LS_RESET_MASK,
 418         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 419         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_NOSUP)},
 420         {XRESETPS_PMU_GLB_RST_CTRL,     PS_ONLY_RESET_MASK,
 421         XRESETPS_BM_INVALID,            XRESETPS_PT_NO_DLY_NO_PSCHK,
 422         XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_NOSUP)},
 423         /* All fields invalidated for PL since not supported */
 424         {XRESETPS_REGADDR_INVALID,      XRESETPS_BM_INVALID,
 425         XRESETPS_BM_INVALID,            XRESETPS_PT_INVALID,
 426         XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)},
 427 };
 428 #endif
 429
 430 /***************** Macros (Inline Functions) Definitions *********************/
 431
 432 /****************************************************************************/
 433 /**
 434 *
 435 * Initialize a specific reset controller instance/driver. This function
 436 * must be called before other functions of the driver are called.
 437 *
 438 * @param        InstancePtr is a pointer to the XResetPs instance.
 439 * @param        ConfigPtr is the config structure.
 440 * @param        EffectiveAddress is the base address for the device. It could be
 441 *               a virtual address if address translation is supported in the
 442 *               system, otherwise it is the physical address.
 443 *
 444 * @return
 445 *               - XST_SUCCESS if initialization was successful.
 446 *
 447 * @note         None.
 448 *
 449 ******************************************************************************/
 450 XStatus XResetPs_CfgInitialize(XResetPs *InstancePtr,
 451                                XResetPs_Config *ConfigPtr, u32 EffectiveAddress)
 452 {
 453         /* Arguments validation */
 454         Xil_AssertNonvoid(InstancePtr != NULL);
 455         Xil_AssertNonvoid(ConfigPtr != NULL);
 456
 457         /* Copying instance */
 458         InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
 459         InstancePtr->Config.BaseAddress = EffectiveAddress;
 460
 461         return XST_SUCCESS;
 462 }
 463
 464 #if !EL1_NONSECURE
 465 /****************************************************************************/
 466 /**
 467 *
 468 * Pulse Reset RPU.
 469 *
 470 * @param        None.
 471 *
 472 * @return
 473 *               - XST_SUCCESS if successful else error code.
 474 *
 475 * @note         The pulse reset sequence is referred from ug1085(v1.3)
 476 *               chapter-38. Few changes to the sequence are adpoted from PMUFW.
 477 *
 478 ******************************************************************************/
 479 static XStatus XResetPs_PulseResetRpuLs(void)
 480 {
 481         u32 TimeOut;
 482         u32 RegValue;
 483
 484         /* Block Cortex-R5 master interface */
 485         RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL);
 486         RegValue &= (~RPU_MASTER_ISO_MASK);
 487         RegValue |= RPU_MASTER_ISO_MASK;
 488         XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue);
 489
 490         /* Wait for acknowledgment from AIB until timeout */
 491         TimeOut = XRESETPS_AIB_PSPL_DELAY;
 492         RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_ACK_CTRL);
 493         while ((TimeOut > 0U) &&
 494                 ((RegValue & RPU_MASTER_ISO_MASK) != RPU_MASTER_ISO_MASK)) {
 495                 RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_ACK_CTRL);
 496                 TimeOut--;
 497         }
 498
 499         if (TimeOut == 0U) {
 500                 /*
 501                  * @NOTE:
 502                  * AIB ack Timed Out.
 503                  * As per ug1085(v1.3), nothing is to be done on timeout, hence
 504                  * continuing with reset sequence.
 505                  */
 506         }
 507
 508         /* Block Cortex-R5 slave interface */
 509         RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL);
 510         RegValue &= (~RPU_SLAVE_ISO_MASK);
 511         RegValue |= RPU_SLAVE_ISO_MASK;
 512         XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue);
 513
 514         /* Wait for acknowledgment from AIB until timeout */
 515         TimeOut = XRESETPS_AIB_PSPL_DELAY;
 516         RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_ACK_CTRL);
 517         while ((TimeOut > 0U) &&
 518                 ((RegValue & RPU_SLAVE_ISO_MASK) != RPU_SLAVE_ISO_MASK)) {
 519                 RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_ACK_CTRL);
 520                 TimeOut--;
 521         }
 522
 523         if (TimeOut == 0U) {
 524                 /*
 525                  * @NOTE:
 526                  * AIB ack Timed Out.
 527                  * As per ug1085(v1.3), nothing is to be done on timeout, hence
 528                  * continuing with reset sequence.
 529                  */
 530         }
 531
 532         /* Unblock Cortex-R5 master interface */
 533         RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL);
 534         RegValue &= (~RPU_MASTER_ISO_MASK);
 535         XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue);
 536
 537         /* Initiate Cortex-R5 LockStep reset */
 538         RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL);
 539         RegValue |= RPU_LS_RESET_MASK;
 540         XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue);
 541
 542         /* Wait */
 543         TimeOut = XRESETPS_RST_PROP_DELAY;
 544         while (TimeOut > 0U) {
 545                 TimeOut--;
 546         }
 547
 548         /* Release Cortex-R5 from Reset */
 549         RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL);
 550         RegValue &= (~RPU_LS_RESET_MASK);
 551         XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue);
 552
 553         /* Wait */
 554         TimeOut = XRESETPS_RST_PROP_DELAY;
 555         while (TimeOut > 0U) {
 556                 TimeOut--;
 557         }
 558
 559         /* Unblock Cortex-R5 slave interface */
 560         RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL);
 561         RegValue &= (~RPU_SLAVE_ISO_MASK);
 562         XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue);
 563
 564         return XST_SUCCESS;
 565 }
 566
 567 /****************************************************************************/
 568 /**
 569 *
 570 * Pulse Reset PS only.
 571 *
 572 * @param        None.
 573 *
 574 * @return
 575 *               - XST_SUCCESS if successful else error code.
 576 *
 577 * @note         The pulse reset sequence is referred from ug1085(v1.3)
 578 *               chapter-38. Few changes to the sequence are adpoted from PMUFW.
 579 *
 580 ******************************************************************************/
 581 static XStatus XResetPs_PulseResetPsOnly(void)
 582 {
 583
 584         u32 RegValue;
 585         u32 TimeOut;
 586         u8  ReconfirmAckCnt;
 587
 588         /* TODO: Set PMU Error to indicate to PL */
 589
 590         /* Block FPD to PL and LPD to PL interfaces with AIB (in PS) */
 591         XResetPs_WriteReg(XRESETPS_PMU_GLB_AIB_CTRL, AIB_ISO_CTRL_MASK);
 592
 593         /*
 594          * @NOTE: Updated referring PMUFW
 595          * There is a possibility of glitch in AIB ack signal to PMU, hence ack
 596          * needs reconfirmation.
 597          */
 598         /* Wait for AIB ack or Timeout */
 599         ReconfirmAckCnt = XRESETPS_AIB_PSPL_RECONFIRM_CNT;
 600         do {
 601                 TimeOut = XRESETPS_AIB_PSPL_DELAY;
 602                 RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_AIB_STATUS);
 603                 while ((TimeOut > 0U) &&
 604                     ((RegValue & AIB_ISO_STATUS_MASK) != AIB_ISO_STATUS_MASK)) {
 605                         RegValue =
 606                                   XResetPs_ReadReg(XRESETPS_PMU_GLB_AIB_STATUS);
 607                         TimeOut--;
 608                 }
 609
 610                 if (TimeOut == 0U) {
 611                         /*
 612                          * @NOTE:
 613                          * AIB ack Timed Out.
 614                          * As per ug1085(v1.3), nothing is to be done on
 615                          * timeout, hence continuing with reset sequence.
 616                          */
 617                         ReconfirmAckCnt = 0U;
 618                 } else {
 619                         ReconfirmAckCnt--;
 620                 }
 621         }
 622         while (ReconfirmAckCnt > 0U);
 623
 624         /*
 625          * @NOTE: Updated referring PMUFW.
 626          * Check if we are running Silicon version 1.0. If so,
 627          * bypass the RPLL before initiating the reset. This is
 628          * due to a bug in 1.0 Silicon wherein the PS hangs on a
 629          * reset if the RPLL is in use.
 630          */
 631         RegValue = XResetPs_ReadReg(XRESETPS_CSU_VERSION_REG);
 632         if (XRESETPS_PLATFORM_PS_VER1 == (RegValue & PS_VERSION_MASK)) {
 633                 RegValue = XResetPs_ReadReg(XRESETPS_CRL_APB_RPLL_CTRL);
 634                 RegValue |= RPLL_BYPASS_MASK;
 635                 XResetPs_WriteReg(XRESETPS_CRL_APB_RPLL_CTRL, RegValue);
 636         }
 637
 638         /* Block the propagation of the PROG signal to the PL */
 639         RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_PS_CTRL);
 640         RegValue &= (~PROG_ENABLE_MASK);
 641         XResetPs_WriteReg(XRESETPS_PMU_GLB_PS_CTRL, RegValue);
 642
 643         RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_PS_CTRL);
 644         RegValue |= PROG_GATE_MASK;
 645         XResetPs_WriteReg(XRESETPS_PMU_GLB_PS_CTRL, RegValue);
 646
 647         /* Initiate PS-only reset */
 648         RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL);
 649         RegValue |= PS_ONLY_RESET_MASK;
 650         XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue);
 651
 652         return XST_SUCCESS;
 653 }
 654
 655 /****************************************************************************/
 656 /**
 657 *
 658 * Pulse Reset FPD.
 659 *
 660 * @param        None.
 661 *
 662 * @return
 663 *               - XST_SUCCESS if successful else error code.
 664 *
 665 * @note         The pulse reset sequence is referred from ug1085(v1.3)
 666 *               chapter-38. Few changes to the sequence are adpoted from PMUFW.
 667 *
 668 ******************************************************************************/
 669 static XStatus XResetPs_PulseResetFpd(void)
 670 {
 671         u32 TimeOut;
 672         u32 RegValue;
 673
 674         /* Enable FPD to LPD isolations */
 675         RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL);
 676         RegValue &= (~FPD_TO_LPD_ISO_MASK);
 677         RegValue |= FPD_TO_LPD_ISO_MASK;
 678         XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue);
 679
 680         RegValue = XResetPs_ReadReg(XRESETPS_LPD_SLCR_APBISO_REQ_CTRL);
 681         RegValue |= GPU_ISO_MASK;
 682         XResetPs_WriteReg(XRESETPS_LPD_SLCR_APBISO_REQ_CTRL, RegValue);
 683
 684         /* Enable LPD to FPD isolations */
 685         RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL);
 686         RegValue &= (~LPD_TO_FPD_ISO_MASK);
 687         RegValue |= LPD_TO_FPD_ISO_MASK;
 688         XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue);
 689
 690         /*
 691          * Here we need to check for AIB ack, since nothing is done incase
 692          * ack is not received, we are just waiting for specified timeout
 693          * and continuing
 694          */
 695         TimeOut = XRESETPS_AIB_ISO_DELAY;
 696         while (TimeOut > 0U) {
 697                 TimeOut--;
 698         }
 699
 700         /* Initiate FPD reset */
 701         RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL);
 702         RegValue |= FPD_APU_RESET_MASK;
 703         XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue);
 704
 705         /* Wait till reset propagates */
 706         TimeOut = XRESETPS_RST_PROP_DELAY;
 707         while (TimeOut > 0U) {
 708                 TimeOut--;
 709         }
 710
 711         /* Disable FPD to LPD isolations */
 712         RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL);
 713         RegValue &= (~FPD_TO_LPD_ISO_MASK);
 714         XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue);
 715
 716         RegValue = XResetPs_ReadReg(XRESETPS_LPD_SLCR_APBISO_REQ_CTRL);
 717         RegValue &= (~GPU_ISO_MASK);
 718         XResetPs_WriteReg(XRESETPS_LPD_SLCR_APBISO_REQ_CTRL, RegValue);
 719
 720         /* Release from Reset and wait till it propagates */
 721         RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL);
 722         RegValue &= (~FPD_APU_RESET_MASK);
 723         XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue);
 724
 725         /* Wait till reset propagates */
 726         TimeOut = XRESETPS_RST_PROP_DELAY;
 727         while (TimeOut > 0U) {
 728                 TimeOut--;
 729         }
 730
 731         /* Disable LPD to FPD isolations */
 732         RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL);
 733         RegValue &= (~LPD_TO_FPD_ISO_MASK);
 734         XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue);
 735
 736         return XST_SUCCESS;
 737 }
 738 #endif
 739
 740 /****************************************************************************/
 741 /**
 742 *
 743 * Assert reset for specific peripheral based on reset ID.
 744 *
 745 * @param        InstancePtr is a pointer to the XResetPs instance.
 746 * @param        ResetID is the ID of the peripheral.
 747 *
 748 * @return
 749 *               - XST_SUCCESS if reset assertion was successful.
 750 *               - Error Code otherwise.
 751 *
 752 * @note         None.
 753 *
 754 ******************************************************************************/
 755 XStatus XResetPs_ResetAssert(XResetPs *InstancePtr,
 756                                                    const XResetPs_RstId ResetID)
 757 {
 758         /* Arguments validation */
 759         Xil_AssertNonvoid(InstancePtr != NULL);
 760         if ((ResetID > XRESETPS_RSTID_END) ||
 761                 (ResetID < XRESETPS_RSTID_START)) {
 762                 return XST_INVALID_PARAM;
 763         }
 764
 765 #if EL1_NONSECURE
 766         /* Assert reset via PMUFW */
 767         u64 SmcArgs;
 768         XSmc_OutVar out;
 769
 770         SmcArgs =  (u64)XRESETPS_RSTACT_ASSERT << 32;
 771         SmcArgs |= ((u64)(ResetID + XRESETPS_RSTID_BASE));
 772
 773         out = Xil_Smc(PM_ASSERT_SMC_FID, SmcArgs, 0, 0, 0, 0, 0, 0);
 774
 775         return ((u32)out.Arg0);
 776 #else
 777         u32 RegAddr;
 778         u32 RegBitmask;
 779         u32 RegValue;
 780
 781         /* Ignoring Nodes that doesnot support assert */
 782         if (!XRESETPS_CHK_ASSERT_SUPPORT(ResetMap[ResetID].SupportedActions)) {
 783                         return XST_NO_FEATURE;
 784         }
 785
 786         RegAddr = ResetMap[ResetID].SlcrregAddr;
 787         RegBitmask = ResetMap[ResetID].SlcrregBitmask;
 788
 789         /* Enable bit to assert reset */
 790         RegValue = XResetPs_ReadReg(RegAddr);
 791         RegValue |= RegBitmask;
 792         XResetPs_WriteReg(RegAddr, RegValue);
 793
 794         return XST_SUCCESS;
 795 #endif
 796 }
 797
 798 /****************************************************************************/
 799 /**
 800 *
 801 * Deassert reset for specific peripheral based on reset ID.
 802 *
 803 * @param        InstancePtr is a pointer to the XResetPs instance.
 804 * @param        ResetID is the ID of the peripheral.
 805 *
 806 * @return
 807 *               - XST_SUCCESS if reset deassertion was successful.
 808 *               - Error Code otherwise.
 809 *
 810 * @note         None.
 811 *
 812 ******************************************************************************/
 813 XStatus XResetPs_ResetDeassert(XResetPs *InstancePtr,
 814                                                    const XResetPs_RstId ResetID)
 815 {
 816         /* Arguments validation */
 817         Xil_AssertNonvoid(InstancePtr != NULL);
 818         if ((ResetID > XRESETPS_RSTID_END) ||
 819                 (ResetID < XRESETPS_RSTID_START)) {
 820                 return XST_INVALID_PARAM;
 821         }
 822
 823 #if EL1_NONSECURE
 824         /* Deassert reset via PMUFW */
 825         u64 SmcArgs;
 826         XSmc_OutVar out;
 827
 828         SmcArgs =  (u64)XRESETPS_RSTACT_RELEASE << 32;
 829         SmcArgs |= ((u64)(ResetID + XRESETPS_RSTID_BASE));
 830
 831         out = Xil_Smc(PM_ASSERT_SMC_FID, SmcArgs, 0, 0, 0, 0, 0, 0);
 832
 833         return ((u32)out.Arg0);
 834 #else
 835         u32 RegAddr;
 836         u32 RegBitmask;
 837         u32 RegValue;
 838
 839         /* Ignoring Nodes that does not support deassert */
 840         if (!XRESETPS_CHK_ASSERT_SUPPORT(ResetMap[ResetID].SupportedActions)) {
 841                         return XST_NO_FEATURE;
 842         }
 843
 844         RegAddr = ResetMap[ResetID].SlcrregAddr;
 845         RegBitmask = ResetMap[ResetID].SlcrregBitmask;
 846
 847         /* Disable bit to deassert reset */
 848         RegValue = XResetPs_ReadReg(RegAddr);
 849         RegValue &= (~RegBitmask);
 850         XResetPs_WriteReg(RegAddr, RegValue);
 851
 852         return XST_SUCCESS;
 853 #endif
 854 }
 855
 856 /****************************************************************************/
 857 /**
 858 *
 859 * Pulse reset for specific peripheral based on reset ID.
 860 *
 861 * @param        InstancePtr is a pointer to the XResetPs instance.
 862 * @param        ResetID is the ID of the peripheral.
 863 *
 864 * @return
 865 *               - XST_SUCCESS if pulse reset was successful.
 866 *               - Error Code otherwise.
 867 *
 868 * @note         None.
 869 *
 870 ******************************************************************************/
 871 XStatus XResetPs_ResetPulse(XResetPs *InstancePtr, const XResetPs_RstId ResetID)
 872 {
 873         /* Arguments validation */
 874         Xil_AssertNonvoid(InstancePtr != NULL);
 875         if ((ResetID > XRESETPS_RSTID_END) ||
 876                 (ResetID < XRESETPS_RSTID_START)) {
 877                 return XST_INVALID_PARAM;
 878         }
 879
 880 #if EL1_NONSECURE
 881         /* Pulse reset via PMUFW */
 882         u64 SmcArgs;
 883         XSmc_OutVar out;
 884
 885         SmcArgs =  (u64)XRESETPS_RSTACT_PULSE << 32;
 886         SmcArgs |= ((u64)(ResetID + XRESETPS_RSTID_BASE));
 887
 888         out = Xil_Smc(PM_ASSERT_SMC_FID, SmcArgs, 0, 0, 0, 0, 0, 0);
 889
 890         return ((u32)out.Arg0);
 891 #else
 892         u32 RegAddr;
 893         u32 RegBitmask;
 894         u32 RegValue;
 895         u32 TimeOut;
 896
 897         /* Ignoring Nodes that donot support pulse reset */
 898         if (!XRESETPS_CHK_PULSE_SUPPORT(ResetMap[ResetID].SupportedActions)) {
 899                         return XST_NO_FEATURE;
 900         }
 901
 902         /* Handling specific pulse resets */
 903         switch (ResetID) {
 904                 case XRESETPS_RSTID_FPD:
 905                         return XResetPs_PulseResetFpd();
 906                 case XRESETPS_RSTID_RPU_LS:
 907                         return XResetPs_PulseResetRpuLs();
 908                 case XRESETPS_RSTID_PS_ONLY:
 909                         return XResetPs_PulseResetPsOnly();
 910                 default:
 911                         break;
 912         }
 913
 914         RegAddr = ResetMap[ResetID].SlcrregAddr;
 915         RegBitmask = ResetMap[ResetID].SlcrregBitmask;
 916
 917         /* Power state mask validation */
 918         if ((ResetMap[ResetID].PulseType == XRESETPS_PT_DLY_PSCHK) &&
 919                 (ResetMap[ResetID].PwrStateBitmask != XRESETPS_BM_INVALID)) {
 920                 RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_PWR_STATUS);
 921                 if (ResetMap[ResetID].PwrStateBitmask !=
 922                         (RegValue && ResetMap[ResetID].PwrStateBitmask )) {
 923                         return XST_REGISTER_ERROR;
 924                 }
 925         }
 926
 927         /* Enable bit to assert reset */
 928         RegValue = XResetPs_ReadReg(RegAddr);
 929         RegValue |= RegBitmask;
 930         XResetPs_WriteReg(RegAddr, RegValue);
 931
 932         /* Wait for assert propogation */
 933         if (ResetMap[ResetID].PulseType != XRESETPS_PT_NO_DLY_NO_PSCHK) {
 934                 TimeOut = XRESETPS_PULSE_PROP_DELAY;
 935                 while (TimeOut > 0U) {
 936                         TimeOut--;
 937                 }
 938         }
 939
 940         /* Disable bit to deassert reset */
 941         RegValue = XResetPs_ReadReg(RegAddr);
 942         RegValue &= (~RegBitmask);
 943         XResetPs_WriteReg(RegAddr, RegValue);
 944
 945         /* Wait for release propogation */
 946         if (ResetMap[ResetID].PulseType != XRESETPS_PT_NO_DLY_NO_PSCHK) {
 947                 TimeOut = XRESETPS_PULSE_PROP_DELAY;
 948                 while (TimeOut > 0U) {
 949                         TimeOut--;
 950                 }
 951         }
 952
 953         return XST_SUCCESS;
 954 #endif
 955 }
 956
 957 /****************************************************************************/
 958 /**
 959 *
 960 * Get reset status for specific peripheral based on reset ID.
 961 *
 962 * @param        InstancePtr is a pointer to the XResetPs instance.
 963 * @param        ResetID is the ID of the peripheral.
 964 * @param        Status is the status of reset for ResetID.
 965 *               1 if asserted and 0 if released
 966 *
 967 * @return
 968 *               - XST_SUCCESS if status fetched successful.
 969 *               - Error Code otherwise.
 970 *
 971 * @note         None.
 972 *
 973 ******************************************************************************/
 974 XStatus XResetPs_ResetStatus(XResetPs *InstancePtr,
 975                        const XResetPs_RstId ResetID, XResetPs_RstStatus *Status)
 976 {
 977         /* Arguments validation */
 978         Xil_AssertNonvoid(InstancePtr != NULL);
 979         Xil_AssertNonvoid(Status != NULL);
 980         if ((ResetID > XRESETPS_RSTID_END) ||
 981                 (ResetID < XRESETPS_RSTID_START)) {
 982                 return XST_INVALID_PARAM;
 983         }
 984
 985 #if EL1_NONSECURE
 986         /* Get reset status via PMUFW */
 987         XSmc_OutVar out;
 988
 989         out = Xil_Smc(PM_GETSTATUS_SMC_FID,
 990                       ((u64)(ResetID + XRESETPS_RSTID_BASE)), 0, 0, 0, 0, 0, 0);
 991         *Status = ((u32)(out.Arg0 >> 32));
 992
 993         return ((u32)out.Arg0);
 994 #else
 995         u32 RegAddr;
 996         u32 RegBitmask;
 997         u32 RegValue;
 998
 999         /* Ignoring Nodes that donot support reset status */
1000         if (!XRESETPS_CHK_STATUS_SUPPORT(ResetMap[ResetID].SupportedActions)) {
1001                         return XST_NO_FEATURE;
1002         }
1003
1004         /*
1005          * @NOTE:
1006          * This will always move to else part as GPO3 are ignored because
1007          * XRESETPS_PMU_LCL_READ_CTRL is not accessible.
1008          */
1009         /* GPO3PL have status address different from control address */
1010         if ((ResetID >= XRESETPS_RSTID_GPO3PL0) &&
1011                         (ResetID <= XRESETPS_RSTID_GPO3PL31)) {
1012                 RegAddr = XRESETPS_PMU_LCL_READ_CTRL;
1013         } else {
1014                 RegAddr = ResetMap[ResetID].SlcrregAddr;
1015         }
1016
1017         RegBitmask = ResetMap[ResetID].SlcrregBitmask;
1018
1019         RegValue = XResetPs_ReadReg(RegAddr);
1020         if ((RegValue & RegBitmask) == RegBitmask) {
1021                 *Status = XRESETPS_RESETASSERTED;
1022         } else {
1023                 *Status = XRESETPS_RESETRELEASED;
1024         }
1025
1026         return XST_SUCCESS;
1027 #endif
1028 }
1029
1030 /** @} */