1 /******************************************************************************
3 * Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 * Except as contained in this notice, the name of the Xilinx shall not be used
28 * in advertising or otherwise to promote the sale, use or other dealings in
29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup sdps_v3_4
39 * Contains the interface functions of the XSdPs driver.
40 * See xsdps.h for a detailed description of the device and driver.
43 * MODIFICATION HISTORY:
45 * Ver Who Date Changes
46 * ----- --- -------- -----------------------------------------------
47 * 1.00a hk/sg 10/17/13 Initial release
48 * 2.0 hk 12/13/13 Added check for arm to use sleep.h and its API's
49 * 2.1 hk 04/18/14 Add sleep for microblaze designs. CR# 781117.
50 * 2.2 hk 07/28/14 Make changes to enable use of data cache.
51 * 2.3 sk 09/23/14 Send command for relative card address
52 * when re-initialization is done.CR# 819614.
53 * Use XSdPs_Change_ClkFreq API whenever changing
55 * 2.4 sk 12/04/14 Added support for micro SD without
57 * Checked for DAT Inhibit mask instead of CMD
58 * Inhibit mask in Cmd Transfer API.
59 * Added Support for SD Card v1.0
60 * 2.5 sg 07/09/15 Added SD 3.0 features
61 * kvn 07/15/15 Modified the code according to MISRAC-2012.
62 * 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
63 * 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
64 * sk 12/10/15 Added support for MMC cards.
65 * sk 02/16/16 Corrected the Tuning logic.
66 * sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
67 * 2.8 sk 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
68 * 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
69 * sk 07/16/16 Added support for UHS modes.
70 * sk 07/07/16 Used usleep API for both arm and microblaze.
71 * sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
73 * 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
74 * sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
75 * sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
76 * sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
77 * 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
78 * sk 02/01/17 Added HSD and DDR mode support for eMMC.
79 * vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
80 * sk 03/20/17 Add support for EL1 non-secure mode.
81 * 3.3 mn 05/17/17 Add support for 64bit DMA addressing
82 * mn 07/17/17 Add support for running SD at 200MHz
83 * mn 07/26/17 Fixed compilation warnings
84 * mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
85 * mn 08/17/17 Added CCI support for A53 and disabled data cache
86 * operations when it is enabled.
87 * mn 08/22/17 Updated for Word Access System support
88 * mn 09/06/17 Resolved compilation errors with IAR toolchain
89 * mn 09/26/17 Added UHS_MODE_ENABLE macro to enable UHS mode
90 * 3.4 mn 10/17/17 Use different commands for single and multi block
92 * mn 03/02/18 Move UHS macro check to SD card initialization routine
95 ******************************************************************************/
97 /***************************** Include Files *********************************/
101 /************************** Constant Definitions *****************************/
102 #define XSDPS_CMD8_VOL_PATTERN 0x1AAU
103 #define XSDPS_RESPOCR_READY 0x80000000U
104 #define XSDPS_ACMD41_HCS 0x40000000U
105 #define XSDPS_ACMD41_3V3 0x00300000U
106 #define XSDPS_CMD1_HIGH_VOL 0x00FF8000U
107 #define XSDPS_CMD1_DUAL_VOL 0x00FF8010U
108 #define HIGH_SPEED_SUPPORT 0x2U
109 #define UHS_SDR50_SUPPORT 0x4U
110 #define WIDTH_4_BIT_SUPPORT 0x4U
111 #define SD_CLK_25_MHZ 25000000U
112 #define SD_CLK_19_MHZ 19000000U
113 #define SD_CLK_26_MHZ 26000000U
114 #define EXT_CSD_DEVICE_TYPE_BYTE 196U
115 #define EXT_CSD_SEC_COUNT_BYTE1 212U
116 #define EXT_CSD_SEC_COUNT_BYTE2 213U
117 #define EXT_CSD_SEC_COUNT_BYTE3 214U
118 #define EXT_CSD_SEC_COUNT_BYTE4 215U
119 #define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U
120 #define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U
121 #define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U
122 #define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U
123 #define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U
124 #define CSD_SPEC_VER_3 0x3U
125 #define SCR_SPEC_VER_3 0x80U
127 /**************************** Type Definitions *******************************/
129 /***************** Macros (Inline Functions) Definitions *********************/
131 /************************** Function Prototypes ******************************/
132 u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd);
133 s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
134 void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
135 extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
136 static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr);
137 static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr);
140 /*****************************************************************************/
143 * Initializes a specific XSdPs instance such that the driver is ready to use.
146 * @param InstancePtr is a pointer to the XSdPs instance.
147 * @param ConfigPtr is a reference to a structure containing information
148 * about a specific SD device. This function initializes an
149 * InstancePtr object for a specific device specified by the
150 * contents of Config.
151 * @param EffectiveAddr is the device base address in the virtual memory
152 * address space. The caller is responsible for keeping the address
153 * mapping from EffectiveAddr to the device physical base address
154 * unchanged once this function is invoked. Unexpected errors may
155 * occur if the address mapping changes after this function is
156 * called. If address translation is not used, use
157 * ConfigPtr->Config.BaseAddress for this device.
160 * - XST_SUCCESS if successful.
161 * - XST_DEVICE_IS_STARTED if the device is already started.
162 * It must be stopped to re-initialize.
164 * @note This function initializes the host controller.
165 * Initial clock of 400KHz is set.
166 * Voltage of 3.3V is selected as that is supported by host.
167 * Interrupts status is enabled and signal disabled by default.
168 * Default data direction is card to host and
169 * 32 bit ADMA2 is selected. Defualt Block size is 512 bytes.
171 ******************************************************************************/
172 s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
179 Xil_AssertNonvoid(InstancePtr != NULL);
180 Xil_AssertNonvoid(ConfigPtr != NULL);
182 /* Set some default values. */
183 InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
184 InstancePtr->Config.BaseAddress = EffectiveAddr;
185 InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
186 InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
187 InstancePtr->Config.CardDetect = ConfigPtr->CardDetect;
188 InstancePtr->Config.WriteProtect = ConfigPtr->WriteProtect;
189 InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
190 InstancePtr->Config.BankNumber = ConfigPtr->BankNumber;
191 InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO;
192 InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent;
193 InstancePtr->SectorCount = 0;
194 InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
195 InstancePtr->Config_TapDelay = NULL;
197 /* Disable bus power and issue emmc hw reset */
198 if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
199 XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK) ==
201 XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
202 XSDPS_POWER_CTRL_OFFSET, XSDPS_PC_EMMC_HW_RST_MASK);
204 XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
205 XSDPS_POWER_CTRL_OFFSET, 0x0);
207 /* Delay to poweroff card */
210 /* "Software reset for all" is initiated */
211 XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
212 XSDPS_SWRST_ALL_MASK);
214 /* Proceed with initialization only after reset is complete */
215 ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
216 XSDPS_SW_RST_OFFSET);
217 while ((ReadReg & XSDPS_SWRST_ALL_MASK) != 0U) {
218 ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
219 XSDPS_SW_RST_OFFSET);
221 /* Host Controller version is read. */
222 InstancePtr->HC_Version =
223 (u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
224 XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
227 * Read capabilities register and update it in Instance pointer.
228 * It is sufficient to read this once on power on.
230 InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
233 /* Select voltage and enable bus power. */
234 if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
235 XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
236 XSDPS_POWER_CTRL_OFFSET,
237 (XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK) &
238 ~XSDPS_PC_EMMC_HW_RST_MASK);
240 XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
241 XSDPS_POWER_CTRL_OFFSET,
242 XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
244 /* Delay before issuing the command after emmc reset */
245 if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
246 if ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) ==
250 /* Change the clock frequency to 400 KHz */
251 Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
252 if (Status != XST_SUCCESS) {
253 Status = XST_FAILURE;
257 if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V3_MASK) != 0U) {
258 PowerLevel = XSDPS_PC_BUS_VSEL_3V3_MASK;
259 } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V0_MASK) != 0U) {
260 PowerLevel = XSDPS_PC_BUS_VSEL_3V0_MASK;
261 } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_1V8_MASK) != 0U) {
262 PowerLevel = XSDPS_PC_BUS_VSEL_1V8_MASK;
267 /* Select voltage based on capability and enable bus power. */
268 XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
269 XSDPS_POWER_CTRL_OFFSET,
270 PowerLevel | XSDPS_PC_BUS_PWR_MASK);
273 /* Enable ADMA2 in 64bit mode. */
274 XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
275 XSDPS_HOST_CTRL1_OFFSET,
276 XSDPS_HC_DMA_ADMA2_64_MASK);
278 /* Enable ADMA2 in 32bit mode. */
279 XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
280 XSDPS_HOST_CTRL1_OFFSET,
281 XSDPS_HC_DMA_ADMA2_32_MASK);
284 /* Enable all interrupt status except card interrupt initially */
285 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
286 XSDPS_NORM_INTR_STS_EN_OFFSET,
287 XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK));
289 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
290 XSDPS_ERR_INTR_STS_EN_OFFSET,
291 XSDPS_ERROR_INTR_ALL_MASK);
293 /* Disable all interrupt signals by default. */
294 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
295 XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0U);
296 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
297 XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0U);
300 * Transfer mode register - default value
301 * DMA enabled, block count enabled, data direction card to host(read)
303 TransferMode = XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
304 XSDPS_TM_DAT_DIR_SEL_MASK;
306 /* Set block size to 512 by default */
307 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
308 XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK);
310 Status = XST_SUCCESS;
317 /*****************************************************************************/
319 * SD initialization is done in this function
322 * @param InstancePtr is a pointer to the instance to be worked on.
325 * - XST_SUCCESS if initialization was successful
326 * - XST_FAILURE if failure - could be because
327 * a) SD is already initialized
328 * b) There is no card inserted
329 * c) One of the steps (commands) in the
330 initialization cycle failed
332 * @note This function initializes the SD card by following its
333 * initialization and identification state diagram.
334 * CMD0 is sent to reset card.
335 * CMD8 and ACDM41 are sent to identify voltage and
336 * high capacity support
337 * CMD2 and CMD3 are sent to obtain Card ID and
338 * Relative card address respectively.
339 * CMD9 is sent to read the card specific data.
341 ******************************************************************************/
342 s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
350 u32 BlkLen, DeviceSize, Mult;
352 Xil_AssertNonvoid(InstancePtr != NULL);
353 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
355 #ifndef UHS_MODE_ENABLE
356 InstancePtr->Config.BusWidth = XSDPS_WIDTH_4;
359 if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
360 ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
361 != XSDPS_CAPS_EMB_SLOT)) {
362 if(InstancePtr->Config.CardDetect != 0U) {
364 * Check the present state register to make sure
365 * card is inserted and detected by host controller
367 PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
368 XSDPS_PRES_STATE_OFFSET);
369 if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) {
370 Status = XST_FAILURE;
376 /* CMD0 no response expected */
377 Status = XSdPs_CmdTransfer(InstancePtr, (u32)CMD0, 0U, 0U);
378 if (Status != XST_SUCCESS) {
379 Status = XST_FAILURE;
384 * CMD8; response expected
385 * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern
387 Status = XSdPs_CmdTransfer(InstancePtr, CMD8,
388 XSDPS_CMD8_VOL_PATTERN, 0U);
389 if ((Status != XST_SUCCESS) && (Status != XSDPS_CT_ERROR)) {
390 Status = XST_FAILURE;
394 if (Status == XSDPS_CT_ERROR) {
395 /* "Software reset for all" is initiated */
396 XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
397 XSDPS_SWRST_CMD_LINE_MASK);
399 /* Proceed with initialization only after reset is complete */
400 ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
401 XSDPS_SW_RST_OFFSET);
402 while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
403 ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
404 XSDPS_SW_RST_OFFSET);
408 RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
410 if (RespOCR != XSDPS_CMD8_VOL_PATTERN) {
411 InstancePtr->Card_Version = XSDPS_SD_VER_1_0;
414 InstancePtr->Card_Version = XSDPS_SD_VER_2_0;
418 /* Send ACMD41 while card is still busy with power up */
419 while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
420 Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0U, 0U);
421 if (Status != XST_SUCCESS) {
422 Status = XST_FAILURE;
426 Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U);
428 * There is no support to switch to 1.8V and use UHS mode on
431 if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
432 #if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
433 (XGetPSVersion_Info() > XPS_VERSION_1) &&
435 (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
436 Arg |= XSDPS_OCR_S18;
439 /* 0x40300000 - Host High Capacity support & 3.3V window */
440 Status = XSdPs_CmdTransfer(InstancePtr, ACMD41,
442 if (Status != XST_SUCCESS) {
443 Status = XST_FAILURE;
447 /* Response with card capacity */
448 RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
453 /* Update HCS support flag based on card capacity response */
454 if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
455 InstancePtr->HCS = 1U;
458 if ((RespOCR & XSDPS_OCR_S18) != 0U) {
459 InstancePtr->Switch1v8 = 1U;
460 Status = XSdPs_Switch_Voltage(InstancePtr);
461 if (Status != XST_SUCCESS) {
462 Status = XST_FAILURE;
467 /* CMD2 for Card ID */
468 Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
469 if (Status != XST_SUCCESS) {
470 Status = XST_FAILURE;
474 InstancePtr->CardID[0] =
475 XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
477 InstancePtr->CardID[1] =
478 XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
480 InstancePtr->CardID[2] =
481 XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
483 InstancePtr->CardID[3] =
484 XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
487 Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0U, 0U);
488 if (Status != XST_SUCCESS) {
489 Status = XST_FAILURE;
494 * Relative card address is stored as the upper 16 bits
495 * This is to avoid shifting when sending commands
497 InstancePtr->RelCardAddr =
498 XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
499 XSDPS_RESP0_OFFSET) & 0xFFFF0000U;
500 } while (InstancePtr->RelCardAddr == 0U);
502 Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
503 if (Status != XST_SUCCESS) {
504 Status = XST_FAILURE;
509 * Card specific data is read.
510 * Currently not used for any operation.
512 CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
514 CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
516 CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
518 CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
521 if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 0U) {
522 BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
523 Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
524 DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
525 DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
526 DeviceSize = (DeviceSize + 1U) * Mult;
527 DeviceSize = DeviceSize * BlkLen;
528 InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
529 } else if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 1U) {
530 InstancePtr->SectorCount = (((CSD[1] & CSD_V2_C_SIZE_MASK) >> 8U) +
534 Status = XST_SUCCESS;
541 /*****************************************************************************/
544 * Initialize Card with Identification mode sequence
547 * @param InstancePtr is a pointer to the instance to be worked on.
550 * - XST_SUCCESS if initialization was successful
551 * - XST_FAILURE if failure - could be because
552 * a) SD is already initialized
553 * b) There is no card inserted
554 * c) One of the steps (commands) in the
555 * initialization cycle failed
558 ******************************************************************************/
559 s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
562 #pragma data_alignment = 32
563 static u8 ExtCsd[512];
565 #pragma data_alignment = 4
567 static u8 ExtCsd[512] __attribute__ ((aligned(32)));
568 u8 SCR[8] __attribute__ ((aligned(32))) = { 0U };
570 u8 ReadBuff[64] = { 0U };
574 Xil_AssertNonvoid(InstancePtr != NULL);
575 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
577 /* Default settings */
578 InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
579 InstancePtr->CardType = XSDPS_CARD_SD;
580 InstancePtr->Switch1v8 = 0U;
581 InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ;
583 if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
584 ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
585 == XSDPS_CAPS_EMB_SLOT)) {
586 InstancePtr->CardType = XSDPS_CHIP_EMMC;
588 Status = XSdPs_IdentifyCard(InstancePtr);
589 if (Status == XST_FAILURE) {
594 if ((InstancePtr->CardType != XSDPS_CARD_SD) &&
595 (InstancePtr->CardType != XSDPS_CARD_MMC) &&
596 (InstancePtr->CardType != XSDPS_CHIP_EMMC)) {
597 Status = XST_FAILURE;
601 if (InstancePtr->CardType == XSDPS_CARD_SD) {
602 Status = XSdPs_SdCardInitialize(InstancePtr);
603 if (Status != XST_SUCCESS) {
604 Status = XST_FAILURE;
608 /* Change clock to default clock 25MHz */
610 * SD default speed mode timing should be closed at 19 MHz.
611 * The reason for this is SD requires a voltage level shifter.
612 * This limitation applies to ZynqMPSoC.
614 if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
615 InstancePtr->BusSpeed = SD_CLK_19_MHZ;
617 InstancePtr->BusSpeed = SD_CLK_25_MHZ;
618 Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
619 if (Status != XST_SUCCESS) {
620 Status = XST_FAILURE;
624 } else if ((InstancePtr->CardType == XSDPS_CARD_MMC)
625 || (InstancePtr->CardType == XSDPS_CHIP_EMMC)) {
626 Status = XSdPs_MmcCardInitialize(InstancePtr);
627 if (Status != XST_SUCCESS) {
628 Status = XST_FAILURE;
631 /* Change clock to default clock 26MHz */
632 InstancePtr->BusSpeed = SD_CLK_26_MHZ;
633 Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
634 if (Status != XST_SUCCESS) {
635 Status = XST_FAILURE;
639 Status = XST_FAILURE;
643 Status = XSdPs_Select_Card(InstancePtr);
644 if (Status != XST_SUCCESS) {
645 Status = XST_FAILURE;
649 if (InstancePtr->CardType == XSDPS_CARD_SD) {
650 /* Pull-up disconnected during data transfer */
651 Status = XSdPs_Pullup(InstancePtr);
652 if (Status != XST_SUCCESS) {
653 Status = XST_FAILURE;
657 Status = XSdPs_Get_BusWidth(InstancePtr, SCR);
658 if (Status != XST_SUCCESS) {
659 Status = XST_FAILURE;
663 if ((SCR[1] & WIDTH_4_BIT_SUPPORT) != 0U) {
664 Status = XSdPs_Change_BusWidth(InstancePtr);
665 if (Status != XST_SUCCESS) {
666 Status = XST_FAILURE;
671 /* Get speed supported by device */
672 Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff);
673 if (Status != XST_SUCCESS) {
677 if (((SCR[2] & SCR_SPEC_VER_3) != 0U) &&
678 (ReadBuff[13] >= UHS_SDR50_SUPPORT) &&
679 (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8) &&
680 #if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
681 (XGetPSVersion_Info() > XPS_VERSION_1) &&
683 (InstancePtr->Switch1v8 == 0U)) {
684 u16 CtrlReg, ClockReg;
687 CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
688 XSDPS_CLK_CTRL_OFFSET);
689 CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
690 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
693 /* Enabling 1.8V in controller */
694 CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
695 XSDPS_HOST_CTRL2_OFFSET);
696 CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
697 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
700 /* Wait minimum 5mSec */
703 /* Check for 1.8V signal enable bit is cleared by Host */
704 CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
705 XSDPS_HOST_CTRL2_OFFSET);
706 if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) {
707 Status = XST_FAILURE;
711 /* Wait for internal clock to stabilize */
712 ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
713 XSDPS_CLK_CTRL_OFFSET);
714 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
715 XSDPS_CLK_CTRL_OFFSET,
716 ClockReg | XSDPS_CC_INT_CLK_EN_MASK);
717 ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
718 XSDPS_CLK_CTRL_OFFSET);
719 while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
720 ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
721 XSDPS_CLK_CTRL_OFFSET);
724 /* Enable SD clock */
725 ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
726 XSDPS_CLK_CTRL_OFFSET);
727 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
728 XSDPS_CLK_CTRL_OFFSET,
729 ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
734 InstancePtr->Switch1v8 = 1U;
737 #if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
738 if (InstancePtr->Switch1v8 != 0U) {
740 /* Identify the UHS mode supported by card */
741 XSdPs_Identify_UhsMode(InstancePtr, ReadBuff);
743 /* Set UHS-I SDR104 mode */
744 Status = XSdPs_Uhs_ModeInit(InstancePtr, InstancePtr->Mode);
745 if (Status != XST_SUCCESS) {
752 * card supports CMD6 when SD_SPEC field in SCR register
753 * indicates that the Physical Layer Specification Version
754 * is 1.10 or later. So for SD v1.0 cmd6 is not supported.
757 /* Check for high speed support */
758 if (((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) &&
759 (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
760 InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
761 #if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
762 InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
764 Status = XSdPs_Change_BusSpeed(InstancePtr);
765 if (Status != XST_SUCCESS) {
766 Status = XST_FAILURE;
771 #if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
775 } else if (((InstancePtr->CardType == XSDPS_CARD_MMC) &&
776 (InstancePtr->Card_Version > CSD_SPEC_VER_3)) &&
777 (InstancePtr->HC_Version == XSDPS_HC_SPEC_V2)) {
779 Status = XSdPs_Change_BusWidth(InstancePtr);
780 if (Status != XST_SUCCESS) {
781 Status = XST_FAILURE;
785 Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
786 if (Status != XST_SUCCESS) {
787 Status = XST_FAILURE;
791 InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
792 InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
793 InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
794 InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
796 if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
797 EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
798 (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
799 InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
800 Status = XSdPs_Change_BusSpeed(InstancePtr);
801 if (Status != XST_SUCCESS) {
802 Status = XST_FAILURE;
806 Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
807 if (Status != XST_SUCCESS) {
808 Status = XST_FAILURE;
812 if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
813 Status = XST_FAILURE;
817 } else if (InstancePtr->CardType == XSDPS_CHIP_EMMC){
818 /* Change bus width to 8-bit */
819 Status = XSdPs_Change_BusWidth(InstancePtr);
820 if (Status != XST_SUCCESS) {
821 Status = XST_FAILURE;
825 /* Get Extended CSD */
826 Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
827 if (Status != XST_SUCCESS) {
828 Status = XST_FAILURE;
832 InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
833 InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
834 InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
835 InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
837 /* Check for card supported speed */
838 if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
839 (EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 |
840 EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) &&
841 (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
842 InstancePtr->Mode = XSDPS_HS200_MODE;
843 #if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
844 InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
846 } else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
847 (EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED |
848 EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED)) != 0U) &&
849 (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
850 InstancePtr->Mode = XSDPS_DDR52_MODE;
851 #if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
852 InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay;
854 } else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
855 EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
856 (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
857 InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
858 #if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
859 InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
862 InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
864 if (InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) {
865 Status = XSdPs_Change_BusSpeed(InstancePtr);
866 if (Status != XST_SUCCESS) {
867 Status = XST_FAILURE;
871 Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
872 if (Status != XST_SUCCESS) {
873 Status = XST_FAILURE;
877 if (InstancePtr->Mode == XSDPS_HS200_MODE) {
878 if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) {
879 Status = XST_FAILURE;
884 if ((InstancePtr->Mode == XSDPS_HIGH_SPEED_MODE) ||
885 InstancePtr->Mode == XSDPS_DDR52_MODE) {
886 if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
887 Status = XST_FAILURE;
891 if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
892 Status = XSdPs_Change_BusWidth(InstancePtr);
893 if (Status != XST_SUCCESS) {
894 Status = XST_FAILURE;
901 /* Enable Rst_n_Fun bit if it is disabled */
902 if(ExtCsd[EXT_CSD_RST_N_FUN_BYTE] == EXT_CSD_RST_N_FUN_TEMP_DIS) {
903 Arg = XSDPS_MMC_RST_FUN_EN_ARG;
904 Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg);
905 if (Status != XST_SUCCESS) {
906 Status = XST_FAILURE;
911 if ((InstancePtr->Mode != XSDPS_DDR52_MODE) ||
912 (InstancePtr->CardType == XSDPS_CARD_SD)) {
913 Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
914 if (Status != XST_SUCCESS) {
915 Status = XST_FAILURE;
924 /*****************************************************************************/
927 * Identify type of card using CMD0 + CMD1 sequence
930 * @param InstancePtr is a pointer to the XSdPs instance.
932 ******************************************************************************/
933 static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr)
938 Xil_AssertNonvoid(InstancePtr != NULL);
939 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
941 /* 74 CLK delay after card is powered up, before the first command. */
942 usleep(XSDPS_INIT_DELAY);
944 /* CMD0 no response expected */
945 Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
946 if (Status != XST_SUCCESS) {
947 Status = XST_FAILURE;
951 /* Host High Capacity support & High voltage window */
952 Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
953 XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
954 if (Status != XST_SUCCESS) {
955 InstancePtr->CardType = XSDPS_CARD_SD;
957 InstancePtr->CardType = XSDPS_CARD_MMC;
960 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
961 XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
962 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
963 XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
965 /* "Software reset for all" is initiated */
966 XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
967 XSDPS_SWRST_CMD_LINE_MASK);
969 /* Proceed with initialization only after reset is complete */
970 ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
971 XSDPS_SW_RST_OFFSET);
972 while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
973 ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
974 XSDPS_SW_RST_OFFSET);
977 Status = XST_SUCCESS;
983 /*****************************************************************************/
986 * Switches the SD card voltage from 3v3 to 1v8
989 * @param InstancePtr is a pointer to the XSdPs instance.
991 ******************************************************************************/
992 static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
996 u32 ReadReg, ClockReg;
998 /* Send switch voltage command */
999 Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U);
1000 if (Status != XST_SUCCESS) {
1001 Status = XST_FAILURE;
1004 /* Wait for CMD and DATA line to go low */
1005 ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
1006 XSDPS_PRES_STATE_OFFSET);
1007 while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK |
1008 XSDPS_PSR_DAT30_SG_LVL_MASK)) != 0U) {
1009 ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
1010 XSDPS_PRES_STATE_OFFSET);
1013 /* Stop the clock */
1014 CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
1015 XSDPS_CLK_CTRL_OFFSET);
1016 CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
1017 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
1020 /* Enabling 1.8V in controller */
1021 CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
1022 XSDPS_HOST_CTRL2_OFFSET);
1023 CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
1024 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
1027 /* Wait minimum 5mSec */
1028 (void)usleep(5000U);
1030 /* Check for 1.8V signal enable bit is cleared by Host */
1031 CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
1032 XSDPS_HOST_CTRL2_OFFSET);
1033 if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) {
1034 Status = XST_FAILURE;
1038 /* Wait for internal clock to stabilize */
1039 ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
1040 XSDPS_CLK_CTRL_OFFSET);
1041 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
1042 XSDPS_CLK_CTRL_OFFSET,
1043 ClockReg | XSDPS_CC_INT_CLK_EN_MASK);
1044 ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
1045 XSDPS_CLK_CTRL_OFFSET);
1046 while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
1047 ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
1048 XSDPS_CLK_CTRL_OFFSET);
1051 /* Enable SD clock */
1052 ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
1053 XSDPS_CLK_CTRL_OFFSET);
1054 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
1055 XSDPS_CLK_CTRL_OFFSET,
1056 ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
1058 /* Wait for 1mSec */
1059 (void)usleep(1000U);
1061 /* Wait for CMD and DATA line to go high */
1062 ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
1063 XSDPS_PRES_STATE_OFFSET);
1064 while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK))
1065 != (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) {
1066 ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
1067 XSDPS_PRES_STATE_OFFSET);
1074 /*****************************************************************************/
1077 * This function does SD command generation.
1079 * @param InstancePtr is a pointer to the instance to be worked on.
1080 * @param Cmd is the command to be sent.
1081 * @param Arg is the argument to be sent along with the command.
1082 * This could be address or any other information
1083 * @param BlkCnt - Block count passed by the user.
1086 * - XST_SUCCESS if initialization was successful
1087 * - XST_FAILURE if failure - could be because another transfer
1088 * is in progress or command or data inhibit is set
1090 ******************************************************************************/
1091 s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt)
1093 u32 PresentStateReg;
1098 Xil_AssertNonvoid(InstancePtr != NULL);
1099 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
1102 * Check the command inhibit to make sure no other
1103 * command transfer is in progress
1105 PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
1106 XSDPS_PRES_STATE_OFFSET);
1107 if ((PresentStateReg & XSDPS_PSR_INHIBIT_CMD_MASK) != 0U) {
1108 Status = XST_FAILURE;
1112 /* Write block count register */
1113 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
1114 XSDPS_BLK_CNT_OFFSET, (u16)BlkCnt);
1116 XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
1117 XSDPS_TIMEOUT_CTRL_OFFSET, 0xEU);
1119 /* Write argument register */
1120 XSdPs_WriteReg(InstancePtr->Config.BaseAddress,
1121 XSDPS_ARGMT_OFFSET, Arg);
1123 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
1124 XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
1125 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
1126 XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
1127 /* Command register is set to trigger transfer of command */
1128 CommandReg = XSdPs_FrameCmd(InstancePtr, Cmd);
1131 * Mask to avoid writing to reserved bits 31-30
1132 * This is necessary because 0x80000000 is used by this software to
1133 * distinguish between ACMD and CMD of same number
1135 CommandReg = CommandReg & 0x3FFFU;
1138 * Check for data inhibit in case of command using DAT lines.
1139 * For Tuning Commands DAT lines check can be ignored.
1141 if ((Cmd != CMD21) && (Cmd != CMD19)) {
1142 PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
1143 XSDPS_PRES_STATE_OFFSET);
1144 if (((PresentStateReg & (XSDPS_PSR_INHIBIT_DAT_MASK |
1145 XSDPS_PSR_INHIBIT_DAT_MASK)) != 0U) &&
1146 ((CommandReg & XSDPS_DAT_PRESENT_SEL_MASK) != 0U)) {
1147 Status = XST_FAILURE;
1152 XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
1153 (CommandReg << 16) | TransferMode);
1155 /* Polling for response for now */
1157 StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
1158 XSDPS_NORM_INTR_STS_OFFSET);
1159 if ((Cmd == CMD21) || (Cmd == CMD19)) {
1160 if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
1161 XSDPS_NORM_INTR_STS_OFFSET) & XSDPS_INTR_BRR_MASK) != 0U){
1162 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
1163 XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_BRR_MASK);
1168 if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
1169 Status = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
1170 XSDPS_ERR_INTR_STS_OFFSET);
1171 if ((Status & ~XSDPS_INTR_ERR_CT_MASK) == 0) {
1172 Status = XSDPS_CT_ERROR;
1174 /* Write to clear error bits */
1175 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
1176 XSDPS_ERR_INTR_STS_OFFSET,
1177 XSDPS_ERROR_INTR_ALL_MASK);
1180 } while((StatusReg & XSDPS_INTR_CC_MASK) == 0U);
1181 /* Write to clear bit */
1182 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
1183 XSDPS_NORM_INTR_STS_OFFSET,
1184 XSDPS_INTR_CC_MASK);
1186 Status = XST_SUCCESS;
1193 /*****************************************************************************/
1195 * This function frames the Command register for a particular command.
1196 * Note that this generates only the command register value i.e.
1197 * the upper 16 bits of the transfer mode and command register.
1198 * This value is already shifted to be upper 16 bits and can be directly
1199 * OR'ed with transfer mode register value.
1201 * @param Command to be sent.
1203 * @return Command register value complete with response type and
1204 * data, CRC and index related flags.
1206 ******************************************************************************/
1207 u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd)
1215 RetVal |= RESP_NONE;
1227 RetVal |= RESP_NONE;
1233 if (InstancePtr->CardType == XSDPS_CARD_SD) {
1234 RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
1246 if (InstancePtr->CardType == XSDPS_CARD_SD) {
1249 RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
1266 RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
1272 RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
1280 RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
1296 /*****************************************************************************/
1298 * This function performs SD read in polled mode.
1300 * @param InstancePtr is a pointer to the instance to be worked on.
1301 * @param Arg is the address passed by the user that is to be sent as
1302 * argument along with the command.
1303 * @param BlkCnt - Block count passed by the user.
1304 * @param Buff - Pointer to the data buffer for a DMA transfer.
1307 * - XST_SUCCESS if initialization was successful
1308 * - XST_FAILURE if failure - could be because another transfer
1309 * is in progress or command or data inhibit is set
1311 ******************************************************************************/
1312 s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
1315 u32 PresentStateReg;
1318 if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
1319 ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
1320 != XSDPS_CAPS_EMB_SLOT)) {
1321 if(InstancePtr->Config.CardDetect != 0U) {
1322 /* Check status to ensure card is initialized */
1323 PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
1324 XSDPS_PRES_STATE_OFFSET);
1325 if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
1326 Status = XST_FAILURE;
1332 /* Set block size to 512 if not already set */
1333 if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
1334 XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
1335 Status = XSdPs_SetBlkSize(InstancePtr,
1336 XSDPS_BLK_SIZE_512_MASK);
1337 if (Status != XST_SUCCESS) {
1338 Status = XST_FAILURE;
1343 XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
1344 if (InstancePtr->Config.IsCacheCoherent == 0) {
1345 Xil_DCacheInvalidateRange((INTPTR)Buff,
1346 BlkCnt * XSDPS_BLK_SIZE_512_MASK);
1350 TransferMode = XSDPS_TM_BLK_CNT_EN_MASK |
1351 XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
1353 /* Send single block read command */
1354 Status = XSdPs_CmdTransfer(InstancePtr, CMD17, Arg, BlkCnt);
1355 if (Status != XST_SUCCESS) {
1356 Status = XST_FAILURE;
1360 TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
1361 XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK |
1362 XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK;
1364 /* Send multiple blocks read command */
1365 Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
1366 if (Status != XST_SUCCESS) {
1367 Status = XST_FAILURE;
1372 /* Check for transfer complete */
1374 StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
1375 XSDPS_NORM_INTR_STS_OFFSET);
1376 if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
1377 /* Write to clear error bits */
1378 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
1379 XSDPS_ERR_INTR_STS_OFFSET,
1380 XSDPS_ERROR_INTR_ALL_MASK);
1381 Status = XST_FAILURE;
1384 } while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
1386 /* Write to clear bit */
1387 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
1388 XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
1389 Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
1390 XSDPS_RESP0_OFFSET);
1392 Status = XST_SUCCESS;
1398 /*****************************************************************************/
1400 * This function performs SD write in polled mode.
1402 * @param InstancePtr is a pointer to the instance to be worked on.
1403 * @param Arg is the address passed by the user that is to be sent as
1404 * argument along with the command.
1405 * @param BlkCnt - Block count passed by the user.
1406 * @param Buff - Pointer to the data buffer for a DMA transfer.
1409 * - XST_SUCCESS if initialization was successful
1410 * - XST_FAILURE if failure - could be because another transfer
1411 * is in progress or command or data inhibit is set
1413 ******************************************************************************/
1414 s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
1417 u32 PresentStateReg;
1420 if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
1421 ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
1422 != XSDPS_CAPS_EMB_SLOT)) {
1423 if(InstancePtr->Config.CardDetect != 0U) {
1424 /* Check status to ensure card is initialized */
1425 PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
1426 XSDPS_PRES_STATE_OFFSET);
1427 if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
1428 Status = XST_FAILURE;
1434 /* Set block size to 512 if not already set */
1435 if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
1436 XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
1437 Status = XSdPs_SetBlkSize(InstancePtr,
1438 XSDPS_BLK_SIZE_512_MASK);
1439 if (Status != XST_SUCCESS) {
1440 Status = XST_FAILURE;
1446 XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
1447 if (InstancePtr->Config.IsCacheCoherent == 0) {
1448 Xil_DCacheFlushRange((INTPTR)Buff,
1449 BlkCnt * XSDPS_BLK_SIZE_512_MASK);
1453 TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DMA_EN_MASK;
1455 /* Send single block write command */
1456 Status = XSdPs_CmdTransfer(InstancePtr, CMD24, Arg, BlkCnt);
1457 if (Status != XST_SUCCESS) {
1458 Status = XST_FAILURE;
1462 TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
1463 XSDPS_TM_BLK_CNT_EN_MASK |
1464 XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
1466 /* Send multiple blocks write command */
1467 Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
1468 if (Status != XST_SUCCESS) {
1469 Status = XST_FAILURE;
1475 * Check for transfer complete
1476 * Polling for response for now
1479 StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
1480 XSDPS_NORM_INTR_STS_OFFSET);
1481 if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
1482 /* Write to clear error bits */
1483 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
1484 XSDPS_ERR_INTR_STS_OFFSET,
1485 XSDPS_ERROR_INTR_ALL_MASK);
1486 Status = XST_FAILURE;
1489 } while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
1491 /* Write to clear bit */
1492 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
1493 XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
1495 Status = XST_SUCCESS;
1501 /*****************************************************************************/
1504 * Selects card and sets default block size
1507 * @param InstancePtr is a pointer to the XSdPs instance.
1510 * - XST_SUCCESS if successful.
1511 * - XST_FAILURE if fail.
1515 ******************************************************************************/
1516 s32 XSdPs_Select_Card (XSdPs *InstancePtr)
1520 /* Send CMD7 - Select card */
1521 Status = XSdPs_CmdTransfer(InstancePtr, CMD7,
1522 InstancePtr->RelCardAddr, 0U);
1523 if (Status != XST_SUCCESS) {
1524 Status = XST_FAILURE;
1533 /*****************************************************************************/
1536 * API to setup ADMA2 descriptor table
1539 * @param InstancePtr is a pointer to the XSdPs instance.
1540 * @param BlkCnt - block count.
1541 * @param Buff pointer to data buffer.
1547 ******************************************************************************/
1548 void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
1550 u32 TotalDescLines = 0U;
1554 /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
1555 BlkSize = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
1556 XSDPS_BLK_SIZE_OFFSET);
1557 BlkSize = BlkSize & XSDPS_BLK_SIZE_MASK;
1559 if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
1561 TotalDescLines = 1U;
1565 TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
1566 if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
1567 TotalDescLines += 1U;
1572 for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
1574 InstancePtr->Adma2_DescrTbl[DescNum].Address =
1575 (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
1577 InstancePtr->Adma2_DescrTbl[DescNum].Address =
1578 (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
1580 InstancePtr->Adma2_DescrTbl[DescNum].Attribute =
1581 XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
1582 /* This will write '0' to length field which indicates 65536 */
1583 InstancePtr->Adma2_DescrTbl[DescNum].Length =
1584 (u16)XSDPS_DESC_MAX_LENGTH;
1588 InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
1589 (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
1591 InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
1592 (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
1595 InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute =
1596 XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
1598 InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length =
1599 (u16)((BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH));
1602 XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_EXT_OFFSET,
1603 (u32)(((u64)&(InstancePtr->Adma2_DescrTbl[0]))>>32));
1606 XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
1607 (u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]));
1609 if (InstancePtr->Config.IsCacheCoherent == 0) {
1610 Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]),
1611 sizeof(XSdPs_Adma2Descriptor) * 32U);
1615 /*****************************************************************************/
1617 * Mmc initialization is done in this function
1620 * @param InstancePtr is a pointer to the instance to be worked on.
1623 * - XST_SUCCESS if initialization was successful
1624 * - XST_FAILURE if failure - could be because
1625 * a) MMC is already initialized
1626 * b) There is no card inserted
1627 * c) One of the steps (commands) in the initialization
1629 * @note This function initializes the SD card by following its
1630 * initialization and identification state diagram.
1631 * CMD0 is sent to reset card.
1632 * CMD1 sent to identify voltage and high capacity support
1633 * CMD2 and CMD3 are sent to obtain Card ID and
1634 * Relative card address respectively.
1635 * CMD9 is sent to read the card specific data.
1637 ******************************************************************************/
1638 s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
1640 u32 PresentStateReg;
1644 u32 BlkLen, DeviceSize, Mult;
1646 Xil_AssertNonvoid(InstancePtr != NULL);
1647 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
1649 if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
1650 ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
1651 != XSDPS_CAPS_EMB_SLOT)) {
1652 if(InstancePtr->Config.CardDetect != 0U) {
1654 * Check the present state register to make sure
1655 * card is inserted and detected by host controller
1657 PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
1658 XSDPS_PRES_STATE_OFFSET);
1659 if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) {
1660 Status = XST_FAILURE;
1666 /* CMD0 no response expected */
1667 Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
1668 if (Status != XST_SUCCESS) {
1669 Status = XST_FAILURE;
1674 /* Send CMD1 while card is still busy with power up */
1675 while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
1677 /* Host High Capacity support & High volage window */
1678 Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
1679 XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
1680 if (Status != XST_SUCCESS) {
1681 Status = XST_FAILURE;
1685 /* Response with card capacity */
1686 RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
1687 XSDPS_RESP0_OFFSET);
1691 /* Update HCS support flag based on card capacity response */
1692 if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
1693 InstancePtr->HCS = 1U;
1696 /* CMD2 for Card ID */
1697 Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
1698 if (Status != XST_SUCCESS) {
1699 Status = XST_FAILURE;
1703 InstancePtr->CardID[0] =
1704 XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
1705 XSDPS_RESP0_OFFSET);
1706 InstancePtr->CardID[1] =
1707 XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
1708 XSDPS_RESP1_OFFSET);
1709 InstancePtr->CardID[2] =
1710 XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
1711 XSDPS_RESP2_OFFSET);
1712 InstancePtr->CardID[3] =
1713 XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
1714 XSDPS_RESP3_OFFSET);
1716 /* Set relative card address */
1717 InstancePtr->RelCardAddr = 0x12340000U;
1718 Status = XSdPs_CmdTransfer(InstancePtr, CMD3, (InstancePtr->RelCardAddr), 0U);
1719 if (Status != XST_SUCCESS) {
1720 Status = XST_FAILURE;
1724 Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
1725 if (Status != XST_SUCCESS) {
1726 Status = XST_FAILURE;
1731 * Card specific data is read.
1732 * Currently not used for any operation.
1734 CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
1735 XSDPS_RESP0_OFFSET);
1736 CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
1737 XSDPS_RESP1_OFFSET);
1738 CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
1739 XSDPS_RESP2_OFFSET);
1740 CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
1741 XSDPS_RESP3_OFFSET);
1743 InstancePtr->Card_Version = (CSD[3] & CSD_SPEC_VER_MASK) >>18U;
1745 /* Calculating the memory capacity */
1746 BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
1747 Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
1748 DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
1749 DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
1750 DeviceSize = (DeviceSize + 1U) * Mult;
1751 DeviceSize = DeviceSize * BlkLen;
1753 InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
1755 Status = XST_SUCCESS;