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31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup sdps_v3_4
39 * This header file contains the identifiers and basic HW access driver
40 * functions (or macros) that can be used to access the device. Other driver
41 * functions are defined in xsdps.h.
44 * MODIFICATION HISTORY:
46 * Ver Who Date Changes
47 * ----- --- -------- -----------------------------------------------
48 * 1.00a hk/sg 10/17/13 Initial release
49 * 2.5 sg 07/09/15 Added SD 3.0 features
50 * kvn 07/15/15 Modified the code according to MISRAC-2012.
51 * 2.7 sk 12/10/15 Added support for MMC cards.
52 * sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
53 * 2.8 sk 04/20/16 Added new workaround for auto tuning.
54 * 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
55 * sk 07/16/16 Added support for UHS modes.
56 * sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
58 * 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
59 * 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
60 * 3.3 mn 08/22/17 Updated for Word Access System support
61 * mn 09/06/17 Added support for ARMCC toolchain
62 * 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
66 ******************************************************************************/
75 /***************************** Include Files *********************************/
77 #include "xil_types.h"
78 #include "xil_assert.h"
80 #include "xparameters.h"
82 /************************** Constant Definitions *****************************/
84 /** @name Register Map
86 * Register offsets from the base address of an SD device.
90 #define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address
92 #define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET
93 /**< SDMA System Address
95 #define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */
96 #define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address
98 #define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */
100 #define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */
101 #define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */
102 #define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */
103 #define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET
104 /**< Argument1 Register */
105 #define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */
107 #define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */
108 #define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */
109 #define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */
110 #define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */
111 #define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */
112 #define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */
113 #define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */
114 #define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */
115 #define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */
116 #define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */
117 #define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */
118 #define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */
119 #define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */
120 #define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */
121 #define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */
122 #define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt
124 #define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt
126 #define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt
127 Status Enable Register */
128 #define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt
129 Status Enable Register */
130 #define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt
131 Signal Enable Register */
132 #define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt
133 Signal Enable Register */
135 #define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status
137 #define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */
138 #define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */
139 #define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */
140 #define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current
141 Capabilities Register */
142 #define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current
143 Capabilities Ext Register */
144 #define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for
145 Error Interrupt Status */
146 #define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt
148 #define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status
150 #define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address
152 #define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address
154 #define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */
155 #define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */
156 #define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */
157 #define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */
158 #define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control
161 #define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control
163 #define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status
165 #define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version
170 /** @name Control Register - Host control, Power control,
171 * Block Gap control and Wakeup control
173 * This register contains bits for various configuration options of
174 * the SD host controller. Read/Write apart from the reserved bits.
178 #define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */
179 #define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */
180 #define XSDPS_HC_BUS_WIDTH_4 0x00000002U
181 #define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */
182 #define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */
183 #define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */
184 #define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */
185 #define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */
186 #define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */
187 #define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */
188 #define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */
189 #define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */
191 #define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */
192 #define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */
193 #define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */
194 #define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */
195 #define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */
196 #define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */
198 #define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */
199 #define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */
200 #define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */
201 #define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */
202 #define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */
203 #define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */
204 #define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */
205 #define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */
207 #define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */
208 #define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */
209 #define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */
213 /** @name Control Register - Clock control, Timeout control & Software reset
215 * This register contains bits for configuration options of clock, timeout and
217 * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
221 #define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U
222 #define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U
223 #define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U
224 #define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U
225 #define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x000000C0U
226 #define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x0000FF00U
227 #define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U
228 #define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U
229 #define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U
230 #define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U
231 #define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U
232 #define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U
233 #define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U
234 #define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U
235 #define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U
236 #define XSDPS_CC_MAX_DIV_CNT 256U
237 #define XSDPS_CC_EXT_MAX_DIV_CNT 2046U
238 #define XSDPS_CC_EXT_DIV_SHIFT 6U
240 #define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU
242 #define XSDPS_SWRST_ALL_MASK 0x00000001U
243 #define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U
244 #define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U
246 #define XSDPS_CC_MAX_NUM_OF_DIV 9U
247 #define XSDPS_CC_DIV_SHIFT 8U
251 /** @name SD Interrupt Registers
253 * <b> Normal and Error Interrupt Status Register </b>
254 * This register shows the normal and error interrupt status.
255 * Status enable register affects reads of this register.
256 * If Signal enable register is set and the corresponding status bit is set,
257 * interrupt is generated.
258 * Write to clear except
259 * Error_interrupt and Card_Interrupt bits - Read only
261 * <b> Normal and Error Interrupt Status Enable Register </b>
262 * Setting this register bits enables Interrupt status.
263 * Read/Write except Fixed_to_0 bit (Read only)
265 * <b> Normal and Error Interrupt Signal Enable Register </b>
266 * This register is used to select which interrupt status is
267 * indicated to the Host System as the interrupt.
268 * Read/Write except Fixed_to_0 bit (Read only)
270 * All three registers have same bit definitions
274 #define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */
275 #define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */
276 #define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */
277 #define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */
278 #define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */
279 #define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */
280 #define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */
281 #define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */
282 #define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */
283 #define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */
284 #define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */
285 #define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */
286 #define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */
287 #define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv
289 #define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate
291 #define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */
292 #define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU
294 #define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout
296 #define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */
297 #define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit
299 #define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */
300 #define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */
301 #define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */
302 #define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */
303 #define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */
304 #define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */
305 #define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */
306 #define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */
307 #define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific
309 #define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */
312 /** @name Block Size and Block Count Register
314 * This register contains the block count for current transfer,
315 * block size and SDMA buffer size.
316 * Read/Write except for reserved bits.
320 #define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */
321 #define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */
322 #define XSDPS_BLK_SIZE_1024 0x400U
323 #define XSDPS_BLK_SIZE_2048 0x800U
324 #define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for
329 /** @name Transfer Mode and Command Register
331 * The Transfer Mode register is used to control the data transfers and
332 * Command register is used for command generation
333 * Read/Write except for reserved bits.
337 #define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */
338 #define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */
339 #define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */
340 #define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer
342 #define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single
345 #define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type
347 #define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */
348 #define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */
349 #define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */
350 #define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 &
353 #define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check
355 #define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check
357 #define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */
358 #define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */
359 #define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */
360 #define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */
361 #define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */
362 #define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */
363 #define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask -
369 /** @name Auto CMD Error Status Register
371 * This register is read only register which contains
372 * information about the error status of Auto CMD 12 and 23.
376 #define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
378 #define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
380 #define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
381 #define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
383 #define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
384 #define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
388 /** @name Host Control2 Register
390 * This register contains extended configuration bits.
394 #define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */
395 #define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */
396 #define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */
397 #define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */
398 #define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */
399 #define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */
400 #define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */
401 #define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength
403 #define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */
404 #define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */
405 #define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */
406 #define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */
407 #define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */
408 #define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock
410 #define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt
412 #define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */
416 /** @name Capabilities Register
418 * Capabilities register is a read only register which contains
419 * information about the host controller.
420 * Sufficient if read once after power on.
424 #define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq
426 #define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit -
428 #define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */
429 #define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */
430 #define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */
431 #define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */
432 #define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */
434 #define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */
435 #define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */
436 #define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */
437 #define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */
438 #define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume
440 #define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */
441 #define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */
442 #define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */
444 #define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus
447 #define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode
449 #define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */
450 #define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */
454 #define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt
456 #define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */
457 #define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */
458 #define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */
459 #define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */
461 #define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */
462 #define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */
463 #define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */
464 #define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */
465 #define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */
466 #define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */
467 #define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for
469 #define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs
471 #define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes
473 #define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */
474 #define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */
475 #define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */
476 #define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value
477 for Programmable clock
479 #define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */
480 #define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */
484 /** @name Present State Register
486 * Gives the current status of the host controller
491 #define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */
492 #define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */
493 #define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */
494 #define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */
495 #define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */
496 #define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */
497 #define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */
498 #define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */
499 #define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */
500 #define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */
501 #define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */
502 #define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch
504 #define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */
505 #define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */
506 #define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */
510 /** @name Maximum Current Capablities Register
512 * This register is read only register which contains
513 * information about current capabilities at each voltage levels.
517 #define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current
518 Capability at 1.8V */
519 #define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current
520 Capability at 3.0V */
521 #define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current
522 Capability at 3.3V */
526 /** @name Force Event for Auto CMD Error Status Register
528 * This register is write only register which contains
529 * control bits to generate events for Auto CMD error status.
533 #define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
535 #define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
537 #define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
538 #define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
540 #define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
541 #define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
547 /** @name Force Event for Error Interrupt Status Register
549 * This register is write only register which contains
550 * control bits to generate events of error interrupt status register.
554 #define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout
556 #define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */
557 #define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit
559 #define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */
560 #define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */
561 #define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */
562 #define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */
563 #define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */
564 #define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */
565 #define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */
566 #define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Reponse */
567 #define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific
572 /** @name ADMA Error Status Register
574 * This register is read only register which contains
575 * status information about ADMA errors.
579 #define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch
581 #define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */
582 #define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State
584 #define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State
586 #define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State
590 /** @name Preset Values Register
592 * This register is read only register which contains
593 * preset values for each of speed modes.
597 #define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency
599 #define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator
601 #define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength
606 /** @name Slot Interrupt Status Register
608 * This register is read only register which contains
609 * interrupt slot signal for each slot.
613 #define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal
618 /** @name Host Controller Version Register
620 * This register is read only register which contains
621 * Host Controller and Vendor Specific version.
625 #define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor
628 #define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host
631 #define XSDPS_HC_SPEC_V3 0x0002U
632 #define XSDPS_HC_SPEC_V2 0x0001U
633 #define XSDPS_HC_SPEC_V1 0x0000U
635 /** @name Block size mask for 512 bytes
637 * Block size mask for 512 bytes - This is the default block size.
641 #define XSDPS_BLK_SIZE_512_MASK 0x200U
647 * Constant definitions for commands and response related to SD
651 #define XSDPS_APP_CMD_PREFIX 0x8000U
659 #define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U)
663 #define CMD10 0x0A00U
664 #define CMD11 0x0B00U
665 #define CMD12 0x0C00U
666 #define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
667 #define CMD16 0x1000U
668 #define CMD17 0x1100U
669 #define CMD18 0x1200U
670 #define CMD19 0x1300U
671 #define CMD21 0x1500U
672 #define CMD23 0x1700U
673 #define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U)
674 #define CMD24 0x1800U
675 #define CMD25 0x1900U
676 #define CMD41 0x2900U
677 #define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U)
678 #define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
679 #define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U)
680 #define CMD52 0x3400U
681 #define CMD55 0x3700U
682 #define CMD58 0x3A00U
684 #define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
685 #define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
686 (u32)XSDPS_CMD_INX_CHK_EN_MASK
688 #define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
689 (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
691 #define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
692 #define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
694 #define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
695 (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
699 /* Card Interface Conditions Definitions */
700 #define XSDPS_CIC_CHK_PATTERN 0xAAU
701 #define XSDPS_CIC_VOLT_MASK (0xFU<<8)
702 #define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8)
703 #define XSDPS_CIC_VOLT_LOW (1U<<9)
705 /* Operation Conditions Register Definitions */
706 #define XSDPS_OCR_PWRUP_STS (1U<<31)
707 #define XSDPS_OCR_CC_STS (1U<<30)
708 #define XSDPS_OCR_S18 (1U<<24)
709 #define XSDPS_OCR_3V5_3V6 (1U<<23)
710 #define XSDPS_OCR_3V4_3V5 (1U<<22)
711 #define XSDPS_OCR_3V3_3V4 (1U<<21)
712 #define XSDPS_OCR_3V2_3V3 (1U<<20)
713 #define XSDPS_OCR_3V1_3V2 (1U<<19)
714 #define XSDPS_OCR_3V0_3V1 (1U<<18)
715 #define XSDPS_OCR_2V9_3V0 (1U<<17)
716 #define XSDPS_OCR_2V8_2V9 (1U<<16)
717 #define XSDPS_OCR_2V7_2V8 (1U<<15)
718 #define XSDPS_OCR_1V7_1V95 (1U<<7)
719 #define XSDPS_OCR_HIGH_VOL 0x00FF8000U
720 #define XSDPS_OCR_LOW_VOL 0x00000080U
722 /* SD Card Configuration Register Definitions */
723 #define XSDPS_SCR_REG_LEN 8U
724 #define XSDPS_SCR_STRUCT_MASK (0xFU<<28)
725 #define XSDPS_SCR_SPEC_MASK (0xFU<<24)
726 #define XSDPS_SCR_SPEC_1V0 0U
727 #define XSDPS_SCR_SPEC_1V1 (1U<<24)
728 #define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24)
729 #define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23)
730 #define XSDPS_SCR_SEC_SUPP_MASK (7U<<20)
731 #define XSDPS_SCR_SEC_SUPP_NONE 0U
732 #define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20)
733 #define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20)
734 #define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20)
735 #define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16)
736 #define XSDPS_SCR_BUS_WIDTH_1 (1U<<16)
737 #define XSDPS_SCR_BUS_WIDTH_4 (4U<<16)
738 #define XSDPS_SCR_SPEC3_MASK (1U<<12)
739 #define XSDPS_SCR_SPEC3_2V0 0U
740 #define XSDPS_SCR_SPEC3_3V0 (1U<<12)
741 #define XSDPS_SCR_CMD_SUPP_MASK 0x3U
742 #define XSDPS_SCR_CMD23_SUPP (1U<<1)
743 #define XSDPS_SCR_CMD20_SUPP (1U<<0)
745 /* Card Status Register Definitions */
746 #define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31)
747 #define XSDPS_CD_STS_ADDR_ERR (1U<<30)
748 #define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29)
749 #define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28)
750 #define XSDPS_CD_STS_ER_PRM_ERR (1U<<27)
751 #define XSDPS_CD_STS_WP_VIO (1U<<26)
752 #define XSDPS_CD_STS_IS_LOCKED (1U<<25)
753 #define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24)
754 #define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23)
755 #define XSDPS_CD_STS_ILGL_CMD (1U<<22)
756 #define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21)
757 #define XSDPS_CD_STS_CC_ERR (1U<<20)
758 #define XSDPS_CD_STS_ERR (1U<<19)
759 #define XSDPS_CD_STS_CSD_OVRWR (1U<<16)
760 #define XSDPS_CD_STS_WP_ER_SKIP (1U<<15)
761 #define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14)
762 #define XSDPS_CD_STS_ER_RST (1U<<13)
763 #define XSDPS_CD_STS_CUR_STATE (0xFU<<9)
764 #define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8)
765 #define XSDPS_CD_STS_APP_CMD (1U<<5)
766 #define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2)
768 /* Switch Function Definitions CMD6 */
769 #define XSDPS_SWITCH_SD_RESP_LEN 64U
771 #define XSDPS_SWITCH_FUNC_SWITCH (1U<<31)
772 #define XSDPS_SWITCH_FUNC_CHECK 0U
774 #define XSDPS_MODE_FUNC_GRP1 1U
775 #define XSDPS_MODE_FUNC_GRP2 2U
776 #define XSDPS_MODE_FUNC_GRP3 3U
777 #define XSDPS_MODE_FUNC_GRP4 4U
778 #define XSDPS_MODE_FUNC_GRP5 5U
779 #define XSDPS_MODE_FUNC_GRP6 6U
781 #define XSDPS_FUNC_GRP_DEF_VAL 0xFU
782 #define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU
784 #define XSDPS_ACC_MODE_DEF_SDR12 0U
785 #define XSDPS_ACC_MODE_HS_SDR25 1U
786 #define XSDPS_ACC_MODE_SDR50 2U
787 #define XSDPS_ACC_MODE_SDR104 3U
788 #define XSDPS_ACC_MODE_DDR50 4U
790 #define XSDPS_CMD_SYS_ARG_SHIFT 4U
791 #define XSDPS_CMD_SYS_DEF 0U
792 #define XSDPS_CMD_SYS_eC 1U
793 #define XSDPS_CMD_SYS_OTP 3U
794 #define XSDPS_CMD_SYS_ASSD 4U
795 #define XSDPS_CMD_SYS_VEND 5U
797 #define XSDPS_DRV_TYPE_ARG_SHIFT 8U
798 #define XSDPS_DRV_TYPE_B 0U
799 #define XSDPS_DRV_TYPE_A 1U
800 #define XSDPS_DRV_TYPE_C 2U
801 #define XSDPS_DRV_TYPE_D 3U
803 #define XSDPS_CUR_LIM_ARG_SHIFT 12U
804 #define XSDPS_CUR_LIM_200 0U
805 #define XSDPS_CUR_LIM_400 1U
806 #define XSDPS_CUR_LIM_600 2U
807 #define XSDPS_CUR_LIM_800 3U
809 #define CSD_SPEC_VER_MASK 0x3C0000U
810 #define READ_BLK_LEN_MASK 0x00000F00U
811 #define C_SIZE_MULT_MASK 0x00000380U
812 #define C_SIZE_LOWER_MASK 0xFFC00000U
813 #define C_SIZE_UPPER_MASK 0x00000003U
814 #define CSD_STRUCT_MASK 0x00C00000U
815 #define CSD_V2_C_SIZE_MASK 0x3FFFFF00U
817 /* EXT_CSD field definitions */
818 #define XSDPS_EXT_CSD_SIZE 512U
820 #define EXT_CSD_WR_REL_PARAM_EN (1U<<2)
822 #define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U)
823 #define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U)
824 #define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U)
825 #define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U)
827 #define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U)
828 #define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U)
829 #define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U)
830 #define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U)
832 #define EXT_CSD_PART_SUPPORT_PART_EN (0x1U)
834 #define EXT_CSD_CMD_SET_NORMAL (1U<<0)
835 #define EXT_CSD_CMD_SET_SECURE (1U<<1)
836 #define EXT_CSD_CMD_SET_CPSECURE (1U<<2)
838 #define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */
839 #define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */
840 #define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */
841 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */
842 /* DDR mode @1.8V or 3V I/O */
843 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */
844 /* DDR mode @1.2V I/O */
845 #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
846 | EXT_CSD_CARD_TYPE_DDR_1_2V)
847 #define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */
848 #define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */
849 /* SDR mode @1.2V I/O */
850 #define EXT_CSD_BUS_WIDTH_BYTE 183U
851 #define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */
852 #define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */
853 #define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */
854 #define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */
855 #define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */
857 #define EXT_CSD_HS_TIMING_BYTE 185U
858 #define EXT_CSD_HS_TIMING_DEF 0U
859 #define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */
860 #define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */
862 #define EXT_CSD_RST_N_FUN_BYTE 162U
863 #define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */
864 #define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */
865 #define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */
867 #define XSDPS_EXT_CSD_CMD_SET 0U
868 #define XSDPS_EXT_CSD_SET_BITS 1U
869 #define XSDPS_EXT_CSD_CLR_BITS 2U
870 #define XSDPS_EXT_CSD_WRITE_BYTE 3U
872 #define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
873 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
874 | ((u32)EXT_CSD_HS_TIMING_DEF << 8))
876 #define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
877 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
878 | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
880 #define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
881 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
882 | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
884 #define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
885 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
886 | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
888 #define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
889 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
890 | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
892 #define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
893 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
894 | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
896 #define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
897 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
898 | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
900 #define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
901 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
902 | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
904 #define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
905 | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
906 | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
908 #define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
912 /* @400KHz, in usec */
913 #define XSDPS_74CLK_DELAY 2960U
914 #define XSDPS_100CLK_DELAY 4000U
915 #define XSDPS_INIT_DELAY 10000U
917 #define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK
918 #define XSDPS_CARD_DEF_ADDR 0x1234U
920 #define XSDPS_CARD_SD 1U
921 #define XSDPS_CARD_MMC 2U
922 #define XSDPS_CARD_SDIO 3U
923 #define XSDPS_CARD_SDCOMBO 4U
924 #define XSDPS_CHIP_EMMC 5U
927 /** @name ADMA2 Descriptor related definitions
929 * ADMA2 Descriptor related definitions
933 #define XSDPS_DESC_MAX_LENGTH 65536U
935 #define XSDPS_DESC_VALID (0x1U << 0)
936 #define XSDPS_DESC_END (0x1U << 1)
937 #define XSDPS_DESC_INT (0x1U << 2)
938 #define XSDPS_DESC_TRAN (0x2U << 4)
942 /* For changing clock frequencies */
943 #define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */
944 #define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */
945 #define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */
946 #define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */
947 #define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */
948 #define XSDPS_SCR_BLKCNT 1U
949 #define XSDPS_SCR_BLKSIZE 8U
950 #define XSDPS_1_BIT_WIDTH 0x1U
951 #define XSDPS_4_BIT_WIDTH 0x2U
952 #define XSDPS_8_BIT_WIDTH 0x3U
953 #define XSDPS_UHS_SPEED_MODE_SDR12 0x0U
954 #define XSDPS_UHS_SPEED_MODE_SDR25 0x1U
955 #define XSDPS_UHS_SPEED_MODE_SDR50 0x2U
956 #define XSDPS_UHS_SPEED_MODE_SDR104 0x3U
957 #define XSDPS_UHS_SPEED_MODE_DDR50 0x4U
958 #define XSDPS_HIGH_SPEED_MODE 0x5U
959 #define XSDPS_DEFAULT_SPEED_MODE 0x6U
960 #define XSDPS_HS200_MODE 0x7U
961 #define XSDPS_DDR52_MODE 0x4U
962 #define XSDPS_SWITCH_CMD_BLKCNT 1U
963 #define XSDPS_SWITCH_CMD_BLKSIZE 64U
964 #define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U
965 #define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U
966 #define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U
967 #define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U
968 #define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U
969 #define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U
970 #define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U
971 #define XSDPS_EXT_CSD_CMD_BLKCNT 1U
972 #define XSDPS_EXT_CSD_CMD_BLKSIZE 512U
973 #define XSDPS_TUNING_CMD_BLKCNT 1U
974 #define XSDPS_TUNING_CMD_BLKSIZE 64U
976 #define XSDPS_HIGH_SPEED_MAX_CLK 50000000U
977 #define XSDPS_UHS_SDR104_MAX_CLK 208000000U
978 #define XSDPS_UHS_SDR50_MAX_CLK 100000000U
979 #define XSDPS_UHS_DDR50_MAX_CLK 50000000U
980 #define XSDPS_UHS_SDR25_MAX_CLK 50000000U
981 #define XSDPS_UHS_SDR12_MAX_CLK 25000000U
983 #define SD_DRIVER_TYPE_B 0x01U
984 #define SD_DRIVER_TYPE_A 0x02U
985 #define SD_DRIVER_TYPE_C 0x04U
986 #define SD_DRIVER_TYPE_D 0x08U
987 #define SD_SET_CURRENT_LIMIT_200 0U
988 #define SD_SET_CURRENT_LIMIT_400 1U
989 #define SD_SET_CURRENT_LIMIT_600 2U
990 #define SD_SET_CURRENT_LIMIT_800 3U
992 #define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200)
993 #define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400)
994 #define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600)
995 #define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800)
997 #define XSDPS_SD_SDR12_MAX_CLK 25000000U
998 #define XSDPS_SD_SDR25_MAX_CLK 50000000U
999 #define XSDPS_SD_SDR50_MAX_CLK 100000000U
1000 #define XSDPS_SD_DDR50_MAX_CLK 50000000U
1001 #define XSDPS_SD_SDR104_MAX_CLK 208000000U
1003 * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
1004 * than the clock value coming from the core. This value is kept to safely
1005 * switch to SDR104 mode if the SD card supports it.
1007 #define XSDPS_SD_INPUT_MAX_CLK 175000000U
1009 #define XSDPS_MMC_HS200_MAX_CLK 200000000U
1010 #define XSDPS_MMC_HSD_MAX_CLK 52000000U
1011 #define XSDPS_MMC_DDR_MAX_CLK 52000000U
1013 #define XSDPS_CARD_STATE_IDLE 0U
1014 #define XSDPS_CARD_STATE_RDY 1U
1015 #define XSDPS_CARD_STATE_IDEN 2U
1016 #define XSDPS_CARD_STATE_STBY 3U
1017 #define XSDPS_CARD_STATE_TRAN 4U
1018 #define XSDPS_CARD_STATE_DATA 5U
1019 #define XSDPS_CARD_STATE_RCV 6U
1020 #define XSDPS_CARD_STATE_PROG 7U
1021 #define XSDPS_CARD_STATE_DIS 8U
1022 #define XSDPS_CARD_STATE_BTST 9U
1023 #define XSDPS_CARD_STATE_SLP 10U
1025 #define XSDPS_SLOT_REM 0U
1026 #define XSDPS_SLOT_EMB 1U
1028 #define XSDPS_WIDTH_8 8U
1029 #define XSDPS_WIDTH_4 4U
1032 #if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
1033 #define SD0_ITAPDLY_SEL_MASK 0x000000FFU
1034 #define SD0_OTAPDLY_SEL_MASK 0x0000003FU
1035 #define SD1_ITAPDLY_SEL_MASK 0x00FF0000U
1036 #define SD1_OTAPDLY_SEL_MASK 0x003F0000U
1037 #define SD_DLL_CTRL 0x00000358U
1038 #define SD_ITAPDLY 0x00000314U
1039 #define SD_OTAPDLY 0x00000318U
1040 #define SD0_DLL_RST 0x00000004U
1041 #define SD1_DLL_RST 0x00040000U
1042 #define SD0_ITAPCHGWIN 0x00000200U
1043 #define SD0_ITAPDLYENA 0x00000100U
1044 #define SD0_OTAPDLYENA 0x00000040U
1045 #define SD1_ITAPCHGWIN 0x02000000U
1046 #define SD1_ITAPDLYENA 0x01000000U
1047 #define SD1_OTAPDLYENA 0x00400000U
1049 #define SD0_OTAPDLYSEL_HS200_B0 0x00000003U
1050 #define SD0_OTAPDLYSEL_HS200_B2 0x00000002U
1051 #define SD0_ITAPDLYSEL_SD50 0x00000014U
1052 #define SD0_OTAPDLYSEL_SD50 0x00000003U
1053 #define SD0_ITAPDLYSEL_SD_DDR50 0x0000003DU
1054 #define SD0_ITAPDLYSEL_EMMC_DDR50 0x00000012U
1055 #define SD0_OTAPDLYSEL_SD_DDR50 0x00000004U
1056 #define SD0_OTAPDLYSEL_EMMC_DDR50 0x00000006U
1057 #define SD0_ITAPDLYSEL_HSD 0x00000015U
1058 #define SD0_OTAPDLYSEL_SD_HSD 0x00000005U
1059 #define SD0_OTAPDLYSEL_EMMC_HSD 0x00000006U
1061 #define SD1_OTAPDLYSEL_HS200_B0 0x00030000U
1062 #define SD1_OTAPDLYSEL_HS200_B2 0x00020000U
1063 #define SD1_ITAPDLYSEL_SD50 0x00140000U
1064 #define SD1_OTAPDLYSEL_SD50 0x00030000U
1065 #define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000U
1066 #define SD1_ITAPDLYSEL_EMMC_DDR50 0x00120000U
1067 #define SD1_OTAPDLYSEL_SD_DDR50 0x00040000U
1068 #define SD1_OTAPDLYSEL_EMMC_DDR50 0x00060000U
1069 #define SD1_ITAPDLYSEL_HSD 0x00150000U
1070 #define SD1_OTAPDLYSEL_SD_HSD 0x00050000U
1071 #define SD1_OTAPDLYSEL_EMMC_HSD 0x00060000U
1075 /**************************** Type Definitions *******************************/
1077 /***************** Macros (Inline Functions) Definitions *********************/
1078 #define XSdPs_In64 Xil_In64
1079 #define XSdPs_Out64 Xil_Out64
1081 #define XSdPs_In32 Xil_In32
1082 #define XSdPs_Out32 Xil_Out32
1084 #define XSdPs_In16 Xil_In16
1085 #define XSdPs_Out16 Xil_Out16
1087 #define XSdPs_In8 Xil_In8
1088 #define XSdPs_Out8 Xil_Out8
1090 /****************************************************************************/
1094 * @param BaseAddress contains the base address of the device.
1095 * @param RegOffset contains the offset from the 1st register of the
1096 * device to the target register.
1098 * @return The value read from the register.
1100 * @note C-Style signature:
1101 * u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
1103 ******************************************************************************/
1104 #define XSdPs_ReadReg64(InstancePtr, RegOffset) \
1105 XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
1107 /***************************************************************************/
1109 * Write to a register.
1111 * @param BaseAddress contains the base address of the device.
1112 * @param RegOffset contains the offset from the 1st register of the
1113 * device to target register.
1114 * @param RegisterValue is the value to be written to the register.
1118 * @note C-Style signature:
1119 * void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
1120 * u64 RegisterValue)
1122 ******************************************************************************/
1123 #define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
1124 XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
1127 /****************************************************************************/
1131 * @param BaseAddress contains the base address of the device.
1132 * @param RegOffset contains the offset from the 1st register of the
1133 * device to the target register.
1135 * @return The value read from the register.
1137 * @note C-Style signature:
1138 * u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
1140 ******************************************************************************/
1141 #define XSdPs_ReadReg(BaseAddress, RegOffset) \
1142 XSdPs_In32((BaseAddress) + (RegOffset))
1144 /***************************************************************************/
1146 * Write to a register.
1148 * @param BaseAddress contains the base address of the device.
1149 * @param RegOffset contains the offset from the 1st register of the
1150 * device to target register.
1151 * @param RegisterValue is the value to be written to the register.
1155 * @note C-Style signature:
1156 * void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
1157 * u32 RegisterValue)
1159 ******************************************************************************/
1160 #define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
1161 XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
1163 /****************************************************************************/
1167 * @param BaseAddress contains the base address of the device.
1168 * @param RegOffset contains the offset from the 1st register of the
1169 * device to the target register.
1171 * @return The value read from the register.
1173 * @note C-Style signature:
1174 * u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
1176 ******************************************************************************/
1177 static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
1179 #if defined (__MICROBLAZE__)
1181 BaseAddress += RegOffset & 0xFC;
1182 Reg = XSdPs_In32(BaseAddress);
1183 Reg >>= ((RegOffset & 0x3)*8);
1186 return XSdPs_In16((BaseAddress) + (RegOffset));
1190 /***************************************************************************/
1192 * Write to a register.
1194 * @param BaseAddress contains the base address of the device.
1195 * @param RegOffset contains the offset from the 1st register of the
1196 * device to target register.
1197 * @param RegisterValue is the value to be written to the register.
1201 * @note C-Style signature:
1202 * void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
1203 * u16 RegisterValue)
1205 ******************************************************************************/
1207 static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
1209 #if defined (__MICROBLAZE__)
1211 BaseAddress += RegOffset & 0xFC;
1212 Reg = XSdPs_In32(BaseAddress);
1213 Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8));
1214 Reg |= RegisterValue <<((RegOffset & 0x3)*8);
1215 XSdPs_Out32(BaseAddress, Reg);
1217 XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
1221 /****************************************************************************/
1225 * @param BaseAddress contains the base address of the device.
1226 * @param RegOffset contains the offset from the 1st register of the
1227 * device to the target register.
1229 * @return The value read from the register.
1231 * @note C-Style signature:
1232 * u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
1234 ******************************************************************************/
1235 static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
1237 #if defined (__MICROBLAZE__)
1239 BaseAddress += RegOffset & 0xFC;
1240 Reg = XSdPs_In32(BaseAddress);
1241 Reg >>= ((RegOffset & 0x3)*8);
1244 return XSdPs_In8((BaseAddress) + (RegOffset));
1247 /***************************************************************************/
1249 * Write to a register.
1251 * @param BaseAddress contains the base address of the device.
1252 * @param RegOffset contains the offset from the 1st register of the
1253 * device to target register.
1254 * @param RegisterValue is the value to be written to the register.
1258 * @note C-Style signature:
1259 * void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
1262 ******************************************************************************/
1263 static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
1265 #if defined (__MICROBLAZE__)
1267 BaseAddress += RegOffset & 0xFC;
1268 Reg = XSdPs_In32(BaseAddress);
1269 Reg &= ~(0xFF<<((RegOffset & 0x3)*8));
1270 Reg |= RegisterValue <<((RegOffset & 0x3)*8);
1271 XSdPs_Out32(BaseAddress, Reg);
1273 XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
1276 /***************************************************************************/
1278 * Macro to get present status register
1280 * @param BaseAddress contains the base address of the device.
1284 * @note C-Style signature:
1285 * void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
1288 ******************************************************************************/
1289 #define XSdPs_GetPresentStatusReg(BaseAddress) \
1290 XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
1292 /************************** Function Prototypes ******************************/
1294 /************************** Variable Definitions *****************************/
1300 #endif /* SD_HW_H_ */