]> git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.c
Update some more standard demos for use on 64-bit architectures.
[freertos] / FreeRTOS / Demo / CORTEX_R5_UltraScale_MPSoC / RTOSDemo_R5_bsp / psu_cortexr5_0 / libsrc / standalone_v5_4 / src / sleep.c
1 /******************************************************************************
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19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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31 ******************************************************************************/
32 /*****************************************************************************
33 *
34 * @file sleep.c
35 *
36 * This function provides a second delay using the Global Timer register in
37 * the ARM Cortex R5 MP core.
38 *
39 * <pre>
40 * MODIFICATION HISTORY:
41 *
42 * Ver   Who      Date     Changes
43 * ----- -------- -------- -----------------------------------------------
44 * 5.00  pkp      02/20/14 First release
45 * 5.04  pkp              02/19/16 sleep routine is modified to use TTC3 if present
46 *                                                 else it will use set of assembly instructions to
47 *                                                 provide the required delay
48 * 5.04  pkp              03/09/16 Assembly routine for sleep is modified to avoid
49 *                                                 disabling the interrupt
50 * 5.04  pkp              03/11/16 Compare the counter value to previously read value
51 *                                                 to detect the overflow for TTC3
52 * </pre>
53 *
54 ******************************************************************************/
55 /***************************** Include Files *********************************/
56
57 #include "sleep.h"
58 #include "xtime_l.h"
59 #include "xparameters.h"
60
61 /*****************************************************************************/
62 /*
63 *
64 * This API is used to provide delays in seconds.
65 *
66 * @param        seconds requested
67 *
68 * @return       0 always
69 *
70 * @note         The sleep API is implemented using TTC3 counter 0 timer if present.
71 *                       When TTC3 is absent, sleep is implemented using assembly
72 *                       instructions which is tested with instruction and data caches
73 *                       enabled and it gives proper delay. It may give more delay than
74 *                       exepcted when caches are disabled. If interrupt comes when sleep
75 *                       using assembly instruction is being executed, the delay may be
76 *                       greater than what is expected since once the interrupt is served
77 *                       count resumes from where it was interrupted unlike the case of TTC3
78 *                       where counter keeps running while interrupt is being served.
79 *
80 ****************************************************************************/
81
82 s32 sleep(u32 seconds)
83 {
84 #ifdef SLEEP_TIMER_BASEADDR
85         u64 tEnd;
86         u64 tCur;
87         u32 TimeHighVal;
88         XTime TimeLowVal1;
89         XTime TimeLowVal2;
90
91         TimeHighVal = 0;
92
93         XTime_GetTime(&TimeLowVal1);
94         tEnd  = (u64)TimeLowVal1 + (((u64) seconds) * COUNTS_PER_SECOND);
95
96         do
97         {
98
99             XTime_GetTime(&TimeLowVal2);
100             if (TimeLowVal2 < TimeLowVal1) {
101                                 TimeHighVal++;
102                 }
103
104                 TimeLowVal1 = TimeLowVal2;
105             tCur = (((u64) TimeHighVal) << 32U) | (u64)TimeLowVal2;
106
107         } while (tCur < tEnd);
108
109         return 0;
110 #else
111         __asm__ __volatile__ (
112                         " push {r0,r1}          \n\t"
113                         " mov r0, %[sec]        \n\t"
114                         " 1: \n\t"
115                         " mov r1, %[iter]       \n\t"
116                         " 2:                            \n\t"
117                         " subs r1, r1, #0x1 \n\t"
118                         " bne   2b              \n\t"
119                         " subs r0,r0,#0x1       \n\t"
120                         "  bne 1b                       \n\t"
121                         " pop {r0,r1}           \n\t"
122                         :: [iter] "r" (ITERS_PER_SEC), [sec] "r" (seconds)
123         );
124 #endif
125 }