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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
  28 * in advertising or otherwise to promote the sale, use or other dealings in
  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /*****************************************************************************/
  33 /**
  34 *
  35 * @file xpm_counter.c
  36 *
  37 * This file contains APIs for configuring and controlling the Cortex-R5
  38 * Performance Monitor Events. For more information about the event counters,
  39 * see xpm_counter.h.
  40 *
  41 * <pre>
  42 * MODIFICATION HISTORY:
  43 *
  44 * Ver   Who  Date     Changes
  45 * ----- ---- -------- -----------------------------------------------
  46 * 5.00  pkp  02/10/14 Initial version
  47 * </pre>
  48 *
  49 ******************************************************************************/
  50
  51 /***************************** Include Files *********************************/
  52
  53 #include "xpm_counter.h"
  54
  55 /************************** Constant Definitions ****************************/
  56
  57 /**************************** Type Definitions ******************************/
  58
  59 typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT];
  60
  61 /***************** Macros (Inline Functions) Definitions ********************/
  62
  63 /************************** Variable Definitions *****************************/
  64
  65
  66
  67 /************************** Function Prototypes ******************************/
  68
  69 void Xpm_DisableEventCounters(void);
  70 void Xpm_EnableEventCounters (void);
  71 void Xpm_ResetEventCounters (void);
  72
  73 /******************************************************************************/
  74
  75 /****************************************************************************/
  76 /**
  77 *
  78 * This function disables the Cortex R5 event counters.
  79 *
  80 * @param        None.
  81 *
  82 * @return       None.
  83 *
  84 * @note         None.
  85 *
  86 *****************************************************************************/
  87 void Xpm_DisableEventCounters(void)
  88 {
  89         /* Disable the event counters */
  90         mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f);
  91 }
  92
  93 /****************************************************************************/
  94 /**
  95 *
  96 * This function enables the Cortex R5 event counters.
  97 *
  98 * @param        None.
  99 *
 100 * @return       None.
 101 *
 102 * @note         None.
 103 *
 104 *****************************************************************************/
 105 void Xpm_EnableEventCounters(void)
 106 {
 107         /* Enable the event counters */
 108         mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f);
 109 }
 110
 111 /****************************************************************************/
 112 /**
 113 *
 114 * This function resets the Cortex R5 event counters.
 115 *
 116 * @param        None.
 117 *
 118 * @return       None.
 119 *
 120 * @note         None.
 121 *
 122 *****************************************************************************/
 123 void Xpm_ResetEventCounters(void)
 124 {
 125         u32 Reg;
 126
 127 #ifdef __GNUC__
 128         Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
 129 #else
 130         { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
 131           Reg = C15Reg; }
 132 #endif
 133         Reg |= (1U << 2U); /* reset event counters */
 134         mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
 135 }
 136
 137 /****************************************************************************/
 138 /**
 139 *
 140 * This function configures the Cortex R5 event counters controller, with the
 141 * event codes, in a configuration selected by the user and enables the counters.
 142 *
 143 * @param        PmcrCfg is configuration value based on which the event counters
 144 *               are configured.
 145 *               Use XPM_CNTRCFG* values defined in xpm_counter.h.
 146 *
 147 * @return       None.
 148 *
 149 * @note         None.
 150 *
 151 *****************************************************************************/
 152 void Xpm_SetEvents(s32 PmcrCfg)
 153 {
 154         u32 Counter;
 155         static PmcrEventCfg32 PmcrEvents[] = {
 156                 {
 157                         XPM_EVENT_SOFTINCR,
 158                         XPM_EVENT_INSRFETCH_CACHEREFILL,
 159                         XPM_EVENT_INSTRFECT_TLBREFILL,
 160                         XPM_EVENT_DATA_CACHEREFILL,
 161                         XPM_EVENT_DATA_CACHEACCESS,
 162                         XPM_EVENT_DATA_TLBREFILL
 163                 },
 164                 {
 165                         XPM_EVENT_DATA_READS,
 166                         XPM_EVENT_DATA_WRITE,
 167                         XPM_EVENT_EXCEPTION,
 168                         XPM_EVENT_EXCEPRETURN,
 169                         XPM_EVENT_CHANGECONTEXT,
 170                         XPM_EVENT_SW_CHANGEPC
 171                 },
 172                 {
 173                         XPM_EVENT_IMMEDBRANCH,
 174                         XPM_EVENT_UNALIGNEDACCESS,
 175                         XPM_EVENT_BRANCHMISS,
 176                         XPM_EVENT_CLOCKCYCLES,
 177                         XPM_EVENT_BRANCHPREDICT,
 178                         XPM_EVENT_JAVABYTECODE
 179                 },
 180                 {
 181                         XPM_EVENT_SWJAVABYTECODE,
 182                         XPM_EVENT_JAVABACKBRANCH,
 183                         XPM_EVENT_COHERLINEMISS,
 184                         XPM_EVENT_COHERLINEHIT,
 185                         XPM_EVENT_INSTRSTALL,
 186                         XPM_EVENT_DATASTALL
 187                 },
 188                 {
 189                         XPM_EVENT_MAINTLBSTALL,
 190                         XPM_EVENT_STREXPASS,
 191                         XPM_EVENT_STREXFAIL,
 192                         XPM_EVENT_DATAEVICT,
 193                         XPM_EVENT_NODISPATCH,
 194                         XPM_EVENT_ISSUEEMPTY
 195                 },
 196                 {
 197                         XPM_EVENT_INSTRRENAME,
 198                         XPM_EVENT_PREDICTFUNCRET,
 199                         XPM_EVENT_MAINEXEC,
 200                         XPM_EVENT_SECEXEC,
 201                         XPM_EVENT_LDRSTR,
 202                         XPM_EVENT_FLOATRENAME
 203                 },
 204                 {
 205                         XPM_EVENT_NEONRENAME,
 206                         XPM_EVENT_PLDSTALL,
 207                         XPM_EVENT_WRITESTALL,
 208                         XPM_EVENT_INSTRTLBSTALL,
 209                         XPM_EVENT_DATATLBSTALL,
 210                         XPM_EVENT_INSTR_uTLBSTALL
 211                 },
 212                 {
 213                         XPM_EVENT_DATA_uTLBSTALL,
 214                         XPM_EVENT_DMB_STALL,
 215                         XPM_EVENT_INT_CLKEN,
 216                         XPM_EVENT_DE_CLKEN,
 217                         XPM_EVENT_INSTRISB,
 218                         XPM_EVENT_INSTRDSB
 219                 },
 220                 {
 221                         XPM_EVENT_INSTRDMB,
 222                         XPM_EVENT_EXTINT,
 223                         XPM_EVENT_PLE_LRC,
 224                         XPM_EVENT_PLE_LRS,
 225                         XPM_EVENT_PLE_FLUSH,
 226                         XPM_EVENT_PLE_CMPL
 227                 },
 228                 {
 229                         XPM_EVENT_PLE_OVFL,
 230                         XPM_EVENT_PLE_PROG,
 231                         XPM_EVENT_PLE_LRC,
 232                         XPM_EVENT_PLE_LRS,
 233                         XPM_EVENT_PLE_FLUSH,
 234                         XPM_EVENT_PLE_CMPL
 235                 },
 236                 {
 237                         XPM_EVENT_DATASTALL,
 238                         XPM_EVENT_INSRFETCH_CACHEREFILL,
 239                         XPM_EVENT_INSTRFECT_TLBREFILL,
 240                         XPM_EVENT_DATA_CACHEREFILL,
 241                         XPM_EVENT_DATA_CACHEACCESS,
 242                         XPM_EVENT_DATA_TLBREFILL
 243                 },
 244         };
 245         const u32 *ptr = PmcrEvents[PmcrCfg];
 246
 247         Xpm_DisableEventCounters();
 248
 249         for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
 250
 251                 /* Selecet event counter */
 252                 mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
 253
 254                 /* Set the event */
 255                 mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]);
 256         }
 257
 258         Xpm_ResetEventCounters();
 259         Xpm_EnableEventCounters();
 260 }
 261
 262 /****************************************************************************/
 263 /**
 264 *
 265 * This function disables the event counters and returns the counter values.
 266 *
 267 * @param        PmCtrValue is a pointer to an array of type u32 PmCtrValue[6].
 268 *               It is an output parameter which is used to return the PM
 269 *               counter values.
 270 *
 271 * @return       None.
 272 *
 273 * @note         None.
 274 *
 275 *****************************************************************************/
 276 void Xpm_GetEventCounters(u32 *PmCtrValue)
 277 {
 278         u32 Counter;
 279
 280         Xpm_DisableEventCounters();
 281
 282         for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
 283
 284                 mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
 285 #ifdef __GNUC__
 286                 PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
 287 #else
 288                 { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
 289                   PmCtrValue[Counter] = Cp15Reg; }
 290 #endif
 291         }
 292 }