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32 /*****************************************************************************/
36 * This file contains the initial vector table for the Cortex R5 processor
39 * MODIFICATION HISTORY:
41 * Ver Who Date Changes
42 * ----- ------- -------- ---------------------------------------------------
43 * 5.00 pkp 02/10/14 Initial version
44 * 6.0 mus 27/07/16 Added UndefinedException handler
51 ******************************************************************************/
61 .globl DataAbortInterrupt
62 .globl PrefetchAbortInterrupt
67 .section .vectors, "a"
72 ldr pc,=PrefetchAbortHandler
73 ldr pc,=DataAbortHandler
74 NOP /* Placeholder for address exception vector*/
79 IRQHandler: /* IRQ vector handler */
80 stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/
81 bl IRQInterrupt /* IRQ vector */
82 ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
83 subs pc, lr, #4 /* adjust return */
85 FIQHandler: /* FIQ vector handler */
86 stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
88 bl FIQInterrupt /* FIQ vector */
89 ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
90 subs pc, lr, #4 /* adjust return */
92 Undefined: /* Undefined handler */
93 stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
94 ldr r0, =UndefinedExceptionAddr
96 str r1, [r0] /* Store address of instruction causing undefined exception */
98 bl UndefinedException /* UndefinedException: call C function here */
99 ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
102 SVCHandler: /* SWI handler */
103 stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
104 tst r0, #0x20 /* check the T bit */
105 ldrneh r0, [lr,#-2] /* Thumb mode */
106 bicne r0, r0, #0xff00 /* Thumb mode */
107 ldreq r0, [lr,#-4] /* ARM mode */
108 biceq r0, r0, #0xff000000 /* ARM mode */
109 bl SWInterrupt /* SWInterrupt: call C function here */
110 ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
111 movs pc, lr /* adjust return */
113 DataAbortHandler: /* Data Abort handler */
114 stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
115 ldr r0, =DataAbortAddr
117 str r1, [r0] /* Stores instruction causing data abort */
118 bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */
119 ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
120 subs pc, lr, #8 /* adjust return */
122 PrefetchAbortHandler: /* Prefetch Abort handler */
123 stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
124 ldr r0, =PrefetchAbortAddr
126 str r1, [r0] /* Stores instruction causing prefetch abort */
127 bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */
128 ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
129 subs pc, lr, #4 /* adjust return */