1 /******************************************************************************
3 * Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 * Except as contained in this notice, the name of the Xilinx shall not be used
28 * in advertising or otherwise to promote the sale, use or other dealings in
29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
32 /*****************************************************************************/
36 * This file contains initial configuration of the MPU.
39 * MODIFICATION HISTORY:
41 * Ver Who Date Changes
42 * ----- ---- -------- ---------------------------------------------------
43 * 5.00 pkp 02/20/14 First release
44 * 5.04 pkp 12/18/15 Updated MPU initialization as per the proper address map
45 * 6.00 pkp 06/27/16 moving the Init_MPU code to .boot section since it is a
46 * part of processor boot process
47 * 6.2 mus 01/27/17 Updated to support IAR compiler
54 ******************************************************************************/
55 /***************************** Include Files *********************************/
57 #include "xil_types.h"
58 #include "xreg_cortexr5.h"
60 #include "xpseudo_asm.h"
61 #include "xparameters.h"
63 /***************** Macros (Inline Functions) Definitions *********************/
65 /**************************** Type Definitions *******************************/
67 /************************** Constant Definitions *****************************/
69 /************************** Variable Definitions *****************************/
73 unsigned int encoding;
77 { 0x80, REGION_128B },
78 { 0x100, REGION_256B },
79 { 0x200, REGION_512B },
82 { 0x1000, REGION_4K },
83 { 0x2000, REGION_8K },
84 { 0x4000, REGION_16K },
85 { 0x8000, REGION_32K },
86 { 0x10000, REGION_64K },
87 { 0x20000, REGION_128K },
88 { 0x40000, REGION_256K },
89 { 0x80000, REGION_512K },
90 { 0x100000, REGION_1M },
91 { 0x200000, REGION_2M },
92 { 0x400000, REGION_4M },
93 { 0x800000, REGION_8M },
94 { 0x1000000, REGION_16M },
95 { 0x2000000, REGION_32M },
96 { 0x4000000, REGION_64M },
97 { 0x8000000, REGION_128M },
98 { 0x10000000, REGION_256M },
99 { 0x20000000, REGION_512M },
100 { 0x40000000, REGION_1G },
101 { 0x80000000, REGION_2G },
102 { 0x100000000, REGION_4G },
105 /************************** Function Prototypes ******************************/
106 #if defined (__GNUC__)
107 void Init_MPU(void) __attribute__((__section__(".boot")));
108 static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) __attribute__((__section__(".boot")));
109 static void Xil_DisableMPURegions(void) __attribute__((__section__(".boot")));
110 #elif defined (__ICCARM__)
111 #pragma default_function_attributes = @ ".boot"
113 static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib);
114 static void Xil_DisableMPURegions(void);
116 /*****************************************************************************
118 * Initialize MPU for a given address map and Enabled the background Region in
119 * MPU with default memory attributes for rest of address range for Cortex R5
127 ******************************************************************************/
137 Xil_DisableMPURegions();
140 #ifdef XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR
141 /* If the DDR is present, configure region as per DDR size */
142 size = (XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR - XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR) + 1;
143 if (size < 0x80000000) {
144 /* Lookup the size. */
145 for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
146 if (size <= region_size[i].size) {
147 RegSize = region_size[i].encoding;
152 /* if the DDR size is > 2GB, truncate it to 2GB */
156 /* For DDRless system, configure region for TCM */
157 RegSize = REGION_256K;
159 Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
160 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
164 * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL.
165 * 512 MB - LPD-PL interface
166 * 256 MB - FPD-PL (HPM0) interface
167 * 256 MB - FPD-PL (HPM1) interface
171 Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW ;
172 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
175 /* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */
177 RegSize = REGION_512M;
178 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
179 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
182 /* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */
184 RegSize = REGION_256M;
185 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
186 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
189 /* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */
191 RegSize = REGION_16M;
192 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
193 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
196 /* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */
199 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
200 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
203 /* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */
205 RegSize = REGION_16M;
206 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
207 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
210 /* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */
212 RegSize = REGION_16M;
213 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
214 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
218 * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves,
222 RegSize = REGION_16M;
223 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
224 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
227 /* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */
229 RegSize = REGION_256K;
230 Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ;
231 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
233 /* A total of 10 MPU regions are allocated with another 6 being free for users */
237 /*****************************************************************************
239 * Set the memory attributes for a section of memory with starting address addr
240 * of the region size defined by reg_size having attributes attrib of region number
243 * @param addr is the address for which attributes are to be set.
244 * @param attrib specifies the attributes for that memory region.
245 * @param reg_size specifies the size for that memory region.
246 * @param reg_num specifies the number for that memory region.
250 ******************************************************************************/
251 static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib)
253 u32 Local_reg_size = reg_size;
255 Local_reg_size = Local_reg_size<<1U;
256 Local_reg_size |= REGION_EN;
258 mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
260 mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */
261 mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */
262 mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size); /* set the region size and enable it*/
264 isb(); /* synchronize context on this processor */
268 /*****************************************************************************
270 * Disable all the MPU regions if any of them is enabled
277 ******************************************************************************/
278 static void Xil_DisableMPURegions(void)
282 for (Index = 0; Index <= 15; Index++) {
283 mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index);
284 #if defined (__GNUC__)
285 Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
286 #elif defined (__ICCARM__)
287 mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
289 Temp &= (~REGION_EN);
291 mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
298 #if defined (__ICCARM__)
299 #pragma default_function_attributes =