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31 ******************************************************************************/
32 /*****************************************************************************/
37 * This function supports user configurable sleep implementation.
38 * This provides a microsecond delay using the timer specified by the user in
39 * the ARM Cortex R5 MP core.
42 * MODIFICATION HISTORY:
44 * Ver Who Date Changes
45 * ----- -------- -------- -----------------------------------------------
46 * 5.00 pkp 02/20/14 First release
47 * 5.04 pkp 02/19/16 usleep routine is modified to use TTC3 if present
48 * else it will use set of assembly instructions to
49 * provide the required delay
50 * 5.04 pkp 03/09/16 Assembly routine for usleep is modified to avoid
51 * disabling the interrupt
52 * 5.04 pkp 03/11/16 Compare the counter value to previously read value
53 * to detect the overflow for TTC3
54 * 6.0 asa 08/15/16 Updated the usleep signature. Fix for CR#956899.
55 * 6.6 srm 10/18/17 Updated sleep routines to support user configurable
56 * implementation. Now sleep routines will use TTC
57 * instance specified by user.
61 ******************************************************************************/
62 /***************************** Include Files *********************************/
66 #include "xparameters.h"
67 #include "xil_types.h"
68 #include "xpseudo_asm.h"
69 #include "xreg_cortexr5.h"
71 #if defined (SLEEP_TIMER_BASEADDR)
72 #include "xil_sleeptimer.h"
75 /*****************************************************************************/
78 * This API gives a delay in microseconds
80 * @param useconds requested
84 * @note By default, usleep is implemented using TTC3. Although user is
85 * given an option to select other instances of TTC. When the user
86 * selects other instances of TTC, usleep is implemented by that
87 * specific TTC instance. If the user didn't select any other instance
88 * of TTC specifically and when TTC3 is absent, usleep is implemented
89 * using assembly instructions which is tested with instruction and
90 * data caches enabled and it gives proper delay. It may give more
91 * delay than exepcted when caches are disabled. If interrupt comes
92 * when usleep using assembly instruction is being executed, the delay
93 * may be greater than what is expected since once the interrupt is
94 * served count resumes from where it was interrupted unlike the case
95 * of TTC3 where counter keeps running while interrupt is being served.
97 ****************************************************************************/
99 int usleep_R5(unsigned long useconds)
101 #if defined (SLEEP_TIMER_BASEADDR)
102 Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND);
104 #if defined (__GNUC__)
105 __asm__ __volatile__ (
106 #elif defined (__ICCARM__)
115 "subs r3, r3, #0x1\n"
117 "subs r0, r0, #0x1 \n"
120 ::[iter] "r" (ITERS_PER_USEC), [usec] "r" (useconds)